drm/amd/display: Fix null pointer deref error on rotation

[Why&How]
Fix the null pointer dererefence error when rotating the monitor on
a DCN32 variant, which causes a call trace like:

[   42.469548] RIP: 0010:dcn20_program_front_end_for_ctx.cold+0x68/0x435 [amdgpu]
[   42.477140] Code: c1 4c 01 e8 48 8b b0 f0 01 00 00 e8 b6 1c 4c f9 42 f6 84 2b a0 0a 00 00 02 74 30 4d 03 ac 24 68 04 00 00 49 8b 85 f0 01 00 00 <83> b8 50 06 00 00 02 75 18 49 8b bd e0 02 00 00 48 8b 07 48 8b 40
[   42.496225] RSP: 0018:ffffaf744326f6a0 EFLAGS: 00010282
[   42.501539] RAX: 0000000000000000 RBX: ffff948765180000 RCX: 0000000000000000
[   42.508797] RDX: 0000000000000000 RSI: ffffffffbaea5329 RDI: 00000000ffffffff
[   42.516055] RBP: ffff948701674400 R08: 0000000000000000 R09: ffffaf744326f538
[   42.523312] R10: 0000000000000003 R11: ffff948a1d33ffe8 R12: ffff948708700000
[   42.530569] R13: ffff94876e901180 R14: 0000000000000002 R15: 0000000000000001
[   42.537825] FS:  00007f1c7c04a5c0(0000) GS:ffff948a05a80000(0000) knlGS:0000000000000000
[   42.546055] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   42.551898] CR2: 0000000000000650 CR3: 0000000127dd6000 CR4: 00000000003506e0
[   42.559155] Call Trace:
[   42.561645]  <TASK>
[   42.563782]  commit_planes_for_stream+0x8b1/0x1410 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46]
[   42.573298]  dc_update_planes_and_stream+0x3f9/0x9f0 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46]
[   42.582986]  amdgpu_dm_atomic_commit_tail+0x19be/0x3270 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46]
[   42.592944]  ? vsnprintf+0x35e/0x550
[   42.596593]  commit_tail+0x94/0x130
[   42.600146]  drm_atomic_helper_commit+0x112/0x140
[   42.604931]  drm_atomic_commit+0x96/0xc0
[   42.608922]  ? drm_plane_get_damage_clips.cold+0x1c/0x1c
[   42.614326]  drm_mode_atomic_ioctl+0x97b/0xb90
[   42.618848]  ? drm_atomic_set_property+0xb40/0xb40
[   42.623633]  drm_ioctl_kernel+0xc9/0x170
[   42.627694]  drm_ioctl+0x22f/0x410
[   42.631157]  ? drm_atomic_set_property+0xb40/0xb40
[   42.636031]  amdgpu_drm_ioctl+0x4a/0x80 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46]
[   42.644537]  __x64_sys_ioctl+0x90/0xd0
[   42.648355]  do_syscall_64+0x5b/0x80
[   42.651992]  ? do_syscall_64+0x67/0x80
[   42.655808]  ? exit_to_user_mode_prepare+0x1e/0x140
[   42.660773]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[   42.665913] RIP: 0033:0x7f1c7f31aaff
[   42.669550] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <41> 89 c0 3d 00 f0 ff ff 77 1f 48 8b 44 24 18 64 48 2b 04 25 28 00
[   42.688635] RSP: 002b:00007fff29eca1a0 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
[   42.696334] RAX: ffffffffffffffda RBX: 00007fff29eca250 RCX: 00007f1c7f31aaff
[   42.703591] RDX: 00007fff29eca250 RSI: 00000000c03864bc RDI: 0000000000000009
[   42.710848] RBP: 00000000c03864bc R08: 000000000000000e R09: 000000000000000e
[   42.718104] R10: 0000000000000007 R11: 0000000000000246 R12: 00005643f0991d70
[   42.725361] R13: 0000000000000009 R14: 00005643f22d0c50 R15: 00005643f0a74550
[   42.732621]  </TASK>
Reviewed-by: Samson Tam <Samson.Tam@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

@@ -1826,15 +1826,17 @@ void dcn20_program_front_end_for_ctx(
 	/* When disabling phantom pipes, turn on phantom OTG first (so we can get double
 	 * buffer updates properly)
 	 */
-	for (i = 0; i < dc->res_pool->pipe_count; i++)
-		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
-				&& dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;
+
+		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&
+			dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
 			struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
 
 			if (tg->funcs->enable_crtc)
 				tg->funcs->enable_crtc(tg);
 		}
-
+	}
 	/* OTG blank before disabling all front ends */
 	for (i = 0; i < dc->res_pool->pipe_count; i++)
 		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable