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Commit af34a16d authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Remove info metrics erroneously in TopdownL1 

Bug affected server metrics only. This doesn't impact default metrics
but if the TopdownL1 metric group is specified. Passes on the fix in:

  https://github.com/intel/perfmon/commit/b09f0a3953234ec592b4a872b87764c78da05d8bReviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Link: https://lore.kernel.org/r/20240321060016.1464787-13-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 7bce27f8
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Showing with 181 additions and 273 deletions
tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
View file @ af34a16d
......@@ -732,9 +732,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_data_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "",
......@@ -745,9 +744,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
......@@ -764,9 +762,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
......@@ -807,9 +804,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
......@@ -838,16 +834,14 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
"MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_miss_latency",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_Lat;Offcore",
"MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
......@@ -867,9 +861,8 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "tma_info_memory_tlb_page_walks_utilization",
"MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_page_walks_utilization",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
......
tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
View file @ af34a16d
......@@ -618,9 +618,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_data_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "",
......@@ -631,9 +630,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
......@@ -650,9 +648,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
......@@ -669,9 +666,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
......@@ -700,16 +696,14 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
"MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_miss_latency",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_Lat;Offcore",
"MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
......@@ -729,9 +723,8 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "tma_info_memory_tlb_page_walks_utilization",
"MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_page_walks_utilization",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
......
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