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Commit b0f392c6 authored by Tony Lindgren's avatar Tony Lindgren
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Merge tag 'omap-devel-a-for-3.11' of... 

Merge tag 'omap-devel-a-for-3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.11/omap5

Add support for the OMAP5 SoC family.

As part of the transition to DT, no board files will be used
for OMAP5.  The hwmod data is gradually being transitioned
away from arch/arm/mach-omap2: IRQ, DMA, and memory map data
has been moved to DT.  Hopefully the dev_attr and clock role
data will be the next step.

Basic test logs are available here, although not for OMAP5,
since I don't have an OMAP5 board:
http://www.pwsan.com/omap/testlogs/omap5_v3.10/20130608130949/
parents 317ddd25 e4020aa9
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arch/arm/mach-omap2/Makefile
View file @ b0f392c6
......@@ -127,6 +127,7 @@ obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
......@@ -141,6 +142,7 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
......@@ -156,6 +158,7 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
......@@ -198,6 +201,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o
......
arch/arm/mach-omap2/clockdomain.h
View file @ b0f392c6
......@@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
extern void clkdm_del_autodeps(struct clockdomain *clkdm);
......
arch/arm/mach-omap2/clockdomains54xx_data.c 0 → 100644
View file @ b0f392c6
/*
* OMAP54XX Clock domains framework
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com)
* Paul Walmsley (paul@pwsan.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include "clockdomain.h"
#include "cm1_54xx.h"
#include "cm2_54xx.h"
#include "cm-regbits-54xx.h"
#include "prm54xx.h"
#include "prcm44xx.h"
#include "prcm_mpu54xx.h"
/* Static Dependencies for OMAP4 Clock Domains */
static struct clkdm_dep c2c_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ NULL },
};
static struct clkdm_dep cam_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ NULL },
};
static struct clkdm_dep dma_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep dsp_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep dss_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ NULL },
};
static struct clkdm_dep gpu_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ NULL },
};
static struct clkdm_dep ipu_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "dsp_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "gpu_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep iva_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ NULL },
};
static struct clkdm_dep l3init_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ NULL },
};
static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ NULL },
};
static struct clkdm_dep mpu_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "dsp_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "gpu_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clockdomain l4sec_54xx_clkdm = {
.name = "l4sec_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
.dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT,
.wkdep_srcs = l4sec_wkup_sleep_deps,
.sleepdep_srcs = l4sec_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain iva_54xx_clkdm = {
.name = "iva_clkdm",
.pwrdm = { .name = "iva_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_IVA_INST,
.clkdm_offs = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
.dep_bit = OMAP54XX_IVA_STATDEP_SHIFT,
.wkdep_srcs = iva_wkup_sleep_deps,
.sleepdep_srcs = iva_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain mipiext_54xx_clkdm = {
.name = "mipiext_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
.wkdep_srcs = mipiext_wkup_sleep_deps,
.sleepdep_srcs = mipiext_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain l3main2_54xx_clkdm = {
.name = "l3main2_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
.dep_bit = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
};
static struct clockdomain l3main1_54xx_clkdm = {
.name = "l3main1_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
.dep_bit = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
};
static struct clockdomain custefuse_54xx_clkdm = {
.name = "custefuse_clkdm",
.pwrdm = { .name = "custefuse_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain ipu_54xx_clkdm = {
.name = "ipu_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
.dep_bit = OMAP54XX_IPU_STATDEP_SHIFT,
.wkdep_srcs = ipu_wkup_sleep_deps,
.sleepdep_srcs = ipu_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain l4cfg_54xx_clkdm = {
.name = "l4cfg_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
.dep_bit = OMAP54XX_L4CFG_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
};
static struct clockdomain abe_54xx_clkdm = {
.name = "abe_clkdm",
.pwrdm = { .name = "abe_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_AON_ABE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
.dep_bit = OMAP54XX_ABE_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain dss_54xx_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "dss_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_DSS_INST,
.clkdm_offs = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
.dep_bit = OMAP54XX_DSS_STATDEP_SHIFT,
.wkdep_srcs = dss_wkup_sleep_deps,
.sleepdep_srcs = dss_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain dsp_54xx_clkdm = {
.name = "dsp_clkdm",
.pwrdm = { .name = "dsp_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_AON_DSP_INST,
.clkdm_offs = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
.dep_bit = OMAP54XX_DSP_STATDEP_SHIFT,
.wkdep_srcs = dsp_wkup_sleep_deps,
.sleepdep_srcs = dsp_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain c2c_54xx_clkdm = {
.name = "c2c_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
.wkdep_srcs = c2c_wkup_sleep_deps,
.sleepdep_srcs = c2c_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain l4per_54xx_clkdm = {
.name = "l4per_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
.dep_bit = OMAP54XX_L4PER_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain gpu_54xx_clkdm = {
.name = "gpu_clkdm",
.pwrdm = { .name = "gpu_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_GPU_INST,
.clkdm_offs = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
.dep_bit = OMAP54XX_GPU_STATDEP_SHIFT,
.wkdep_srcs = gpu_wkup_sleep_deps,
.sleepdep_srcs = gpu_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain wkupaon_54xx_clkdm = {
.name = "wkupaon_clkdm",
.pwrdm = { .name = "wkupaon_pwrdm" },
.prcm_partition = OMAP54XX_PRM_PARTITION,
.cm_inst = OMAP54XX_PRM_WKUPAON_CM_INST,
.clkdm_offs = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
.dep_bit = OMAP54XX_WKUPAON_STATDEP_SHIFT,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain mpu0_54xx_clkdm = {
.name = "mpu0_clkdm",
.pwrdm = { .name = "cpu0_pwrdm" },
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.cm_inst = OMAP54XX_PRCM_MPU_CM_C0_INST,
.clkdm_offs = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain mpu1_54xx_clkdm = {
.name = "mpu1_clkdm",
.pwrdm = { .name = "cpu1_pwrdm" },
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.cm_inst = OMAP54XX_PRCM_MPU_CM_C1_INST,
.clkdm_offs = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain coreaon_54xx_clkdm = {
.name = "coreaon_clkdm",
.pwrdm = { .name = "coreaon_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_COREAON_INST,
.clkdm_offs = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain mpu_54xx_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_AON_MPU_INST,
.clkdm_offs = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
.wkdep_srcs = mpu_wkup_sleep_deps,
.sleepdep_srcs = mpu_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain l3init_54xx_clkdm = {
.name = "l3init_clkdm",
.pwrdm = { .name = "l3init_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_L3INIT_INST,
.clkdm_offs = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
.dep_bit = OMAP54XX_L3INIT_STATDEP_SHIFT,
.wkdep_srcs = l3init_wkup_sleep_deps,
.sleepdep_srcs = l3init_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain dma_54xx_clkdm = {
.name = "dma_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
.wkdep_srcs = dma_wkup_sleep_deps,
.sleepdep_srcs = dma_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain l3instr_54xx_clkdm = {
.name = "l3instr_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
};
static struct clockdomain emif_54xx_clkdm = {
.name = "emif_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
.dep_bit = OMAP54XX_EMIF_STATDEP_SHIFT,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain emu_54xx_clkdm = {
.name = "emu_clkdm",
.pwrdm = { .name = "emu_pwrdm" },
.prcm_partition = OMAP54XX_PRM_PARTITION,
.cm_inst = OMAP54XX_PRM_EMU_CM_INST,
.clkdm_offs = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain cam_54xx_clkdm = {
.name = "cam_clkdm",
.pwrdm = { .name = "cam_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CAM_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
.wkdep_srcs = cam_wkup_sleep_deps,
.sleepdep_srcs = cam_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
/* As clockdomains are added or removed above, this list must also be changed */
static struct clockdomain *clockdomains_omap54xx[] __initdata = {
&l4sec_54xx_clkdm,
&iva_54xx_clkdm,
&mipiext_54xx_clkdm,
&l3main2_54xx_clkdm,
&l3main1_54xx_clkdm,
&custefuse_54xx_clkdm,
&ipu_54xx_clkdm,
&l4cfg_54xx_clkdm,
&abe_54xx_clkdm,
&dss_54xx_clkdm,
&dsp_54xx_clkdm,
&c2c_54xx_clkdm,
&l4per_54xx_clkdm,
&gpu_54xx_clkdm,
&wkupaon_54xx_clkdm,
&mpu0_54xx_clkdm,
&mpu1_54xx_clkdm,
&coreaon_54xx_clkdm,
&mpu_54xx_clkdm,
&l3init_54xx_clkdm,
&dma_54xx_clkdm,
&l3instr_54xx_clkdm,
&emif_54xx_clkdm,
&emu_54xx_clkdm,
&cam_54xx_clkdm,
NULL
};
void __init omap54xx_clockdomains_init(void)
{
clkdm_register_platform_funcs(&omap4_clkdm_operations);
clkdm_register_clkdms(clockdomains_omap54xx);
clkdm_complete_init();
}
arch/arm/mach-omap2/cm-regbits-54xx.h 0 → 100644
View file @ b0f392c6
/*
* OMAP54xx Clock Management register bits
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */
#define OMAP54XX_ABE_DYNDEP_SHIFT 3
#define OMAP54XX_ABE_DYNDEP_WIDTH 0x1
#define OMAP54XX_ABE_DYNDEP_MASK (1 << 3)
/*
* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
* CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_ABE_STATDEP_SHIFT 3
#define OMAP54XX_ABE_STATDEP_WIDTH 0x1
#define OMAP54XX_ABE_STATDEP_MASK (1 << 3)
/*
* Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA,
* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1,
* CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB
*/
#define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0
#define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3
#define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_C2C_DYNDEP_SHIFT 18
#define OMAP54XX_C2C_DYNDEP_WIDTH 0x1
#define OMAP54XX_C2C_DYNDEP_MASK (1 << 18)
/* Used by CM_MPU_STATICDEP */
#define OMAP54XX_C2C_STATDEP_SHIFT 18
#define OMAP54XX_C2C_STATDEP_WIDTH 0x1
#define OMAP54XX_C2C_STATDEP_MASK (1 << 18)
/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_CAM_DYNDEP_SHIFT 9
#define OMAP54XX_CAM_DYNDEP_WIDTH 0x1
#define OMAP54XX_CAM_DYNDEP_MASK (1 << 9)
/*
* Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
* CM_MPU_STATICDEP
*/
#define OMAP54XX_CAM_STATDEP_SHIFT 9
#define OMAP54XX_CAM_STATDEP_WIDTH 0x1
#define OMAP54XX_CAM_STATDEP_MASK (1 << 9)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13)
/* Used by CM_C2C_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9)
/* Used by CM_C2C_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10)
/* Used by CM_C2C_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14
#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9)
/* Used by CM_CUSTEFUSE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8)
/* Used by CM_CUSTEFUSE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9)
/* Used by CM_EMIF_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9)
/* Used by CM_DMA_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8)
/* Used by CM_DSP_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10)
/* Used by CM_EMIF_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8)
/* Used by CM_EMIF_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11)
/* Used by CM_EMIF_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10)
/* Used by CM_EMU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
/* Used by CM_GPU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9)
/* Used by CM_GPU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10)
/* Used by CM_GPU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6
#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7
#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16
#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16)
/* Used by CM_IPU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8)
/* Used by CM_IVA_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11)
/* Used by CM_L3INSTR_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9)
/* Used by CM_L3INSTR_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8)
/* Used by CM_L3INSTR_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10)
/* Used by CM_L3MAIN1_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8)
/* Used by CM_L3MAIN2_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8)
/* Used by CM_L4CFG_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8)
/* Used by CM_L4SEC_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8)
/* Used by CM_L4SEC_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9)
/* Used by CM_MIPIEXT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8)
/* Used by CM_MIPIEXT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2
#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17
#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18
#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18)
/* Used by CM_MPU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14
#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15
#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15
#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19
#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15
#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14
#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14
#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
/* Used by CM_MIPIEXT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10)
/* Used by CM_MIPIEXT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13)
/* Used by CM_MIPIEXT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31
#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13)
/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8
#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1
#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8)
/*
* Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
* CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
* CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
* CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
*/
#define OMAP54XX_CLKSEL_SHIFT 24
#define OMAP54XX_CLKSEL_WIDTH 0x1
#define OMAP54XX_CLKSEL_MASK (1 << 24)
/*
* Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF,
* CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON
*/
#define OMAP54XX_CLKSEL_0_0_SHIFT 0
#define OMAP54XX_CLKSEL_0_0_WIDTH 0x1
#define OMAP54XX_CLKSEL_0_0_MASK (1 << 0)
/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
#define OMAP54XX_CLKSEL_0_1_SHIFT 0
#define OMAP54XX_CLKSEL_0_1_WIDTH 0x2
#define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0)
/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
#define OMAP54XX_CLKSEL_24_25_SHIFT 24
#define OMAP54XX_CLKSEL_24_25_WIDTH 0x2
#define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24)
/* Used by CM_MPU_MPU_CLKCTRL */
#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26
#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
/* Used by CM_ABE_AESS_CLKCTRL */
#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24
#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1
#define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24)
/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */
#define OMAP54XX_CLKSEL_DIV_SHIFT 25
#define OMAP54XX_CLKSEL_DIV_WIDTH 0x1
#define OMAP54XX_CLKSEL_DIV_MASK (1 << 25)
/* Used by CM_MPU_MPU_CLKCTRL */
#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2
#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24)
/* Used by CM_CAM_FDIF_CLKCTRL */
#define OMAP54XX_CLKSEL_FCLK_SHIFT 24
#define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1
#define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24)
/* Used by CM_GPU_GPU_CLKCTRL */
#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24
#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1
#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
/* Used by CM_GPU_GPU_CLKCTRL */
#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25
#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1
#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
/* Used by CM_GPU_GPU_CLKCTRL */
#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26
#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1
#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26)
/*
* Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
* CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
*/
#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26
#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2
#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26)
/* Used by CM_CLKSEL_CORE */
#define OMAP54XX_CLKSEL_L3_SHIFT 4
#define OMAP54XX_CLKSEL_L3_WIDTH 0x1
#define OMAP54XX_CLKSEL_L3_MASK (1 << 4)
/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1
#define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1
#define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1)
/* Used by CM_CLKSEL_CORE */
#define OMAP54XX_CLKSEL_L4_SHIFT 8
#define OMAP54XX_CLKSEL_L4_WIDTH 0x1
#define OMAP54XX_CLKSEL_L4_MASK (1 << 8)
/* Used by CM_EMIF_EMIF1_CLKCTRL */
#define OMAP54XX_CLKSEL_LL_SHIFT 24
#define OMAP54XX_CLKSEL_LL_WIDTH 0x1
#define OMAP54XX_CLKSEL_LL_MASK (1 << 24)
/* Used by CM_CLKSEL_ABE */
#define OMAP54XX_CLKSEL_OPP_SHIFT 0
#define OMAP54XX_CLKSEL_OPP_WIDTH 0x2
#define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0)
/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */
#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24
#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1
#define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24)
/*
* Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
* CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
*/
#define OMAP54XX_CLKSEL_SOURCE_SHIFT 24
#define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2
#define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24)
/*
* Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL,
* CM_L3INIT_MMC2_CLKCTRL
*/
#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24
#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1
#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24
#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1
#define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25
#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1
#define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25)
/*
* Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
* CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
* CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
* CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
* CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE,
* CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER,
* CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB,
* CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP54XX_CLKST_SHIFT 9
#define OMAP54XX_CLKST_WIDTH 0x1
#define OMAP54XX_CLKST_MASK (1 << 9)
/*
* Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL,
* CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL,
* CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
* CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
* CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL,
* CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
* CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
*/
#define OMAP54XX_CLKTRCTRL_SHIFT 0
#define OMAP54XX_CLKTRCTRL_WIDTH 0x2
#define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0)
/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
#define OMAP54XX_CLKX2ST_SHIFT 11
#define OMAP54XX_CLKX2ST_WIDTH 0x1
#define OMAP54XX_CLKX2ST_MASK (1 << 11)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_COREAON_DYNDEP_SHIFT 16
#define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1
#define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16)
/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_COREAON_STATDEP_SHIFT 16
#define OMAP54XX_COREAON_STATDEP_WIDTH 0x1
#define OMAP54XX_COREAON_STATDEP_MASK (1 << 16)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17
#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1
#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17)
/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17
#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1
#define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_CUSTOM_SHIFT 6
#define OMAP54XX_CUSTOM_WIDTH 0x2
#define OMAP54XX_CUSTOM_MASK (0x3 << 6)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
*/
#define OMAP54XX_DCC_EN_SHIFT 22
#define OMAP54XX_DCC_EN_WIDTH 0x1
#define OMAP54XX_DCC_EN_MASK (1 << 22)
/*
* Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS,
* CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS,
* CM_CORE_AON_DEBUG_L4SEC_FD_TRANS
*/
#define OMAP54XX_CM_DEBUG_OUT_SHIFT 0
#define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd
#define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS,
* CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20
#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS,
* CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9
#define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS,
* CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5
#define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS,
* CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6
#define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS,
* CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb
#define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS,
* CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7
#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0)
/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */
#define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14
#define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0)
/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */
#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa
#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0)
/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */
#define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b
#define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0)
/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */
#define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe
#define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0)
/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */
#define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16
#define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0)
/*
* Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
* CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
* CM_SSC_DELTAMSTEP_DPLL_PER
*/
#define OMAP54XX_DELTAMSTEP_SHIFT 0
#define OMAP54XX_DELTAMSTEP_WIDTH 0x14
#define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0)
/*
* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1,
* CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB
*/
#define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0
#define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15
#define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
/*
* Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
* CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
* CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
* CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
* CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
*/
#define OMAP54XX_DIVHS_SHIFT 0
#define OMAP54XX_DIVHS_WIDTH 0x6
#define OMAP54XX_DIVHS_MASK (0x3f << 0)
/*
* Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
* CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE,
* CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP54XX_DIVHS_0_4_SHIFT 0
#define OMAP54XX_DIVHS_0_4_WIDTH 0x5
#define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0)
/*
* Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2,
* CM_DIV_M2_DPLL_USB
*/
#define OMAP54XX_DIVHS_0_6_SHIFT 0
#define OMAP54XX_DIVHS_0_6_WIDTH 0x7
#define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0)
/* Used by CM_DLL_CTRL */
#define OMAP54XX_DLL_OVERRIDE_SHIFT 0
#define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1
#define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0)
/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2
#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1
#define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP54XX_DLL_RESET_SHIFT 3
#define OMAP54XX_DLL_RESET_WIDTH 0x1
#define OMAP54XX_DLL_RESET_MASK (1 << 3)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
*/
#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23
#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1
#define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
/* Used by CM_CLKSEL_DPLL_CORE */
#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8
#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3
#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
/* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2
#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6
#define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11
#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5
#define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
*/
#define OMAP54XX_DPLL_DIV_SHIFT 0
#define OMAP54XX_DPLL_DIV_WIDTH 0x7
#define OMAP54XX_DPLL_DIV_MASK (0x7f << 0)
/*
* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1,
* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
*/
#define OMAP54XX_DPLL_DIV_0_7_SHIFT 0
#define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8
#define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8
#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1
#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
*/
#define OMAP54XX_DPLL_EN_SHIFT 0
#define OMAP54XX_DPLL_EN_WIDTH 0x3
#define OMAP54XX_DPLL_EN_MASK (0x7 << 0)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10
#define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1
#define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
*/
#define OMAP54XX_DPLL_MULT_SHIFT 8
#define OMAP54XX_DPLL_MULT_WIDTH 0xb
#define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8)
/*
* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1,
* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
*/
#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8
#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc
#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define OMAP54XX_DPLL_REGM4XEN_SHIFT 11
#define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1
#define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11)
/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
#define OMAP54XX_DPLL_SD_DIV_SHIFT 24
#define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8
#define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24)
/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
#define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21
#define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1
#define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
*/
#define OMAP54XX_DPLL_SSC_ACK_SHIFT 13
#define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1
#define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
*/
#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
*/
#define OMAP54XX_DPLL_SSC_EN_SHIFT 12
#define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1
#define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_DSP_DYNDEP_SHIFT 1
#define OMAP54XX_DSP_DYNDEP_WIDTH 0x1
#define OMAP54XX_DSP_DYNDEP_MASK (1 << 1)
/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_DSP_STATDEP_SHIFT 1
#define OMAP54XX_DSP_STATDEP_WIDTH 0x1
#define OMAP54XX_DSP_STATDEP_MASK (1 << 1)
/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP54XX_DSS_DYNDEP_SHIFT 8
#define OMAP54XX_DSS_DYNDEP_WIDTH 0x1
#define OMAP54XX_DSS_DYNDEP_MASK (1 << 8)
/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_DSS_STATDEP_SHIFT 8
#define OMAP54XX_DSS_STATDEP_WIDTH 0x1
#define OMAP54XX_DSS_STATDEP_MASK (1 << 8)
/*
* Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP
*/
#define OMAP54XX_EMIF_DYNDEP_SHIFT 4
#define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1
#define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4)
/*
* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
* CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_EMIF_STATDEP_SHIFT 4
#define OMAP54XX_EMIF_STATDEP_WIDTH 0x1
#define OMAP54XX_EMIF_STATDEP_MASK (1 << 4)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP54XX_FREQ_UPDATE_SHIFT 0
#define OMAP54XX_FREQ_UPDATE_WIDTH 0x1
#define OMAP54XX_FREQ_UPDATE_MASK (1 << 0)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_FUNC_SHIFT 16
#define OMAP54XX_FUNC_WIDTH 0xc
#define OMAP54XX_FUNC_MASK (0xfff << 16)
/* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0
#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1
#define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0)
/* Used by CM_L3MAIN2_DYNAMICDEP */
#define OMAP54XX_GPU_DYNDEP_SHIFT 10
#define OMAP54XX_GPU_DYNDEP_WIDTH 0x1
#define OMAP54XX_GPU_DYNDEP_MASK (1 << 10)
/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_GPU_STATDEP_SHIFT 10
#define OMAP54XX_GPU_STATDEP_WIDTH 0x1
#define OMAP54XX_GPU_STATDEP_MASK (1 << 10)
/*
* Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
* CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
* CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
* CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
* CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
* CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
* CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
* CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
* CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
* CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
* CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
* CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
* CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
* CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
* CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
* CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
* CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
* CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
* CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
* CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
* CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
* CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
* CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
* CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
* CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
* CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
* CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
* CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
* CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
* CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
* CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
* CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
* CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
* CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
* CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
* CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
* CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
* CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
* CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
* CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
* CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
* CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
* CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
*/
#define OMAP54XX_IDLEST_SHIFT 16
#define OMAP54XX_IDLEST_WIDTH 0x2
#define OMAP54XX_IDLEST_MASK (0x3 << 16)
/* Used by CM_L3MAIN2_DYNAMICDEP */
#define OMAP54XX_IPU_DYNDEP_SHIFT 0
#define OMAP54XX_IPU_DYNDEP_WIDTH 0x1
#define OMAP54XX_IPU_DYNDEP_MASK (1 << 0)
/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_IPU_STATDEP_SHIFT 0
#define OMAP54XX_IPU_STATDEP_WIDTH 0x1
#define OMAP54XX_IPU_STATDEP_MASK (1 << 0)
/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */
#define OMAP54XX_IVA_DYNDEP_SHIFT 2
#define OMAP54XX_IVA_DYNDEP_WIDTH 0x1
#define OMAP54XX_IVA_DYNDEP_MASK (1 << 2)
/*
* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
* CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_IVA_STATDEP_SHIFT 2
#define OMAP54XX_IVA_STATDEP_WIDTH 0x1
#define OMAP54XX_IVA_STATDEP_MASK (1 << 2)
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP54XX_L3INIT_DYNDEP_SHIFT 7
#define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1
#define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7)
/*
* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
* CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_L3INIT_STATDEP_SHIFT 7
#define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1
#define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7)
/*
* Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
* CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP
*/
#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5
#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1
#define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5)
/*
* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
* CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5
#define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1
#define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5)
/*
* Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP,
* CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP,
* CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP
*/
#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6
#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1
#define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6)
/*
* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
* CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6
#define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1
#define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6)
/* Used by CM_L3MAIN1_DYNAMICDEP */
#define OMAP54XX_L4CFG_DYNDEP_SHIFT 12
#define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1
#define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12)
/*
* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
* CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_L4CFG_STATDEP_SHIFT 12
#define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1
#define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12)
/* Used by CM_L3MAIN2_DYNAMICDEP */
#define OMAP54XX_L4PER_DYNDEP_SHIFT 13
#define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1
#define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13)
/*
* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
* CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_L4PER_STATDEP_SHIFT 13
#define OMAP54XX_L4PER_STATDEP_WIDTH 0x1
#define OMAP54XX_L4PER_STATDEP_MASK (1 << 13)
/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP54XX_L4SEC_DYNDEP_SHIFT 14
#define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1
#define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14)
/*
* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP,
* CM_MPU_STATICDEP
*/
#define OMAP54XX_L4SEC_STATDEP_SHIFT 14
#define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1
#define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14)
/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21
#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1
#define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21)
/* Used by CM_MPU_STATICDEP */
#define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21
#define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1
#define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
* CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
*/
#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8
#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3
#define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
* CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
*/
#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0
#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7
#define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
/*
* Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
* CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
* CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
* CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
* CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
* CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
* CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
* CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
* CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
* CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
* CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
* CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
* CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
* CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
* CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
* CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
* CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
* CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
* CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
* CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
* CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
* CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
* CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
* CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
* CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
* CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
* CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
* CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
* CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
* CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
* CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
* CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
* CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
* CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
* CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
* CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
* CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
* CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
* CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
* CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
* CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
* CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
* CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
*/
#define OMAP54XX_MODULEMODE_SHIFT 0
#define OMAP54XX_MODULEMODE_WIDTH 0x2
#define OMAP54XX_MODULEMODE_MASK (0x3 << 0)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_MPU_DYNDEP_SHIFT 19
#define OMAP54XX_MPU_DYNDEP_WIDTH 0x1
#define OMAP54XX_MPU_DYNDEP_MASK (1 << 19)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11)
/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9
#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8
#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8)
/* Used by CM_CAM_ISS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
/*
* Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
* CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
* CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
*/
#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8)
/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8)
/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8
#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8)
/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9
#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9)
/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10
#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15
#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7
#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6
#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6)
/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8
#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8)
/* Used by CM_L3INIT_SATA_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8)
/* Used by CM_WKUPAON_SCRM_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8
#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
/* Used by CM_WKUPAON_SCRM_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9
#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9)
/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11
#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10
#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
/* Used by CM_MIPIEXT_LLI_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8)
/* Used by CM_MIPIEXT_LLI_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9
#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */
#define OMAP54XX_OUTPUT_SHIFT 0
#define OMAP54XX_OUTPUT_WIDTH 0x20
#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0)
/* Used by CM_CLKSEL_ABE */
#define OMAP54XX_PAD_CLKS_GATE_SHIFT 8
#define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1
#define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8)
/* Used by CM_RESTORE_ST */
#define OMAP54XX_PHASE1_COMPLETED_SHIFT 0
#define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1
#define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0)
/* Used by CM_RESTORE_ST */
#define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1
#define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1
#define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1)
/* Used by CM_RESTORE_ST */
#define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2
#define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1
#define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2)
/* Used by CM_DYN_DEP_PRESCAL */
#define OMAP54XX_PRESCAL_SHIFT 0
#define OMAP54XX_PRESCAL_WIDTH 0x6
#define OMAP54XX_PRESCAL_MASK (0x3f << 0)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_R_RTL_SHIFT 11
#define OMAP54XX_R_RTL_WIDTH 0x5
#define OMAP54XX_R_RTL_MASK (0x1f << 11)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */
#define OMAP54XX_SAR_MODE_SHIFT 4
#define OMAP54XX_SAR_MODE_WIDTH 0x1
#define OMAP54XX_SAR_MODE_MASK (1 << 4)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_SCHEME_SHIFT 30
#define OMAP54XX_SCHEME_WIDTH 0x2
#define OMAP54XX_SCHEME_MASK (0x3 << 30)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_SDMA_DYNDEP_SHIFT 11
#define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1
#define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11)
/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_SDMA_STATDEP_SHIFT 11
#define OMAP54XX_SDMA_STATDEP_WIDTH 0x1
#define OMAP54XX_SDMA_STATDEP_MASK (1 << 11)
/* Used by CM_CORE_AON_DEBUG_CFG */
#define OMAP54XX_SEL0_SHIFT 0
#define OMAP54XX_SEL0_WIDTH 0x7
#define OMAP54XX_SEL0_MASK (0x7f << 0)
/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
#define OMAP54XX_SEL0_0_7_SHIFT 0
#define OMAP54XX_SEL0_0_7_WIDTH 0x8
#define OMAP54XX_SEL0_0_7_MASK (0xff << 0)
/* Used by CM_CORE_AON_DEBUG_CFG */
#define OMAP54XX_SEL1_SHIFT 8
#define OMAP54XX_SEL1_WIDTH 0x7
#define OMAP54XX_SEL1_MASK (0x7f << 8)
/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8
#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8
#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8)
/* Used by CM_CORE_AON_DEBUG_CFG */
#define OMAP54XX_SEL2_SHIFT 16
#define OMAP54XX_SEL2_WIDTH 0x7
#define OMAP54XX_SEL2_MASK (0x7f << 16)
/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16
#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8
#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16)
/* Used by CM_CORE_AON_DEBUG_CFG */
#define OMAP54XX_SEL3_SHIFT 24
#define OMAP54XX_SEL3_WIDTH 0x7
#define OMAP54XX_SEL3_MASK (0x7f << 24)
/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24
#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8
#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24)
/* Used by CM_CLKSEL_ABE */
#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10
#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1
#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10)
/*
* Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
* CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL,
* CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
* CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL,
* CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
* CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL,
* CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL,
* CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL,
* CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL
*/
#define OMAP54XX_STBYST_SHIFT 18
#define OMAP54XX_STBYST_WIDTH 0x1
#define OMAP54XX_STBYST_MASK (1 << 18)
/*
* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
* CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
*/
#define OMAP54XX_ST_DPLL_CLK_SHIFT 0
#define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1
#define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0)
/*
* Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2,
* CM_CLKDCOLDO_DPLL_USB
*/
#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9
#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1
#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
/*
* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
* CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
*/
#define OMAP54XX_ST_DPLL_INIT_SHIFT 4
#define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1
#define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4)
/*
* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
* CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
*/
#define OMAP54XX_ST_DPLL_MODE_SHIFT 1
#define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3
#define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1)
/* Used by CM_CLKSEL_SYS */
#define OMAP54XX_SYS_CLKSEL_SHIFT 0
#define OMAP54XX_SYS_CLKSEL_WIDTH 0x3
#define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0)
/*
* Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP,
* CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP,
* CM_MPU_DYNAMICDEP
*/
#define OMAP54XX_WINDOWSIZE_SHIFT 24
#define OMAP54XX_WINDOWSIZE_WIDTH 0x4
#define OMAP54XX_WINDOWSIZE_MASK (0xf << 24)
/* Used by CM_L3MAIN1_DYNAMICDEP */
#define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15
#define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1
#define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15)
/*
* Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
* CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_WKUPAON_STATDEP_SHIFT 15
#define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1
#define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_X_MAJOR_SHIFT 8
#define OMAP54XX_X_MAJOR_WIDTH 0x3
#define OMAP54XX_X_MAJOR_MASK (0x7 << 8)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_Y_MINOR_SHIFT 0
#define OMAP54XX_Y_MINOR_WIDTH 0x6
#define OMAP54XX_Y_MINOR_MASK (0x3f << 0)
#endif
arch/arm/mach-omap2/cm1_44xx.h
View file @ b0f392c6
......@@ -25,6 +25,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
#include "cm_44xx_54xx.h"
/* CM1 base address */
#define OMAP4430_CM1_BASE 0x4a004000
......@@ -217,9 +219,4 @@
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
/* Function prototypes */
extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
#endif
arch/arm/mach-omap2/cm1_54xx.h 0 → 100644
View file @ b0f392c6
/*
* OMAP54xx CM1 instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
#include "cm_44xx_54xx.h"
/* CM1 base address */
#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
/* CM_CORE_AON instances */
#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
#define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
#define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
#define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
#define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
#define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
#define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
/* CM_CORE_AON clockdomain register offsets (from instance start) */
#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000
/* CM_CORE_AON */
/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
#define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000
#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
#define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080
#define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084
#define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090
#define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094
#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098
#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c
#define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0
#define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4
#define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8
#define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac
#define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0
#define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4
#define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8
#define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc
#define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0
#define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4
#define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8
#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc
#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0
#define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4
#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8
#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc
#define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0
#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4
#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8
#define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec
#define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0
/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
#define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000
#define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000)
#define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008
#define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008)
#define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010
#define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
#define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020)
#define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
#define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024)
#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028)
#define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
#define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c)
#define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
#define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030)
#define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
#define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034)
#define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
#define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038)
#define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
#define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c)
#define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
#define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040)
#define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
#define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
#define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
#define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050)
#define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
#define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054)
#define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
#define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058)
#define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
#define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c)
#define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
#define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060)
#define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
#define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064)
#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068)
#define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
#define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c)
#define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
#define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
#define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
#define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c)
#define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
#define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
#define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
#define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
#define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
#define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
#define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8
#define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8)
#define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc
#define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
#define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
#define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
#define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
#define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
#define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
#define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
#define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
#define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
#define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
#define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
#define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
#define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
#define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
#define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
#define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
#define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180
/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
#define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004
#define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020)
#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028)
/* CM_CORE_AON.DSP_CM_CORE_AON register offsets */
#define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004
#define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020)
/* CM_CORE_AON.ABE_CM_CORE_AON register offsets */
#define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020)
#define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028
#define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028)
#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030
#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030)
#define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038
#define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038)
#define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040
#define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040)
#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048)
#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050)
#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058)
#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060
#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060)
#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068)
#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070)
#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078)
#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080)
#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088
#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088)
#endif
arch/arm/mach-omap2/cm2_44xx.h
View file @ b0f392c6
......@@ -25,6 +25,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
#include "cm_44xx_54xx.h"
/* CM2 base address */
#define OMAP4430_CM2_BASE 0x4a008000
......@@ -449,9 +451,4 @@
#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
/* Function prototypes */
extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
#endif
arch/arm/mach-omap2/cm2_54xx.h 0 → 100644
View file @ b0f392c6
/*
* OMAP54xx CM2 instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
#include "cm_44xx_54xx.h"
/* CM2 base address */
#define OMAP54XX_CM_CORE_BASE 0x4a008000
#define OMAP54XX_CM_CORE_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))
/* CM_CORE instances */
#define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
#define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
#define OMAP54XX_CM_CORE_COREAON_INST 0x0600
#define OMAP54XX_CM_CORE_CORE_INST 0x0700
#define OMAP54XX_CM_CORE_IVA_INST 0x1200
#define OMAP54XX_CM_CORE_CAM_INST 0x1300
#define OMAP54XX_CM_CORE_DSS_INST 0x1400
#define OMAP54XX_CM_CORE_GPU_INST 0x1500
#define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
#define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700
#define OMAP54XX_CM_CORE_RESTORE_INST 0x1e00
#define OMAP54XX_CM_CORE_INSTR_INST 0x1f00
/* CM_CORE clockdomain register offsets (from instance start) */
#define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100
#define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200
#define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
#define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
#define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500
#define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
#define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
#define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800
#define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900
#define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80
#define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
/* CM_CORE */
/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
#define OMAP54XX_REVISION_CM_CORE_OFFSET 0x0000
#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
#define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET 0x0080
#define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET 0x0084
/* CM_CORE.CKGEN_CM_CORE register offsets */
#define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004
#define OMAP54XX_CM_CLKSEL_USB_60MHZ OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004)
#define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET 0x0040
#define OMAP54XX_CM_CLKMODE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040)
#define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET 0x0044
#define OMAP54XX_CM_IDLEST_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044)
#define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048
#define OMAP54XX_CM_AUTOIDLE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048)
#define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET 0x004c
#define OMAP54XX_CM_CLKSEL_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c)
#define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET 0x0050
#define OMAP54XX_CM_DIV_M2_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050)
#define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0054
#define OMAP54XX_CM_DIV_M3_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054)
#define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0058
#define OMAP54XX_CM_DIV_H11_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058)
#define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET 0x005c
#define OMAP54XX_CM_DIV_H12_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c)
#define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET 0x0060
#define OMAP54XX_CM_DIV_H13_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060)
#define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0064
#define OMAP54XX_CM_DIV_H14_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
#define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
#define OMAP54XX_CM_CLKMODE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080)
#define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET 0x0084
#define OMAP54XX_CM_IDLEST_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084)
#define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088
#define OMAP54XX_CM_AUTOIDLE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088)
#define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET 0x008c
#define OMAP54XX_CM_CLKSEL_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c)
#define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET 0x0090
#define OMAP54XX_CM_DIV_M2_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4)
#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET 0x00c0
#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0)
#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET 0x00c4
#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4)
#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET 0x00c8
#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8)
#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET 0x00cc
#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc)
#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET 0x00d0
#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET 0x00e8
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET 0x00ec
#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET 0x00f4
#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4)
#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET 0x0100
#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100)
#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET 0x0104
#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104)
#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET 0x0108
#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108)
#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET 0x010c
#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c)
#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET 0x0110
#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET 0x0128
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET 0x012c
#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET 0x0134
#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134)
/* CM_CORE.COREAON_CM_CORE register offsets */
#define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028)
#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET 0x0030
#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030)
#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038)
#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET 0x0040
#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040)
#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050)
/* CM_CORE.CORE_CM_CORE register offsets */
#define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020)
#define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET 0x0100
#define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET 0x0108
#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET 0x0120
#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120)
#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET 0x0128
#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128)
#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET 0x0130
#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130)
#define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET 0x0200
#define OMAP54XX_CM_IPU_STATICDEP_OFFSET 0x0204
#define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET 0x0208
#define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET 0x0220
#define OMAP54XX_CM_IPU_IPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220)
#define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
#define OMAP54XX_CM_DMA_STATICDEP_OFFSET 0x0304
#define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320)
#define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
#define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
#define OMAP54XX_CM_EMIF_DMM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420)
#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428)
#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430)
#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438)
#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440)
#define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET 0x0500
#define OMAP54XX_CM_C2C_STATICDEP_OFFSET 0x0504
#define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET 0x0508
#define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET 0x0520
#define OMAP54XX_CM_C2C_C2C_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520)
#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET 0x0528
#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528)
#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET 0x0530
#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530)
#define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
#define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620)
#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628)
#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630
#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630)
#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638)
#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640)
#define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET 0x0720
#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720)
#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728)
#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740)
#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748)
#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750)
#define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET 0x0800
#define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET 0x0804
#define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET 0x0808
#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET 0x0820
#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820)
#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET 0x0828
#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828)
#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET 0x0830
#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830)
#define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0900
#define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0908
#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0928
#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928)
#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0930
#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930)
#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0938
#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938)
#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0940
#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940)
#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0948
#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948)
#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0950
#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950)
#define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0958
#define OMAP54XX_CM_L4PER_ELM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958)
#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0960
#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960)
#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0968
#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968)
#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0970
#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970)
#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0978
#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978)
#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0980
#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980)
#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0988
#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988)
#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x09a0
#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0)
#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x09a8
#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8)
#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x09b0
#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0)
#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x09b8
#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8)
#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET 0x09c0
#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0)
#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x09f0
#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0)
#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x09f8
#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8)
#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0a00
#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00)
#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0a08
#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08)
#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0a10
#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10)
#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0a18
#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18)
#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0a20
#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20)
#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0a28
#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28)
#define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0a40
#define OMAP54XX_CM_L4PER_UART1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40)
#define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0a48
#define OMAP54XX_CM_L4PER_UART2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48)
#define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0a50
#define OMAP54XX_CM_L4PER_UART3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50)
#define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0a58
#define OMAP54XX_CM_L4PER_UART4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58)
#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET 0x0a60
#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60)
#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0a68
#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68)
#define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0a70
#define OMAP54XX_CM_L4PER_UART5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70)
#define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET 0x0a78
#define OMAP54XX_CM_L4PER_UART6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78)
#define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0a80
#define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET 0x0a84
#define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0a88
#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x0aa0
#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0)
#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x0aa8
#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8)
#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x0ab0
#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0)
#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x0ab8
#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8)
#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x0ac0
#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0)
#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET 0x0ac8
#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8)
#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x0ad8
#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8)
/* CM_CORE.IVA_CM_CORE register offsets */
#define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_IVA_STATICDEP_OFFSET 0x0004
#define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_IVA_IVA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020)
#define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
#define OMAP54XX_CM_IVA_SL2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028)
/* CM_CORE.CAM_CM_CORE register offsets */
#define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_CAM_STATICDEP_OFFSET 0x0004
#define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_CAM_ISS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020)
#define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028
#define OMAP54XX_CM_CAM_FDIF_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028)
#define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET 0x0030
#define OMAP54XX_CM_CAM_CAL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030)
/* CM_CORE.DSS_CM_CORE register offsets */
#define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_DSS_STATICDEP_OFFSET 0x0004
#define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_DSS_DSS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020)
#define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
#define OMAP54XX_CM_DSS_BB2D_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030)
/* CM_CORE.GPU_CM_CORE register offsets */
#define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_GPU_STATICDEP_OFFSET 0x0004
#define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_GPU_GPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020)
/* CM_CORE.L3INIT_CM_CORE register offsets */
#define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
#define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028)
#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030)
#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038
#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038)
#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET 0x0040
#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040)
#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET 0x0048
#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048)
#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET 0x0058
#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058)
#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET 0x0068
#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068)
#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078)
#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088)
#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0)
#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8)
#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET 0x00f0
#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0)
/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
#define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
#endif
arch/arm/mach-omap2/cm_44xx_54xx.h 0 → 100644
View file @ b0f392c6
/*
* OMAP44xx and OMAP54xx CM1/CM2 function prototypes
*
* Copyright (C) 2009-2013 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
/* CM1 Function prototypes */
extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
/* CM2 Function prototypes */
extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
#endif
arch/arm/mach-omap2/io.c
View file @ b0f392c6
......@@ -631,7 +631,13 @@ void __init omap5_init_early(void)
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap_prm_base_init();
omap_cm_base_init();
omap44xx_prm_init();
omap5xxx_check_revision();
omap54xx_voltagedomains_init();
omap54xx_powerdomains_init();
omap54xx_clockdomains_init();
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
}
#endif
......
arch/arm/mach-omap2/omap_hwmod.h
View file @ b0f392c6
......@@ -699,6 +699,7 @@ extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
extern int omap54xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
......
arch/arm/mach-omap2/omap_hwmod_54xx_data.c 0 → 100644
View file @ b0f392c6
/*
* Hardware modules present on the OMAP54xx chips
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Paul Walmsley
* Benoit Cousson
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/power/smartreflex.h>
#include <linux/platform_data/omap_ocp2scp.h>
#include <linux/i2c-omap.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include "cm1_54xx.h"
#include "cm2_54xx.h"
#include "prm54xx.h"
#include "prm-regbits-54xx.h"
#include "i2c.h"
#include "mmc.h"
#include "wd_timer.h"
/* Base offset for all OMAP5 interrupts external to MPUSS */
#define OMAP54XX_IRQ_GIC_START 32
/* Base offset for all OMAP5 dma requests */
#define OMAP54XX_DMA_REQ_START 1
/*
* IP blocks
*/
/*
* 'dmm' class
* instance(s): dmm
*/
static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
.name = "dmm",
};
/* dmm */
static struct omap_hwmod omap54xx_dmm_hwmod = {
.name = "dmm",
.class = &omap54xx_dmm_hwmod_class,
.clkdm_name = "emif_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
},
},
};
/*
* 'l3' class
* instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
*/
static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
.name = "l3",
};
/* l3_instr */
static struct omap_hwmod omap54xx_l3_instr_hwmod = {
.name = "l3_instr",
.class = &omap54xx_l3_hwmod_class,
.clkdm_name = "l3instr_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/* l3_main_1 */
static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
.name = "l3_main_1",
.class = &omap54xx_l3_hwmod_class,
.clkdm_name = "l3main1_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
},
},
};
/* l3_main_2 */
static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
.name = "l3_main_2",
.class = &omap54xx_l3_hwmod_class,
.clkdm_name = "l3main2_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
},
},
};
/* l3_main_3 */
static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
.name = "l3_main_3",
.class = &omap54xx_l3_hwmod_class,
.clkdm_name = "l3instr_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'l4' class
* instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
*/
static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
.name = "l4",
};
/* l4_abe */
static struct omap_hwmod omap54xx_l4_abe_hwmod = {
.name = "l4_abe",
.class = &omap54xx_l4_hwmod_class,
.clkdm_name = "abe_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
};
/* l4_cfg */
static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
.name = "l4_cfg",
.class = &omap54xx_l4_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
},
},
};
/* l4_per */
static struct omap_hwmod omap54xx_l4_per_hwmod = {
.name = "l4_per",
.class = &omap54xx_l4_hwmod_class,
.clkdm_name = "l4per_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
},
},
};
/* l4_wkup */
static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
.name = "l4_wkup",
.class = &omap54xx_l4_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
},
},
};
/*
* 'mpu_bus' class
* instance(s): mpu_private
*/
static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
.name = "mpu_bus",
};
/* mpu_private */
static struct omap_hwmod omap54xx_mpu_private_hwmod = {
.name = "mpu_private",
.class = &omap54xx_mpu_bus_hwmod_class,
.clkdm_name = "mpu_clkdm",
.prcm = {
.omap4 = {
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
};
/*
* 'counter' class
* 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
*/
static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
.name = "counter",
.sysc = &omap54xx_counter_sysc,
};
/* counter_32k */
static struct omap_hwmod omap54xx_counter_32k_hwmod = {
.name = "counter_32k",
.class = &omap54xx_counter_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "wkupaon_iclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
},
},
};
/*
* 'dma' class
* dma controller for data exchange between memory to memory (i.e. internal or
* external memory) and gp peripherals to memory or memory to gp peripherals
*/
static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
.name = "dma",
.sysc = &omap54xx_dma_sysc,
};
/* dma dev_attr */
static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
.lch_count = 32,
};
/* dma_system */
static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
{ .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
{ .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
{ .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
{ .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap54xx_dma_system_hwmod = {
.name = "dma_system",
.class = &omap54xx_dma_hwmod_class,
.clkdm_name = "dma_clkdm",
.mpu_irqs = omap54xx_dma_system_irqs,
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
},
},
.dev_attr = &dma_dev_attr,
};
/*
* 'dmic' class
* digital microphone controller
*/
static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
.name = "dmic",
.sysc = &omap54xx_dmic_sysc,
};
/* dmic */
static struct omap_hwmod omap54xx_dmic_hwmod = {
.name = "dmic",
.class = &omap54xx_dmic_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "dmic_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'emif' class
* external memory interface no1 (wrapper)
*/
static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
.rev_offs = 0x0000,
};
static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
.name = "emif",
.sysc = &omap54xx_emif_sysc,
};
/* emif1 */
static struct omap_hwmod omap54xx_emif1_hwmod = {
.name = "emif1",
.class = &omap54xx_emif_hwmod_class,
.clkdm_name = "emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.main_clk = "dpll_core_h11x2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/* emif2 */
static struct omap_hwmod omap54xx_emif2_hwmod = {
.name = "emif2",
.class = &omap54xx_emif_hwmod_class,
.clkdm_name = "emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.main_clk = "dpll_core_h11x2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'gpio' class
* general purpose io module
*/
static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0114,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &omap54xx_gpio_sysc,
.rev = 2,
};
/* gpio dev_attr */
static struct omap_gpio_dev_attr gpio_dev_attr = {
.bank_width = 32,
.dbck_flag = true,
};
/* gpio1 */
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
};
static struct omap_hwmod omap54xx_gpio1_hwmod = {
.name = "gpio1",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.main_clk = "wkupaon_iclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio2 */
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbclk" },
};
static struct omap_hwmod omap54xx_gpio2_hwmod = {
.name = "gpio2",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio3 */
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbclk" },
};
static struct omap_hwmod omap54xx_gpio3_hwmod = {
.name = "gpio3",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio4 */
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio4_dbclk" },
};
static struct omap_hwmod omap54xx_gpio4_hwmod = {
.name = "gpio4",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio5 */
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio5_dbclk" },
};
static struct omap_hwmod omap54xx_gpio5_hwmod = {
.name = "gpio5",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio5_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio6 */
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio6_dbclk" },
};
static struct omap_hwmod omap54xx_gpio6_hwmod = {
.name = "gpio6",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio6_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio7 */
static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio7_dbclk" },
};
static struct omap_hwmod omap54xx_gpio7_hwmod = {
.name = "gpio7",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio7_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio8 */
static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio8_dbclk" },
};
static struct omap_hwmod omap54xx_gpio8_hwmod = {
.name = "gpio8",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio8_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/*
* 'i2c' class
* multimaster high-speed i2c controller
*/
static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
.sysc_offs = 0x0010,
.syss_offs = 0x0090,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.clockact = CLOCKACT_TEST_ICLK,
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
.name = "i2c",
.sysc = &omap54xx_i2c_sysc,
.reset = &omap_i2c_reset,
.rev = OMAP_I2C_IP_VERSION_2,
};
/* i2c dev_attr */
static struct omap_i2c_dev_attr i2c_dev_attr = {
.flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
};
/* i2c1 */
static struct omap_hwmod omap54xx_i2c1_hwmod = {
.name = "i2c1",
.class = &omap54xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &i2c_dev_attr,
};
/* i2c2 */
static struct omap_hwmod omap54xx_i2c2_hwmod = {
.name = "i2c2",
.class = &omap54xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &i2c_dev_attr,
};
/* i2c3 */
static struct omap_hwmod omap54xx_i2c3_hwmod = {
.name = "i2c3",
.class = &omap54xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &i2c_dev_attr,
};
/* i2c4 */
static struct omap_hwmod omap54xx_i2c4_hwmod = {
.name = "i2c4",
.class = &omap54xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &i2c_dev_attr,
};
/* i2c5 */
static struct omap_hwmod omap54xx_i2c5_hwmod = {
.name = "i2c5",
.class = &omap54xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &i2c_dev_attr,
};
/*
* 'kbd' class
* keyboard controller
*/
static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
.name = "kbd",
.sysc = &omap54xx_kbd_sysc,
};
/* kbd */
static struct omap_hwmod omap54xx_kbd_hwmod = {
.name = "kbd",
.class = &omap54xx_kbd_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mcbsp' class
* multi channel buffered serial port controller
*/
static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
.sysc_offs = 0x008c,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
.name = "mcbsp",
.sysc = &omap54xx_mcbsp_sysc,
.rev = MCBSP_CONFIG_TYPE4,
};
/* mcbsp1 */
static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
};
static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap54xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "mcbsp1_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcbsp1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
};
/* mcbsp2 */
static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
};
static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap54xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "mcbsp2_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcbsp2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
};
/* mcbsp3 */
static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
};
static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap54xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "mcbsp3_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcbsp3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
};
/*
* 'mcpdm' class
* multi channel pdm controller (proprietary interface with phoenix power
* ic)
*/
static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
.name = "mcpdm",
.sysc = &omap54xx_mcpdm_sysc,
};
/* mcpdm */
static struct omap_hwmod omap54xx_mcpdm_hwmod = {
.name = "mcpdm",
.class = &omap54xx_mcpdm_hwmod_class,
.clkdm_name = "abe_clkdm",
/*
* It's suspected that the McPDM requires an off-chip main
* functional clock, controlled via I2C. This IP block is
* currently reset very early during boot, before I2C is
* available, so it doesn't seem that we have any choice in
* the kernel other than to avoid resetting it. XXX This is
* really a hardware issue workaround: every IP block should
* be able to source its main functional clock from either
* on-chip or off-chip sources. McPDM seems to be the only
* current exception.
*/
.flags = HWMOD_EXT_OPT_MAIN_CLK,
.main_clk = "pad_clks_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
*/
static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
.name = "mcspi",
.sysc = &omap54xx_mcspi_sysc,
.rev = OMAP4_MCSPI_REV,
};
/* mcspi1 */
/* mcspi1 dev_attr */
static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
.num_chipselect = 4,
};
static struct omap_hwmod omap54xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mcspi1_dev_attr,
};
/* mcspi2 */
/* mcspi2 dev_attr */
static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
.num_chipselect = 2,
};
static struct omap_hwmod omap54xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mcspi2_dev_attr,
};
/* mcspi3 */
/* mcspi3 dev_attr */
static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
.num_chipselect = 2,
};
static struct omap_hwmod omap54xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mcspi3_dev_attr,
};
/* mcspi4 */
/* mcspi4 dev_attr */
static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
.num_chipselect = 1,
};
static struct omap_hwmod omap54xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mcspi4_dev_attr,
};
/*
* 'mmc' class
* multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
*/
static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
.name = "mmc",
.sysc = &omap54xx_mmc_sysc,
};
/* mmc1 */
static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
{ .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
};
/* mmc1 dev_attr */
static struct omap_mmc_dev_attr mmc1_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};
static struct omap_hwmod omap54xx_mmc1_hwmod = {
.name = "mmc1",
.class = &omap54xx_mmc_hwmod_class,
.clkdm_name = "l3init_clkdm",
.main_clk = "mmc1_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mmc1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
.dev_attr = &mmc1_dev_attr,
};
/* mmc2 */
static struct omap_hwmod omap54xx_mmc2_hwmod = {
.name = "mmc2",
.class = &omap54xx_mmc_hwmod_class,
.clkdm_name = "l3init_clkdm",
.main_clk = "mmc2_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* mmc3 */
static struct omap_hwmod omap54xx_mmc3_hwmod = {
.name = "mmc3",
.class = &omap54xx_mmc_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* mmc4 */
static struct omap_hwmod omap54xx_mmc4_hwmod = {
.name = "mmc4",
.class = &omap54xx_mmc_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* mmc5 */
static struct omap_hwmod omap54xx_mmc5_hwmod = {
.name = "mmc5",
.class = &omap54xx_mmc_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mpu' class
* mpu sub-system
*/
static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
.name = "mpu",
};
/* mpu */
static struct omap_hwmod omap54xx_mpu_hwmod = {
.name = "mpu",
.class = &omap54xx_mpu_hwmod_class,
.clkdm_name = "mpu_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.main_clk = "dpll_mpu_m2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
},
},
};
/*
* 'timer' class
* general purpose timer module with accurate 1ms tick
* This class contains several variants: ['timer_1ms', 'timer']
*/
static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
.clockact = CLOCKACT_TEST_ICLK,
};
static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
.name = "timer",
.sysc = &omap54xx_timer_1ms_sysc,
};
static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
.name = "timer",
.sysc = &omap54xx_timer_sysc,
};
/* timer1 */
static struct omap_hwmod omap54xx_timer1_hwmod = {
.name = "timer1",
.class = &omap54xx_timer_1ms_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.main_clk = "timer1_gfclk_mux",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer2 */
static struct omap_hwmod omap54xx_timer2_hwmod = {
.name = "timer2",
.class = &omap54xx_timer_1ms_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "timer2_gfclk_mux",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer3 */
static struct omap_hwmod omap54xx_timer3_hwmod = {
.name = "timer3",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "timer3_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer4 */
static struct omap_hwmod omap54xx_timer4_hwmod = {
.name = "timer4",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "timer4_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer5 */
static struct omap_hwmod omap54xx_timer5_hwmod = {
.name = "timer5",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "timer5_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer6 */
static struct omap_hwmod omap54xx_timer6_hwmod = {
.name = "timer6",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "timer6_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer7 */
static struct omap_hwmod omap54xx_timer7_hwmod = {
.name = "timer7",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "timer7_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer8 */
static struct omap_hwmod omap54xx_timer8_hwmod = {
.name = "timer8",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "timer8_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer9 */
static struct omap_hwmod omap54xx_timer9_hwmod = {
.name = "timer9",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "timer9_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer10 */
static struct omap_hwmod omap54xx_timer10_hwmod = {
.name = "timer10",
.class = &omap54xx_timer_1ms_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "timer10_gfclk_mux",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer11 */
static struct omap_hwmod omap54xx_timer11_hwmod = {
.name = "timer11",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "timer11_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'uart' class
* universal asynchronous receiver/transmitter (uart)
*/
static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
.rev_offs = 0x0050,
.sysc_offs = 0x0054,
.syss_offs = 0x0058,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
.name = "uart",
.sysc = &omap54xx_uart_sysc,
};
/* uart1 */
static struct omap_hwmod omap54xx_uart1_hwmod = {
.name = "uart1",
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* uart2 */
static struct omap_hwmod omap54xx_uart2_hwmod = {
.name = "uart2",
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* uart3 */
static struct omap_hwmod omap54xx_uart3_hwmod = {
.name = "uart3",
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* uart4 */
static struct omap_hwmod omap54xx_uart4_hwmod = {
.name = "uart4",
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* uart5 */
static struct omap_hwmod omap54xx_uart5_hwmod = {
.name = "uart5",
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* uart6 */
static struct omap_hwmod omap54xx_uart6_hwmod = {
.name = "uart6",
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'usb_otg_ss' class
* 2.0 super speed (usb_otg_ss) controller
*/
static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
.name = "usb_otg_ss",
.sysc = &omap54xx_usb_otg_ss_sysc,
};
/* usb_otg_ss */
static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
{ .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
};
static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
.name = "usb_otg_ss",
.class = &omap54xx_usb_otg_ss_hwmod_class,
.clkdm_name = "l3init_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "dpll_core_h13x2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = usb_otg_ss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
};
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
* overflow condition
*/
static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap54xx_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable,
};
/* wd_timer2 */
static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &omap54xx_wd_timer_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* Interfaces
*/
/* l3_main_1 -> dmm */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
.master = &omap54xx_l3_main_1_hwmod,
.slave = &omap54xx_dmm_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_SDMA,
};
/* l3_main_3 -> l3_instr */
static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
.master = &omap54xx_l3_main_3_hwmod,
.slave = &omap54xx_l3_instr_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
.master = &omap54xx_l3_main_2_hwmod,
.slave = &omap54xx_l3_main_1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> l3_main_1 */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
.master = &omap54xx_l4_cfg_hwmod,
.slave = &omap54xx_l3_main_1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> l3_main_1 */
static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
.master = &omap54xx_mpu_hwmod,
.slave = &omap54xx_l3_main_1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU,
};
/* l3_main_1 -> l3_main_2 */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
.master = &omap54xx_l3_main_1_hwmod,
.slave = &omap54xx_l3_main_2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU,
};
/* l4_cfg -> l3_main_2 */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
.master = &omap54xx_l4_cfg_hwmod,
.slave = &omap54xx_l3_main_2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
.master = &omap54xx_l3_main_1_hwmod,
.slave = &omap54xx_l3_main_3_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU,
};
/* l3_main_2 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
.master = &omap54xx_l3_main_2_hwmod,
.slave = &omap54xx_l3_main_3_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> l3_main_3 */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
.master = &omap54xx_l4_cfg_hwmod,
.slave = &omap54xx_l3_main_3_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l4_abe */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
.master = &omap54xx_l3_main_1_hwmod,
.slave = &omap54xx_l4_abe_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> l4_abe */
static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
.master = &omap54xx_mpu_hwmod,
.slave = &omap54xx_l4_abe_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
.master = &omap54xx_l3_main_1_hwmod,
.slave = &omap54xx_l4_cfg_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> l4_per */
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
.master = &omap54xx_l3_main_2_hwmod,
.slave = &omap54xx_l4_per_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l4_wkup */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
.master = &omap54xx_l3_main_1_hwmod,
.slave = &omap54xx_l4_wkup_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> mpu_private */
static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
.master = &omap54xx_mpu_hwmod,
.slave = &omap54xx_mpu_private_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
.master = &omap54xx_l4_wkup_hwmod,
.slave = &omap54xx_counter_32k_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
{
.pa_start = 0x4a056000,
.pa_end = 0x4a056fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> dma_system */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
.master = &omap54xx_l4_cfg_hwmod,
.slave = &omap54xx_dma_system_hwmod,
.clk = "l4_root_clk_div",
.addr = omap54xx_dma_system_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_abe -> dmic */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_dmic_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* mpu -> emif1 */
static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
.master = &omap54xx_mpu_hwmod,
.slave = &omap54xx_emif1_hwmod,
.clk = "dpll_core_h11x2_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> emif2 */
static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
.master = &omap54xx_mpu_hwmod,
.slave = &omap54xx_emif2_hwmod,
.clk = "dpll_core_h11x2_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> gpio1 */
static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
.master = &omap54xx_l4_wkup_hwmod,
.slave = &omap54xx_gpio1_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> gpio2 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_gpio2_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> gpio3 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_gpio3_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> gpio4 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_gpio4_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> gpio5 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_gpio5_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> gpio6 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_gpio6_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> gpio7 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_gpio7_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> gpio8 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_gpio8_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> i2c1 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_i2c1_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> i2c2 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_i2c2_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> i2c3 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_i2c3_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> i2c4 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_i2c4_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> i2c5 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_i2c5_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> kbd */
static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
.master = &omap54xx_l4_wkup_hwmod,
.slave = &omap54xx_kbd_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_abe -> mcbsp1 */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_mcbsp1_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> mcbsp2 */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_mcbsp2_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> mcbsp3 */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_mcbsp3_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> mcpdm */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_mcpdm_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_per -> mcspi1 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mcspi1_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mcspi2 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mcspi2_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mcspi3 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mcspi3_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mcspi4 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mcspi4_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mmc1 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mmc1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mmc2 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mmc2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mmc3 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mmc3_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mmc4 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mmc4_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mmc5 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mmc5_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> mpu */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
.master = &omap54xx_l4_cfg_hwmod,
.slave = &omap54xx_mpu_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
.master = &omap54xx_l4_wkup_hwmod,
.slave = &omap54xx_timer1_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> timer2 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_timer2_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> timer3 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_timer3_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> timer4 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_timer4_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_abe -> timer5 */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_timer5_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> timer6 */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_timer6_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> timer7 */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_timer7_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> timer8 */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_timer8_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_per -> timer9 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_timer9_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> timer10 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_timer10_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> timer11 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_timer11_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> uart1 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_uart1_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> uart2 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_uart2_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> uart3 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_uart3_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> uart4 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_uart4_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> uart5 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_uart5_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> uart6 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_uart6_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> usb_otg_ss */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
.master = &omap54xx_l4_cfg_hwmod,
.slave = &omap54xx_usb_otg_ss_hwmod,
.clk = "dpll_core_h13x2_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
.master = &omap54xx_l4_wkup_hwmod,
.slave = &omap54xx_wd_timer2_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l3_main_1__dmm,
&omap54xx_l3_main_3__l3_instr,
&omap54xx_l3_main_2__l3_main_1,
&omap54xx_l4_cfg__l3_main_1,
&omap54xx_mpu__l3_main_1,
&omap54xx_l3_main_1__l3_main_2,
&omap54xx_l4_cfg__l3_main_2,
&omap54xx_l3_main_1__l3_main_3,
&omap54xx_l3_main_2__l3_main_3,
&omap54xx_l4_cfg__l3_main_3,
&omap54xx_l3_main_1__l4_abe,
&omap54xx_mpu__l4_abe,
&omap54xx_l3_main_1__l4_cfg,
&omap54xx_l3_main_2__l4_per,
&omap54xx_l3_main_1__l4_wkup,
&omap54xx_mpu__mpu_private,
&omap54xx_l4_wkup__counter_32k,
&omap54xx_l4_cfg__dma_system,
&omap54xx_l4_abe__dmic,
&omap54xx_mpu__emif1,
&omap54xx_mpu__emif2,
&omap54xx_l4_wkup__gpio1,
&omap54xx_l4_per__gpio2,
&omap54xx_l4_per__gpio3,
&omap54xx_l4_per__gpio4,
&omap54xx_l4_per__gpio5,
&omap54xx_l4_per__gpio6,
&omap54xx_l4_per__gpio7,
&omap54xx_l4_per__gpio8,
&omap54xx_l4_per__i2c1,
&omap54xx_l4_per__i2c2,
&omap54xx_l4_per__i2c3,
&omap54xx_l4_per__i2c4,
&omap54xx_l4_per__i2c5,
&omap54xx_l4_wkup__kbd,
&omap54xx_l4_abe__mcbsp1,
&omap54xx_l4_abe__mcbsp2,
&omap54xx_l4_abe__mcbsp3,
&omap54xx_l4_abe__mcpdm,
&omap54xx_l4_per__mcspi1,
&omap54xx_l4_per__mcspi2,
&omap54xx_l4_per__mcspi3,
&omap54xx_l4_per__mcspi4,
&omap54xx_l4_per__mmc1,
&omap54xx_l4_per__mmc2,
&omap54xx_l4_per__mmc3,
&omap54xx_l4_per__mmc4,
&omap54xx_l4_per__mmc5,
&omap54xx_l4_cfg__mpu,
&omap54xx_l4_wkup__timer1,
&omap54xx_l4_per__timer2,
&omap54xx_l4_per__timer3,
&omap54xx_l4_per__timer4,
&omap54xx_l4_abe__timer5,
&omap54xx_l4_abe__timer6,
&omap54xx_l4_abe__timer7,
&omap54xx_l4_abe__timer8,
&omap54xx_l4_per__timer9,
&omap54xx_l4_per__timer10,
&omap54xx_l4_per__timer11,
&omap54xx_l4_per__uart1,
&omap54xx_l4_per__uart2,
&omap54xx_l4_per__uart3,
&omap54xx_l4_per__uart4,
&omap54xx_l4_per__uart5,
&omap54xx_l4_per__uart6,
&omap54xx_l4_cfg__usb_otg_ss,
&omap54xx_l4_wkup__wd_timer2,
NULL,
};
int __init omap54xx_hwmod_init(void)
{
omap_hwmod_init();
return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
}
arch/arm/mach-omap2/powerdomain.h
View file @ b0f392c6
......@@ -253,6 +253,7 @@ extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
extern void omap54xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
......
arch/arm/mach-omap2/powerdomains54xx_data.c 0 → 100644
View file @ b0f392c6
/*
* OMAP54XX Power domains framework
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com)
* Paul Walmsley (paul@pwsan.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include "powerdomain.h"
#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm-regbits-54xx.h"
#include "prm54xx.h"
#include "prcm_mpu54xx.h"
/* core_54xx_pwrdm: CORE power domain */
static struct powerdomain core_54xx_pwrdm = {
.name = "core_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_CORE_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 5,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */
[2] = PWRSTS_OFF_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */
[2] = PWRSTS_OFF_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* abe_54xx_pwrdm: Audio back end power domain */
static struct powerdomain abe_54xx_pwrdm = {
.name = "abe_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_ABE_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* aessmem */
[1] = PWRSTS_OFF_RET, /* periphmem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* aessmem */
[1] = PWRSTS_OFF_RET, /* periphmem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
static struct powerdomain coreaon_54xx_pwrdm = {
.name = "coreaon_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_COREAON_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_ON,
};
/* dss_54xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_54xx_pwrdm = {
.name = "dss_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_DSS_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* dss_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* dss_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_54xx_pwrdm = {
.name = "cpu0_pwrdm",
.voltdm = { .name = "mpu" },
.prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST,
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cpu0_l1 */
},
};
/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_54xx_pwrdm = {
.name = "cpu1_pwrdm",
.voltdm = { .name = "mpu" },
.prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST,
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cpu1_l1 */
},
};
/* emu_54xx_pwrdm: Emulation power domain */
static struct powerdomain emu_54xx_pwrdm = {
.name = "emu_pwrdm",
.voltdm = { .name = "wkup" },
.prcm_offs = OMAP54XX_PRM_EMU_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* emu_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* emu_bank */
},
};
/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_54xx_pwrdm = {
.name = "mpu_pwrdm",
.voltdm = { .name = "mpu" },
.prcm_offs = OMAP54XX_PRM_MPU_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */
[1] = PWRSTS_RET, /* mpu_ram */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */
[1] = PWRSTS_OFF_RET, /* mpu_ram */
},
};
/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain custefuse_54xx_pwrdm = {
.name = "custefuse_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* dsp_54xx_pwrdm: Tesla processor power domain */
static struct powerdomain dsp_54xx_pwrdm = {
.name = "dsp_pwrdm",
.voltdm = { .name = "mm" },
.prcm_offs = OMAP54XX_PRM_DSP_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 3,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* dsp_edma */
[1] = PWRSTS_OFF_RET, /* dsp_l1 */
[2] = PWRSTS_OFF_RET, /* dsp_l2 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* dsp_edma */
[1] = PWRSTS_OFF_RET, /* dsp_l1 */
[2] = PWRSTS_OFF_RET, /* dsp_l2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* cam_54xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_54xx_pwrdm = {
.name = "cam_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_CAM_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cam_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* cam_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* l3init_54xx_pwrdm: L3 initators pheripherals power domain */
static struct powerdomain l3init_54xx_pwrdm = {
.name = "l3init_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_L3INIT_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* l3init_bank1 */
[1] = PWRSTS_OFF_RET, /* l3init_bank2 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* l3init_bank1 */
[1] = PWRSTS_OFF_RET, /* l3init_bank2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* gpu_54xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gpu_54xx_pwrdm = {
.name = "gpu_pwrdm",
.voltdm = { .name = "mm" },
.prcm_offs = OMAP54XX_PRM_GPU_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* gpu_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* gpu_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* wkupaon_54xx_pwrdm: Wake-up power domain */
static struct powerdomain wkupaon_54xx_pwrdm = {
.name = "wkupaon_pwrdm",
.voltdm = { .name = "wkup" },
.prcm_offs = OMAP54XX_PRM_WKUPAON_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_ON,
.banks = 1,
.pwrsts_mem_ret = {
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* wkup_bank */
},
};
/* iva_54xx_pwrdm: IVA-HD power domain */
static struct powerdomain iva_54xx_pwrdm = {
.name = "iva_pwrdm",
.voltdm = { .name = "mm" },
.prcm_offs = OMAP54XX_PRM_IVA_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 4,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* hwa_mem */
[1] = PWRSTS_OFF_RET, /* sl2_mem */
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* hwa_mem */
[1] = PWRSTS_OFF_RET, /* sl2_mem */
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/*
* The following power domains are not under SW control
*
* mpuaon
* mmaon
*/
/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap54xx[] __initdata = {
&core_54xx_pwrdm,
&abe_54xx_pwrdm,
&coreaon_54xx_pwrdm,
&dss_54xx_pwrdm,
&cpu0_54xx_pwrdm,
&cpu1_54xx_pwrdm,
&emu_54xx_pwrdm,
&mpu_54xx_pwrdm,
&custefuse_54xx_pwrdm,
&dsp_54xx_pwrdm,
&cam_54xx_pwrdm,
&l3init_54xx_pwrdm,
&gpu_54xx_pwrdm,
&wkupaon_54xx_pwrdm,
&iva_54xx_pwrdm,
NULL
};
void __init omap54xx_powerdomains_init(void)
{
pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_omap54xx);
pwrdm_complete_init();
}
arch/arm/mach-omap2/prcm44xx.h
View file @ b0f392c6
......@@ -32,6 +32,12 @@
#define OMAP4430_SCRM_PARTITION 4
#define OMAP4430_PRCM_MPU_PARTITION 5
#define OMAP54XX_PRM_PARTITION 1
#define OMAP54XX_CM_CORE_AON_PARTITION 2
#define OMAP54XX_CM_CORE_PARTITION 3
#define OMAP54XX_SCRM_PARTITION 4
#define OMAP54XX_PRCM_MPU_PARTITION 5
/*
* OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
* IDs, plus one
......
arch/arm/mach-omap2/prcm_mpu44xx.h
View file @ b0f392c6
......@@ -25,12 +25,9 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
#include "prcm_mpu_44xx_54xx.h"
#include "common.h"
# ifndef __ASSEMBLER__
extern void __iomem *prcm_mpu_base;
# endif
#define OMAP4430_PRCM_MPU_BASE 0x48243000
#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
......@@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base;
#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
/* Function prototypes */
# ifndef __ASSEMBLER__
extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
s16 idx);
extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
# endif
#endif
arch/arm/mach-omap2/prcm_mpu54xx.h 0 → 100644
View file @ b0f392c6
/*
* OMAP54xx PRCM MPU instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
#include "prcm_mpu_44xx_54xx.h"
#include "common.h"
#define OMAP54XX_PRCM_MPU_BASE 0x48243000
#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
/* PRCM_MPU instances */
#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
#define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
#define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
#define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
#define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
#define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
/* PRCM_MPU clockdomain register offsets (from instance start) */
#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
/*
* PRCM_MPU
*
* The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
* point of view the PRCM_MPU is a single entity. It shares the same
* programming model as the global PRCM and thus can be assimilate as two new
* MOD inside the PRCM
*/
/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
#define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
#endif
arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h 0 → 100644
View file @ b0f392c6
/*
* OMAP44xx and OMAP54xx PRCM MPU function prototypes
*
* Copyright (C) 2010, 2013 Texas Instruments, Inc.
* Copyright (C) 2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
#ifndef __ASSEMBLER__
extern void __iomem *prcm_mpu_base;
extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
s16 idx);
extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
#endif
#endif
arch/arm/mach-omap2/prm-regbits-54xx.h 0 → 100644
View file @ b0f392c6
This source diff could not be displayed because it is too large. You can view the blob instead.
arch/arm/mach-omap2/prm44xx.h
View file @ b0f392c6
......@@ -25,6 +25,7 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
#include "prm44xx_54xx.h"
#include "prcm-common.h"
#include "prm.h"
......@@ -744,36 +745,4 @@
#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
/* Function prototypes */
# ifndef __ASSEMBLER__
extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
/* OMAP4-specific VP functions */
u32 omap4_prm_vp_check_txdone(u8 vp_id);
void omap4_prm_vp_clear_txdone(u8 vp_id);
/*
* OMAP4 access functions for voltage controller (VC) and
* voltage proccessor (VP) in the PRM.
*/
extern u32 omap4_prm_vcvp_read(u8 offset);
extern void omap4_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
extern void omap44xx_prm_reconfigure_io_chain(void);
/* PRM interrupt-related functions */
extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
extern void omap44xx_prm_ocp_barrier(void);
extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
extern int __init omap44xx_prm_init(void);
extern u32 omap44xx_prm_get_reset_sources(void);
# endif
#endif
arch/arm/mach-omap2/prm44xx_54xx.h 0 → 100644
View file @ b0f392c6
/*
* OMAP44xx and 54xx PRM common functions
*
* Copyright (C) 2009-2013 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
/* Function prototypes */
#ifndef __ASSEMBLER__
extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
/* OMAP4/OMAP5-specific VP functions */
u32 omap4_prm_vp_check_txdone(u8 vp_id);
void omap4_prm_vp_clear_txdone(u8 vp_id);
/*
* OMAP4/OMAP5 access functions for voltage controller (VC) and
* voltage proccessor (VP) in the PRM.
*/
extern u32 omap4_prm_vcvp_read(u8 offset);
extern void omap4_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
extern void omap44xx_prm_reconfigure_io_chain(void);
/* PRM interrupt-related functions */
extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
extern void omap44xx_prm_ocp_barrier(void);
extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
extern int __init omap44xx_prm_init(void);
extern u32 omap44xx_prm_get_reset_sources(void);
#endif
#endif
arch/arm/mach-omap2/prm54xx.h 0 → 100644
View file @ b0f392c6
/*
* OMAP54xx PRM instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
#include "prm44xx_54xx.h"
#include "prcm-common.h"
#include "prm.h"
#define OMAP54XX_PRM_BASE 0x4ae06000
#define OMAP54XX_PRM_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
/* PRM instances */
#define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
#define OMAP54XX_PRM_CKGEN_INST 0x0100
#define OMAP54XX_PRM_MPU_INST 0x0300
#define OMAP54XX_PRM_DSP_INST 0x0400
#define OMAP54XX_PRM_ABE_INST 0x0500
#define OMAP54XX_PRM_COREAON_INST 0x0600
#define OMAP54XX_PRM_CORE_INST 0x0700
#define OMAP54XX_PRM_IVA_INST 0x1200
#define OMAP54XX_PRM_CAM_INST 0x1300
#define OMAP54XX_PRM_DSS_INST 0x1400
#define OMAP54XX_PRM_GPU_INST 0x1500
#define OMAP54XX_PRM_L3INIT_INST 0x1600
#define OMAP54XX_PRM_CUSTEFUSE_INST 0x1700
#define OMAP54XX_PRM_WKUPAON_INST 0x1800
#define OMAP54XX_PRM_WKUPAON_CM_INST 0x1900
#define OMAP54XX_PRM_EMU_INST 0x1a00
#define OMAP54XX_PRM_EMU_CM_INST 0x1b00
#define OMAP54XX_PRM_DEVICE_INST 0x1c00
#define OMAP54XX_PRM_INSTR_INST 0x1f00
/* PRM clockdomain register offsets (from instance start) */
#define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
#define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
/* PRM */
/* PRM.OCP_SOCKET_PRM register offsets */
#define OMAP54XX_REVISION_PRM_OFFSET 0x0000
#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020
#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028
#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030
#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038
#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040)
#define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084
#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090
#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094
#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098
#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c
#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0
#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4
/* PRM.CKGEN_PRM register offsets */
#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000
#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000)
#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
#define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008)
#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c)
#define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010
#define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010)
/* PRM.MPU_PRM register offsets */
#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
/* PRM.DSP_PRM register offsets */
#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010
#define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014
#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024
/* PRM.ABE_PRM register offsets */
#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c
#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030
#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034
#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038
#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c
#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040
#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044
#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048
#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c
#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050
#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054
#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058
#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c
#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060
#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064
#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068
#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c
#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070
#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074
#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078
#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c
#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080
#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084
#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088
#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c
/* PRM.COREAON_PRM register offsets */
#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028
#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c
#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030
#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034
#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038
#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c
/* PRM.CORE_PRM register offsets */
#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124
#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c
#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134
#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210
#define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214
#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224
#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524
#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c
#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534
#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634
#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724
#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824
#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c
#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834
#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928
#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c
#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930
#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934
#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938
#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c
#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940
#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944
#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948
#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c
#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950
#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954
#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c
#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960
#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964
#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968
#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c
#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970
#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974
#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978
#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c
#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980
#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984
#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c
#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0
#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4
#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8
#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac
#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0
#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4
#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8
#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc
#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0
#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0
#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4
#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8
#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc
#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00
#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04
#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08
#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c
#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10
#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14
#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18
#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c
#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20
#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24
#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28
#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c
#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40
#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44
#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48
#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c
#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50
#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54
#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58
#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c
#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60
#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64
#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68
#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c
#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70
#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74
#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78
#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c
#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4
#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac
#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4
#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc
#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4
#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc
#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc
/* PRM.IVA_PRM register offsets */
#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010
#define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014
#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
/* PRM.CAM_PRM register offsets */
#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024
#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c
#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034
/* PRM.DSS_PRM register offsets */
#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004
#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
/* PRM.GPU_PRM register offsets */
#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
/* PRM.L3INIT_PRM register offsets */
#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038
#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c
#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040
#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044
#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058
#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c
#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068
#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c
#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0
#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4
/* PRM.CUSTEFUSE_PRM register offsets */
#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
/* PRM.WKUPAON_PRM register offsets */
#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024
#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c
#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030
#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034
#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038
#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c
#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040
#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044
#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048
#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c
#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054
#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064
#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078
#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c
/* PRM.WKUPAON_CM register offsets */
#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020)
#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028)
#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030)
#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038)
#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040)
#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048)
#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050)
#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060)
#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078)
#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090)
#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098)
/* PRM.EMU_PRM register offsets */
#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
/* PRM.EMU_CM register offsets */
#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020)
#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028
#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028)
/* PRM.DEVICE_PRM register offsets */
#define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000
#define OMAP54XX_PRM_RSTST_OFFSET 0x0004
#define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008
#define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c
#define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010
#define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014
#define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018
#define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c
#define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020
#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
#define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
#define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
#define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040
#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044
#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048
#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c
#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050
#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054
#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058
#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c
#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060
#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064
#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068
#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c
#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070
#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074
#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078
#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c
#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080
#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084
#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088
#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c
#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090
#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094
#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098
#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c
#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0
#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4
#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8
#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac
#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0
#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4
#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8
#define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc
#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4
#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8
#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4
#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8
#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
#define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110
#define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114
#endif
arch/arm/mach-omap2/scrm54xx.h 0 → 100644
View file @ b0f392c6
/*
* OMAP54XX SCRM registers and bitfields
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
#define OMAP5_SCRM_BASE 0x4ae0a000
#define OMAP54XX_SCRM_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
/* SCRM */
/* SCRM.SCRM register offsets */
#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000
#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000)
#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100
#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100)
#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104
#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104)
#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110
#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110)
#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118
#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118)
#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c
#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c)
#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200
#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200)
#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204
#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204)
#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208
#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208)
#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210
#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210)
#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214
#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214)
#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218
#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218)
#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c
#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c)
#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220
#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220)
#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224
#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224)
#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234
#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234)
#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310
#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310)
#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314
#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314)
#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318
#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318)
#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c
#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c)
#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320
#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320)
#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324
#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324)
#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400
#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400)
#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418
#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418)
#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c
#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c)
#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420)
#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510
#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510)
#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514
#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514)
#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518
#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518)
#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c
#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c)
/*
* Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
* AUXCLKREQ5, D2DCLKREQ
*/
#define OMAP5_ACCURACY_SHIFT 1
#define OMAP5_ACCURACY_WIDTH 0x1
#define OMAP5_ACCURACY_MASK (1 << 1)
/* Used by APEWARMRSTST */
#define OMAP5_APEWARMRSTST_SHIFT 1
#define OMAP5_APEWARMRSTST_WIDTH 0x1
#define OMAP5_APEWARMRSTST_MASK (1 << 1)
/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
#define OMAP5_CLKDIV_SHIFT 16
#define OMAP5_CLKDIV_WIDTH 0x4
#define OMAP5_CLKDIV_MASK (0xf << 16)
/* Used by D2DCLKM, MODEMCLKM */
#define OMAP5_CLK_32KHZ_SHIFT 0
#define OMAP5_CLK_32KHZ_WIDTH 0x1
#define OMAP5_CLK_32KHZ_MASK (1 << 0)
/* Used by D2DRSTCTRL, MODEMRSTCTRL */
#define OMAP5_COLDRST_SHIFT 0
#define OMAP5_COLDRST_WIDTH 0x1
#define OMAP5_COLDRST_MASK (1 << 0)
/* Used by D2DWARMRSTST */
#define OMAP5_D2DWARMRSTST_SHIFT 3
#define OMAP5_D2DWARMRSTST_WIDTH 0x1
#define OMAP5_D2DWARMRSTST_MASK (1 << 3)
/* Used by AUXCLK0 */
#define OMAP5_DISABLECLK_SHIFT 9
#define OMAP5_DISABLECLK_WIDTH 0x1
#define OMAP5_DISABLECLK_MASK (1 << 9)
/* Used by CLKSETUPTIME */
#define OMAP5_DOWNTIME_SHIFT 16
#define OMAP5_DOWNTIME_WIDTH 0x6
#define OMAP5_DOWNTIME_MASK (0x3f << 16)
/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
#define OMAP5_ENABLE_SHIFT 8
#define OMAP5_ENABLE_WIDTH 0x1
#define OMAP5_ENABLE_MASK (1 << 8)
/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
#define OMAP5_ENABLE_0_0_SHIFT 0
#define OMAP5_ENABLE_0_0_WIDTH 0x1
#define OMAP5_ENABLE_0_0_MASK (1 << 0)
/* Used by ALTCLKSRC */
#define OMAP5_ENABLE_EXT_SHIFT 3
#define OMAP5_ENABLE_EXT_WIDTH 0x1
#define OMAP5_ENABLE_EXT_MASK (1 << 3)
/* Used by ALTCLKSRC */
#define OMAP5_ENABLE_INT_SHIFT 2
#define OMAP5_ENABLE_INT_WIDTH 0x1
#define OMAP5_ENABLE_INT_MASK (1 << 2)
/* Used by EXTWARMRSTST */
#define OMAP5_EXTWARMRSTST_SHIFT 0
#define OMAP5_EXTWARMRSTST_WIDTH 0x1
#define OMAP5_EXTWARMRSTST_MASK (1 << 0)
/*
* Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
* AUXCLKREQ5
*/
#define OMAP5_MAPPING_SHIFT 2
#define OMAP5_MAPPING_WIDTH 0x3
#define OMAP5_MAPPING_MASK (0x7 << 2)
/* Used by ALTCLKSRC */
#define OMAP5_MODE_SHIFT 0
#define OMAP5_MODE_WIDTH 0x2
#define OMAP5_MODE_MASK (0x3 << 0)
/* Used by MODEMWARMRSTST */
#define OMAP5_MODEMWARMRSTST_SHIFT 2
#define OMAP5_MODEMWARMRSTST_WIDTH 0x1
#define OMAP5_MODEMWARMRSTST_MASK (1 << 2)
/*
* Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
* AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
* D2DCLKREQ, EXTCLKREQ, PWRREQ
*/
#define OMAP5_POLARITY_SHIFT 0
#define OMAP5_POLARITY_WIDTH 0x1
#define OMAP5_POLARITY_MASK (1 << 0)
/* Used by EXTPWRONRSTCTRL */
#define OMAP5_PWRONRST_SHIFT 1
#define OMAP5_PWRONRST_WIDTH 0x1
#define OMAP5_PWRONRST_MASK (1 << 1)
/* Used by REVISION_SCRM */
#define OMAP5_REV_SHIFT 0
#define OMAP5_REV_WIDTH 0x8
#define OMAP5_REV_MASK (0xff << 0)
/* Used by RSTTIME */
#define OMAP5_RSTTIME_SHIFT 0
#define OMAP5_RSTTIME_WIDTH 0x4
#define OMAP5_RSTTIME_MASK (0xf << 0)
/* Used by CLKSETUPTIME */
#define OMAP5_SETUPTIME_SHIFT 0
#define OMAP5_SETUPTIME_WIDTH 0xc
#define OMAP5_SETUPTIME_MASK (0xfff << 0)
/* Used by PMICSETUPTIME */
#define OMAP5_SLEEPTIME_SHIFT 0
#define OMAP5_SLEEPTIME_WIDTH 0x6
#define OMAP5_SLEEPTIME_MASK (0x3f << 0)
/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
#define OMAP5_SRCSELECT_SHIFT 1
#define OMAP5_SRCSELECT_WIDTH 0x2
#define OMAP5_SRCSELECT_MASK (0x3 << 1)
/* Used by D2DCLKM */
#define OMAP5_SYSCLK_SHIFT 1
#define OMAP5_SYSCLK_WIDTH 0x1
#define OMAP5_SYSCLK_MASK (1 << 1)
/* Used by PMICSETUPTIME */
#define OMAP5_WAKEUPTIME_SHIFT 16
#define OMAP5_WAKEUPTIME_WIDTH 0x6
#define OMAP5_WAKEUPTIME_MASK (0x3f << 16)
/* Used by D2DRSTCTRL, MODEMRSTCTRL */
#define OMAP5_WARMRST_SHIFT 1
#define OMAP5_WARMRST_WIDTH 0x1
#define OMAP5_WARMRST_MASK (1 << 1)
#endif
arch/arm/mach-omap2/voltage.h
View file @ b0f392c6
......@@ -171,6 +171,7 @@ extern void omap2xxx_voltagedomains_init(void);
extern void omap3xxx_voltagedomains_init(void);
extern void am33xx_voltagedomains_init(void);
extern void omap44xx_voltagedomains_init(void);
extern void omap54xx_voltagedomains_init(void);
struct voltagedomain *voltdm_lookup(const char *name);
void voltdm_init(struct voltagedomain **voltdm_list);
......
arch/arm/mach-omap2/voltagedomains54xx_data.c 0 → 100644
View file @ b0f392c6
/*
* OMAP5 Voltage Management Routines
*
* Based on voltagedomains44xx_data.c
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/init.h>
#include "common.h"
#include "prm54xx.h"
#include "voltage.h"
#include "omap_opp_data.h"
#include "vc.h"
#include "vp.h"
static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = {
.voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
};
static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = {
.voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET,
};
static const struct omap_vfsm_instance omap5_vdd_core_vfsm = {
.voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
};
static struct voltagedomain omap5_voltdm_mpu = {
.name = "mpu",
.scalable = true,
.read = omap4_prm_vcvp_read,
.write = omap4_prm_vcvp_write,
.rmw = omap4_prm_vcvp_rmw,
.vc = &omap4_vc_mpu,
.vfsm = &omap5_vdd_mpu_vfsm,
.vp = &omap4_vp_mpu,
};
static struct voltagedomain omap5_voltdm_mm = {
.name = "mm",
.scalable = true,
.read = omap4_prm_vcvp_read,
.write = omap4_prm_vcvp_write,
.rmw = omap4_prm_vcvp_rmw,
.vc = &omap4_vc_iva,
.vfsm = &omap5_vdd_mm_vfsm,
.vp = &omap4_vp_iva,
};
static struct voltagedomain omap5_voltdm_core = {
.name = "core",
.scalable = true,
.read = omap4_prm_vcvp_read,
.write = omap4_prm_vcvp_write,
.rmw = omap4_prm_vcvp_rmw,
.vc = &omap4_vc_core,
.vfsm = &omap5_vdd_core_vfsm,
.vp = &omap4_vp_core,
};
static struct voltagedomain omap5_voltdm_wkup = {
.name = "wkup",
};
static struct voltagedomain *voltagedomains_omap5[] __initdata = {
&omap5_voltdm_mpu,
&omap5_voltdm_mm,
&omap5_voltdm_core,
&omap5_voltdm_wkup,
NULL,
};
static const char *sys_clk_name __initdata = "sys_clkin";
void __init omap54xx_voltagedomains_init(void)
{
struct voltagedomain *voltdm;
int i;
/*
* XXX Will depend on the process, validation, and binning
* for the currently-running IC. Use OMAP4 data for time being.
*/
#ifdef CONFIG_PM_OPP
omap5_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
omap5_voltdm_mm.volt_data = omap446x_vdd_iva_volt_data;
omap5_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
#endif
for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++)
voltdm->sys_clk.name = sys_clk_name;
voltdm_init(voltagedomains_omap5);
};
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