Skip to content

L
linux
Commit b1bd42aa authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files
Options

staging: xgifb: delete the driver 

There has not been any real work done on cleaning this driver up and
getting it out of the staging tree in years.  Also, no new fb drivers
are being added to the tree, so it should be converted into a drm driver
as well.

Due to the lack of interest in this codebase, just drop it.

Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
Cc: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Reported-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 9a413526
Show whitespace changes
Inline Side-by-side
Showing with 0 additions and 12554 deletions
MAINTAINERS
View file @ b1bd42aa
...@@ -14471,11 +14471,6 @@ L: linux-wireless@vger.kernel.org ...@@ -14471,11 +14471,6 @@ L: linux-wireless@vger.kernel.org
S: Supported S: Supported
F: drivers/staging/wilc1000/ F: drivers/staging/wilc1000/
STAGING - XGI Z7,Z9,Z11 PCI DISPLAY DRIVER
M: Arnaud Patard <arnaud.patard@rtp-net.org>
S: Odd Fixes
F: drivers/staging/xgifb/
STAGING SUBSYSTEM STAGING SUBSYSTEM
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
......
drivers/staging/Kconfig
View file @ b1bd42aa
...@@ -56,8 +56,6 @@ source "drivers/staging/iio/Kconfig" ...@@ -56,8 +56,6 @@ source "drivers/staging/iio/Kconfig"
source "drivers/staging/sm750fb/Kconfig" source "drivers/staging/sm750fb/Kconfig"
source "drivers/staging/xgifb/Kconfig"
source "drivers/staging/emxx_udc/Kconfig" source "drivers/staging/emxx_udc/Kconfig"
source "drivers/staging/speakup/Kconfig" source "drivers/staging/speakup/Kconfig"
......
drivers/staging/Makefile
View file @ b1bd42aa
...@@ -20,7 +20,6 @@ obj-$(CONFIG_VT6656) += vt6656/ ...@@ -20,7 +20,6 @@ obj-$(CONFIG_VT6656) += vt6656/
obj-$(CONFIG_VME_BUS) += vme/ obj-$(CONFIG_VME_BUS) += vme/
obj-$(CONFIG_IIO) += iio/ obj-$(CONFIG_IIO) += iio/
obj-$(CONFIG_FB_SM750) += sm750fb/ obj-$(CONFIG_FB_SM750) += sm750fb/
obj-$(CONFIG_FB_XGI) += xgifb/
obj-$(CONFIG_USB_EMXX) += emxx_udc/ obj-$(CONFIG_USB_EMXX) += emxx_udc/
obj-$(CONFIG_SPEAKUP) += speakup/ obj-$(CONFIG_SPEAKUP) += speakup/
obj-$(CONFIG_MFD_NVEC) += nvec/ obj-$(CONFIG_MFD_NVEC) += nvec/
......
drivers/staging/xgifb/Kconfig deleted 100644 → 0
View file @ 9a413526
config FB_XGI
tristate "XGI display support"
depends on FB && PCI
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
help
This driver supports notebooks with XGI Z7,Z9,Z11 PCI chips.
Say Y if you have such a graphics card.
To compile this driver as a module, choose M here: the
module will be called xgifb.ko
drivers/staging/xgifb/Makefile deleted 100644 → 0
View file @ 9a413526
obj-$(CONFIG_FB_XGI) += xgifb.o
xgifb-y := XGI_main_26.o vb_init.o vb_setmode.o
drivers/staging/xgifb/TODO deleted 100644 → 0
View file @ 9a413526
This drivers still needs a lot of work. I can list all cleanups to do but it's
going to be long. So, I'm writing "cleanups" and not the list.
Arnaud
TODO:
- clean ups
- sort out dup ids with SiS driver
- remove useless/wrong/unused code...
- get rid of non-linux related stuff
This needs to become a drm driver, the fbdev subsystem doesn't take new drivers
anymore.
Please send patches to:
Arnaud Patard <arnaud.patard@rtp-net.org>
drivers/staging/xgifb/XGI_main.h deleted 100644 → 0
View file @ 9a413526
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _XGIFB_MAIN
#define _XGIFB_MAIN
/* ------------------- Constant Definitions ------------------------- */
#include "XGIfb.h"
#include "vb_def.h"
#define PCI_DEVICE_ID_XGI_42 0x042
#define PCI_DEVICE_ID_XGI_27 0x027
static const struct pci_device_id xgifb_pci_table[] = {
{PCI_DEVICE(PCI_VENDOR_ID_XGI, PCI_DEVICE_ID_XGI_20)},
{PCI_DEVICE(PCI_VENDOR_ID_XGI, PCI_DEVICE_ID_XGI_27)},
{PCI_DEVICE(PCI_VENDOR_ID_XGI, PCI_DEVICE_ID_XGI_40)},
{PCI_DEVICE(PCI_VENDOR_ID_XGI, PCI_DEVICE_ID_XGI_42)},
{0}
};
MODULE_DEVICE_TABLE(pci, xgifb_pci_table);
#define IND_XGI_SCRATCH_REG_CR30 0x30 /* CRs */
#define IND_XGI_SCRATCH_REG_CR31 0x31
#define IND_XGI_SCRATCH_REG_CR32 0x32
#define IND_XGI_SCRATCH_REG_CR33 0x33
#define IND_XGI_LCD_PANEL 0x36
#define IND_XGI_SCRATCH_REG_CR37 0x37
#define XGI_DRAM_SIZE_MASK 0xF0 /*SR14 */
#define XGI_DRAM_SIZE_1MB 0x00
#define XGI_DRAM_SIZE_2MB 0x01
#define XGI_DRAM_SIZE_4MB 0x02
#define XGI_DRAM_SIZE_8MB 0x03
#define XGI_DRAM_SIZE_16MB 0x04
#define XGI_DRAM_SIZE_32MB 0x05
#define XGI_DRAM_SIZE_64MB 0x06
#define XGI_DRAM_SIZE_128MB 0x07
#define XGI_DRAM_SIZE_256MB 0x08
/* ------------------- Global Variables ----------------------------- */
/* display status */
static int XGIfb_crt1off;
static int XGIfb_forcecrt1 = -1;
/* global flags */
static int XGIfb_tvmode;
static int enable_dstn;
static int XGIfb_ypan = -1;
/* TW: CRT2 type (for overriding autodetection) */
static int XGIfb_crt2type = -1;
/* PR: Tv plug type (for overriding autodetection) */
static int XGIfb_tvplug = -1;
#define MD_XGI315 1
/* mode table */
static const struct _XGIbios_mode {
u8 mode_no;
u16 vesa_mode_no_1; /* "XGI defined" VESA mode number */
u16 vesa_mode_no_2; /* Real VESA mode numbers */
u16 xres;
u16 yres;
u16 bpp;
u8 chipset;
} XGIbios_mode[] = {
{ 0x56, 0x0000, 0x0000, 320, 240, 16, MD_XGI315 },
{ 0x5A, 0x0000, 0x0000, 320, 480, 8, MD_XGI315 },
{ 0x5B, 0x0000, 0x0000, 320, 480, 16, MD_XGI315 },
{ 0x2E, 0x0101, 0x0101, 640, 480, 8, MD_XGI315 },
{ 0x44, 0x0111, 0x0111, 640, 480, 16, MD_XGI315 },
{ 0x62, 0x013a, 0x0112, 640, 480, 32, MD_XGI315 },
{ 0x31, 0x0000, 0x0000, 720, 480, 8, MD_XGI315 },
{ 0x33, 0x0000, 0x0000, 720, 480, 16, MD_XGI315 },
{ 0x35, 0x0000, 0x0000, 720, 480, 32, MD_XGI315 },
{ 0x32, 0x0000, 0x0000, 720, 576, 8, MD_XGI315 },
{ 0x34, 0x0000, 0x0000, 720, 576, 16, MD_XGI315 },
{ 0x36, 0x0000, 0x0000, 720, 576, 32, MD_XGI315 },
{ 0x36, 0x0000, 0x0000, 720, 576, 32, MD_XGI315 },
{ 0x70, 0x0000, 0x0000, 800, 480, 8, MD_XGI315 },
{ 0x7a, 0x0000, 0x0000, 800, 480, 16, MD_XGI315 },
{ 0x76, 0x0000, 0x0000, 800, 480, 32, MD_XGI315 },
{ 0x30, 0x0103, 0x0103, 800, 600, 8, MD_XGI315 },
#define DEFAULT_MODE 17 /* index for 800x600x16 */
{ 0x47, 0x0114, 0x0114, 800, 600, 16, MD_XGI315 },
{ 0x63, 0x013b, 0x0115, 800, 600, 32, MD_XGI315 },
{ 0x71, 0x0000, 0x0000, 1024, 576, 8, MD_XGI315 },
{ 0x74, 0x0000, 0x0000, 1024, 576, 16, MD_XGI315 },
{ 0x77, 0x0000, 0x0000, 1024, 576, 32, MD_XGI315 },
{ 0x77, 0x0000, 0x0000, 1024, 576, 32, MD_XGI315 },
{ 0x20, 0x0000, 0x0000, 1024, 600, 8, },
{ 0x21, 0x0000, 0x0000, 1024, 600, 16, },
{ 0x22, 0x0000, 0x0000, 1024, 600, 32, },
{ 0x38, 0x0105, 0x0105, 1024, 768, 8, MD_XGI315 },
{ 0x4A, 0x0117, 0x0117, 1024, 768, 16, MD_XGI315 },
{ 0x64, 0x013c, 0x0118, 1024, 768, 32, MD_XGI315 },
{ 0x64, 0x013c, 0x0118, 1024, 768, 32, MD_XGI315 },
{ 0x23, 0x0000, 0x0000, 1152, 768, 8, },
{ 0x24, 0x0000, 0x0000, 1152, 768, 16, },
{ 0x25, 0x0000, 0x0000, 1152, 768, 32, },
{ 0x79, 0x0000, 0x0000, 1280, 720, 8, MD_XGI315 },
{ 0x75, 0x0000, 0x0000, 1280, 720, 16, MD_XGI315 },
{ 0x78, 0x0000, 0x0000, 1280, 720, 32, MD_XGI315 },
{ 0x23, 0x0000, 0x0000, 1280, 768, 8, MD_XGI315 },
{ 0x24, 0x0000, 0x0000, 1280, 768, 16, MD_XGI315 },
{ 0x25, 0x0000, 0x0000, 1280, 768, 32, MD_XGI315 },
{ 0x7C, 0x0000, 0x0000, 1280, 960, 8, MD_XGI315 },
{ 0x7D, 0x0000, 0x0000, 1280, 960, 16, MD_XGI315 },
{ 0x7E, 0x0000, 0x0000, 1280, 960, 32, MD_XGI315 },
{ 0x3A, 0x0107, 0x0107, 1280, 1024, 8, MD_XGI315 },
{ 0x4D, 0x011a, 0x011a, 1280, 1024, 16, MD_XGI315 },
{ 0x65, 0x013d, 0x011b, 1280, 1024, 32, MD_XGI315 },
{ 0x26, 0x0000, 0x0000, 1400, 1050, 8, MD_XGI315 },
{ 0x27, 0x0000, 0x0000, 1400, 1050, 16, MD_XGI315 },
{ 0x28, 0x0000, 0x0000, 1400, 1050, 32, MD_XGI315 },
{ 0x3C, 0x0130, 0x011c, 1600, 1200, 8, MD_XGI315 },
{ 0x3D, 0x0131, 0x011e, 1600, 1200, 16, MD_XGI315 },
{ 0x66, 0x013e, 0x011f, 1600, 1200, 32, MD_XGI315 },
{ 0x68, 0x013f, 0x0000, 1920, 1440, 8, MD_XGI315 },
{ 0x69, 0x0140, 0x0000, 1920, 1440, 16, MD_XGI315 },
{ 0x6B, 0x0141, 0x0000, 1920, 1440, 32, MD_XGI315 },
{ 0x6c, 0x0000, 0x0000, 2048, 1536, 8, MD_XGI315 },
{ 0x6d, 0x0000, 0x0000, 2048, 1536, 16, MD_XGI315 },
{ 0x6e, 0x0000, 0x0000, 2048, 1536, 32, MD_XGI315 },
{ 0 },
};
static const unsigned short XGI310paneltype[] = {
LCD_UNKNOWN, LCD_800x600, LCD_1024x768, LCD_1280x1024,
LCD_640x480, LCD_1024x600, LCD_1152x864, LCD_1280x960,
LCD_1152x768, LCD_1400x1050, LCD_1280x768, LCD_1600x1200,
LCD_1024x768, LCD_1024x768, LCD_1024x768};
static const struct _XGI_crt2type {
char name[10];
int type_no;
int tvplug_no;
} XGI_crt2type[] = {
{"NONE", 0, -1},
{"LCD", XGIFB_DISP_LCD, -1},
{"TV", XGIFB_DISP_TV, -1},
{"VGA", XGIFB_DISP_CRT, -1},
{"SVIDEO", XGIFB_DISP_TV, TVPLUG_SVIDEO},
{"COMPOSITE", XGIFB_DISP_TV, TVPLUG_COMPOSITE},
{"SCART", XGIFB_DISP_TV, TVPLUG_SCART},
{"none", 0, -1},
{"lcd", XGIFB_DISP_LCD, -1},
{"tv", XGIFB_DISP_TV, -1},
{"vga", XGIFB_DISP_CRT, -1},
{"svideo", XGIFB_DISP_TV, TVPLUG_SVIDEO},
{"composite", XGIFB_DISP_TV, TVPLUG_COMPOSITE},
{"scart", XGIFB_DISP_TV, TVPLUG_SCART},
{"\0", -1, -1}
};
/* TV standard */
static const struct _XGI_tvtype {
char name[6];
int type_no;
} XGI_tvtype[] = {
{"PAL", 1},
{"NTSC", 2},
{"pal", 1},
{"ntsc", 2},
{"\0", -1}
};
static const struct _XGI_vrate {
u16 idx;
u16 xres;
u16 yres;
u16 refresh;
} XGIfb_vrate[] = {
{1, 640, 480, 60}, {2, 640, 480, 72},
{3, 640, 480, 75}, {4, 640, 480, 85},
{5, 640, 480, 100}, {6, 640, 480, 120},
{7, 640, 480, 160}, {8, 640, 480, 200},
{1, 720, 480, 60},
{1, 720, 576, 58},
{1, 800, 480, 60}, {2, 800, 480, 75}, {3, 800, 480, 85},
{1, 800, 600, 60}, {2, 800, 600, 72}, {3, 800, 600, 75},
{4, 800, 600, 85}, {5, 800, 600, 100},
{6, 800, 600, 120}, {7, 800, 600, 160},
{1, 1024, 768, 60}, {2, 1024, 768, 70}, {3, 1024, 768, 75},
{4, 1024, 768, 85}, {5, 1024, 768, 100}, {6, 1024, 768, 120},
{1, 1024, 576, 60}, {2, 1024, 576, 75}, {3, 1024, 576, 85},
{1, 1024, 600, 60},
{1, 1152, 768, 60},
{1, 1280, 720, 60}, {2, 1280, 720, 75}, {3, 1280, 720, 85},
{1, 1280, 768, 60},
{1, 1280, 1024, 60}, {2, 1280, 1024, 75}, {3, 1280, 1024, 85},
{1, 1280, 960, 70},
{1, 1400, 1050, 60},
{1, 1600, 1200, 60}, {2, 1600, 1200, 65},
{3, 1600, 1200, 70}, {4, 1600, 1200, 75},
{5, 1600, 1200, 85}, {6, 1600, 1200, 100},
{7, 1600, 1200, 120},
{1, 1920, 1440, 60}, {2, 1920, 1440, 65},
{3, 1920, 1440, 70}, {4, 1920, 1440, 75},
{5, 1920, 1440, 85}, {6, 1920, 1440, 100},
{1, 2048, 1536, 60}, {2, 2048, 1536, 65},
{3, 2048, 1536, 70}, {4, 2048, 1536, 75},
{5, 2048, 1536, 85},
{0, 0, 0, 0}
};
static const struct _XGI_TV_filter {
u8 filter[9][4];
} XGI_TV_filter[] = {
{ { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_0 */
{0x00, 0xE0, 0x10, 0x60},
{0x00, 0xEE, 0x10, 0x44},
{0x00, 0xF4, 0x10, 0x38},
{0xF8, 0xF4, 0x18, 0x38},
{0xFC, 0xFB, 0x14, 0x2A},
{0x00, 0x00, 0x10, 0x20},
{0x00, 0x04, 0x10, 0x18},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_1 */
{0x00, 0xE0, 0x10, 0x60},
{0x00, 0xEE, 0x10, 0x44},
{0x00, 0xF4, 0x10, 0x38},
{0xF8, 0xF4, 0x18, 0x38},
{0xFC, 0xFB, 0x14, 0x2A},
{0x00, 0x00, 0x10, 0x20},
{0x00, 0x04, 0x10, 0x18},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_2 */
{0xF5, 0xEE, 0x1B, 0x44},
{0xF8, 0xF4, 0x18, 0x38},
{0xEB, 0x04, 0x25, 0x18},
{0xF1, 0x05, 0x1F, 0x16},
{0xF6, 0x06, 0x1A, 0x14},
{0xFA, 0x06, 0x16, 0x14},
{0x00, 0x04, 0x10, 0x18},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_3 */
{0xF1, 0x04, 0x1F, 0x18},
{0xEE, 0x0D, 0x22, 0x06},
{0xF7, 0x06, 0x19, 0x14},
{0xF4, 0x0B, 0x1C, 0x0A},
{0xFA, 0x07, 0x16, 0x12},
{0xF9, 0x0A, 0x17, 0x0C},
{0x00, 0x07, 0x10, 0x12},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_4 */
{0x00, 0xE0, 0x10, 0x60},
{0x00, 0xEE, 0x10, 0x44},
{0x00, 0xF4, 0x10, 0x38},
{0xF8, 0xF4, 0x18, 0x38},
{0xFC, 0xFB, 0x14, 0x2A},
{0x00, 0x00, 0x10, 0x20},
{0x00, 0x04, 0x10, 0x18},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_5 */
{0xF5, 0xEE, 0x1B, 0x44},
{0xF8, 0xF4, 0x18, 0x38},
{0xEB, 0x04, 0x25, 0x18},
{0xF1, 0x05, 0x1F, 0x16},
{0xF6, 0x06, 0x1A, 0x14},
{0xFA, 0x06, 0x16, 0x14},
{0x00, 0x04, 0x10, 0x18},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_6 */
{0xEB, 0x04, 0x25, 0x18},
{0xE7, 0x0E, 0x29, 0x04},
{0xEE, 0x0C, 0x22, 0x08},
{0xF6, 0x0B, 0x1A, 0x0A},
{0xF9, 0x0A, 0x17, 0x0C},
{0xFC, 0x0A, 0x14, 0x0C},
{0x00, 0x08, 0x10, 0x10},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_7 */
{0xEC, 0x02, 0x24, 0x1C},
{0xF2, 0x04, 0x1E, 0x18},
{0xEB, 0x15, 0x25, 0xF6},
{0xF4, 0x10, 0x1C, 0x00},
{0xF8, 0x0F, 0x18, 0x02},
{0x00, 0x04, 0x10, 0x18},
{0x01, 0x06, 0x0F, 0x14},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_0 */
{0x00, 0xE0, 0x10, 0x60},
{0x00, 0xEE, 0x10, 0x44},
{0x00, 0xF4, 0x10, 0x38},
{0xF8, 0xF4, 0x18, 0x38},
{0xFC, 0xFB, 0x14, 0x2A},
{0x00, 0x00, 0x10, 0x20},
{0x00, 0x04, 0x10, 0x18},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_1 */
{0x00, 0xE0, 0x10, 0x60},
{0x00, 0xEE, 0x10, 0x44},
{0x00, 0xF4, 0x10, 0x38},
{0xF8, 0xF4, 0x18, 0x38},
{0xFC, 0xFB, 0x14, 0x2A},
{0x00, 0x00, 0x10, 0x20},
{0x00, 0x04, 0x10, 0x18},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_2 */
{0xF5, 0xEE, 0x1B, 0x44},
{0xF8, 0xF4, 0x18, 0x38},
{0xF1, 0xF7, 0x01, 0x32},
{0xF5, 0xFB, 0x1B, 0x2A},
{0xF9, 0xFF, 0x17, 0x22},
{0xFB, 0x01, 0x15, 0x1E},
{0x00, 0x04, 0x10, 0x18},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_3 */
{0xF5, 0xFB, 0x1B, 0x2A},
{0xEE, 0xFE, 0x22, 0x24},
{0xF3, 0x00, 0x1D, 0x20},
{0xF9, 0x03, 0x17, 0x1A},
{0xFB, 0x02, 0x14, 0x1E},
{0xFB, 0x04, 0x15, 0x18},
{0x00, 0x06, 0x10, 0x14},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_4 */
{0x00, 0xE0, 0x10, 0x60},
{0x00, 0xEE, 0x10, 0x44},
{0x00, 0xF4, 0x10, 0x38},
{0xF8, 0xF4, 0x18, 0x38},
{0xFC, 0xFB, 0x14, 0x2A},
{0x00, 0x00, 0x10, 0x20},
{0x00, 0x04, 0x10, 0x18},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_5 */
{0xF5, 0xEE, 0x1B, 0x44},
{0xF8, 0xF4, 0x18, 0x38},
{0xF1, 0xF7, 0x1F, 0x32},
{0xF5, 0xFB, 0x1B, 0x2A},
{0xF9, 0xFF, 0x17, 0x22},
{0xFB, 0x01, 0x15, 0x1E},
{0x00, 0x04, 0x10, 0x18},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_6 */
{0xF5, 0xEE, 0x1B, 0x2A},
{0xEE, 0xFE, 0x22, 0x24},
{0xF3, 0x00, 0x1D, 0x20},
{0xF9, 0x03, 0x17, 0x1A},
{0xFB, 0x02, 0x14, 0x1E},
{0xFB, 0x04, 0x15, 0x18},
{0x00, 0x06, 0x10, 0x14},
{0xFF, 0xFF, 0xFF, 0xFF} } },
{ { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_7 */
{0xF5, 0xEE, 0x1B, 0x44},
{0xF8, 0xF4, 0x18, 0x38},
{0xFC, 0xFB, 0x14, 0x2A},
{0xEB, 0x05, 0x25, 0x16},
{0xF1, 0x05, 0x1F, 0x16},
{0xFA, 0x07, 0x16, 0x12},
{0x00, 0x07, 0x10, 0x12},
{0xFF, 0xFF, 0xFF, 0xFF} } }
};
static int filter = -1;
#endif
drivers/staging/xgifb/XGI_main_26.c deleted 100644 → 0
View file @ 9a413526
// SPDX-License-Identifier: GPL-2.0
/*
* XG20, XG21, XG40, XG42 frame buffer device
* for Linux kernels 2.5.x, 2.6.x
* Base on TW's sis fbdev code.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/sizes.h>
#include <linux/module.h>
#include <linux/pci.h>
#include "XGI_main.h"
#include "vb_init.h"
#include "vb_util.h"
#include "vb_setmode.h"
#define Index_CR_GPIO_Reg1 0x48
#define Index_CR_GPIO_Reg3 0x4a
#define GPIOG_EN BIT(6)
#define GPIOG_READ BIT(1)
static char *forcecrt2type;
static char *mode;
static int vesa = -1;
static unsigned int refresh_rate;
/* -------------------- Macro definitions ---------------------------- */
#ifdef DEBUG
static void dumpVGAReg(struct xgifb_video_info *xgifb_info)
{
struct vb_device_info *vb = &xgifb_info->dev_info;
u8 i, reg;
xgifb_reg_set(vb->P3c4, 0x05, 0x86);
for (i = 0; i < 0x4f; i++) {
reg = xgifb_reg_get(vb->P3c4, i);
pr_debug("o 3c4 %x\n", i);
pr_debug("i 3c5 => %x\n", reg);
}
for (i = 0; i < 0xF0; i++) {
reg = xgifb_reg_get(vb->P3d4, i);
pr_debug("o 3d4 %x\n", i);
pr_debug("i 3d5 => %x\n", reg);
}
}
#else
static inline void dumpVGAReg(struct xgifb_video_info *xgifb_info)
{
}
#endif
/* --------------- Hardware Access Routines -------------------------- */
static int XGIfb_mode_rate_to_dclock(struct vb_device_info *XGI_Pr,
struct xgi_hw_device_info *HwDeviceExtension,
unsigned char modeno)
{
unsigned short ModeNo = modeno;
unsigned short ModeIdIndex = 0, ClockIndex = 0;
unsigned short RefreshRateTableIndex = 0;
InitTo330Pointer(HwDeviceExtension->jChipType, XGI_Pr);
XGI_SearchModeID(ModeNo, &ModeIdIndex);
RefreshRateTableIndex = XGI_GetRatePtrCRT2(HwDeviceExtension, ModeNo,
ModeIdIndex, XGI_Pr);
ClockIndex = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRTVCLK;
return XGI_VCLKData[ClockIndex].CLOCK * 1000;
}
static int XGIfb_mode_rate_to_ddata(struct vb_device_info *XGI_Pr,
struct xgi_hw_device_info *HwDeviceExtension,
unsigned char modeno, u32 *left_margin,
u32 *right_margin, u32 *upper_margin,
u32 *lower_margin, u32 *hsync_len,
u32 *vsync_len, u32 *sync, u32 *vmode)
{
unsigned short ModeNo = modeno;
unsigned short ModeIdIndex, index = 0;
unsigned short RefreshRateTableIndex = 0;
unsigned short VRE, VBE, VRS, VDE;
unsigned short HRE, HBE, HRS, HDE;
unsigned char sr_data, cr_data, cr_data2;
int B, C, D, F, temp, j;
InitTo330Pointer(HwDeviceExtension->jChipType, XGI_Pr);
if (!XGI_SearchModeID(ModeNo, &ModeIdIndex))
return 0;
RefreshRateTableIndex = XGI_GetRatePtrCRT2(HwDeviceExtension, ModeNo,
ModeIdIndex, XGI_Pr);
index = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
sr_data = XGI_CRT1Table[index].CR[5];
HDE = XGI330_RefIndex[RefreshRateTableIndex].XRes >> 3;
cr_data = XGI_CRT1Table[index].CR[3];
/* Horizontal retrace (=sync) start */
HRS = (cr_data & 0xff) | ((unsigned short)(sr_data & 0xC0) << 2);
F = HRS - HDE - 3;
sr_data = XGI_CRT1Table[index].CR[6];
cr_data = XGI_CRT1Table[index].CR[2];
cr_data2 = XGI_CRT1Table[index].CR[4];
/* Horizontal blank end */
HBE = (cr_data & 0x1f) | ((unsigned short)(cr_data2 & 0x80) >> 2)
| ((unsigned short)(sr_data & 0x03) << 6);
/* Horizontal retrace (=sync) end */
HRE = (cr_data2 & 0x1f) | ((sr_data & 0x04) << 3);
temp = HBE - ((HDE - 1) & 255);
B = (temp > 0) ? temp : (temp + 256);
temp = HRE - ((HDE + F + 3) & 63);
C = (temp > 0) ? temp : (temp + 64);
D = B - F - C;
*left_margin = D * 8;
*right_margin = F * 8;
*hsync_len = C * 8;
sr_data = XGI_CRT1Table[index].CR[14];
cr_data2 = XGI_CRT1Table[index].CR[9];
VDE = XGI330_RefIndex[RefreshRateTableIndex].YRes;
cr_data = XGI_CRT1Table[index].CR[10];
/* Vertical retrace (=sync) start */
VRS = (cr_data & 0xff) | ((unsigned short)(cr_data2 & 0x04) << 6)
| ((unsigned short)(cr_data2 & 0x80) << 2)
| ((unsigned short)(sr_data & 0x08) << 7);
F = VRS + 1 - VDE;
cr_data = XGI_CRT1Table[index].CR[13];
/* Vertical blank end */
VBE = (cr_data & 0xff) | ((unsigned short)(sr_data & 0x10) << 4);
temp = VBE - ((VDE - 1) & 511);
B = (temp > 0) ? temp : (temp + 512);
cr_data = XGI_CRT1Table[index].CR[11];
/* Vertical retrace (=sync) end */
VRE = (cr_data & 0x0f) | ((sr_data & 0x20) >> 1);
temp = VRE - ((VDE + F - 1) & 31);
C = (temp > 0) ? temp : (temp + 32);
D = B - F - C;
*upper_margin = D;
*lower_margin = F;
*vsync_len = C;
if (XGI330_RefIndex[RefreshRateTableIndex].Ext_InfoFlag & 0x8000)
*sync &= ~FB_SYNC_VERT_HIGH_ACT;
else
*sync |= FB_SYNC_VERT_HIGH_ACT;
if (XGI330_RefIndex[RefreshRateTableIndex].Ext_InfoFlag & 0x4000)
*sync &= ~FB_SYNC_HOR_HIGH_ACT;
else
*sync |= FB_SYNC_HOR_HIGH_ACT;
*vmode = FB_VMODE_NONINTERLACED;
if (XGI330_RefIndex[RefreshRateTableIndex].Ext_InfoFlag & 0x0080) {
*vmode = FB_VMODE_INTERLACED;
} else {
j = 0;
while (XGI330_EModeIDTable[j].Ext_ModeID != 0xff) {
if (XGI330_EModeIDTable[j].Ext_ModeID ==
XGI330_RefIndex[RefreshRateTableIndex].ModeID) {
if (XGI330_EModeIDTable[j].Ext_ModeFlag &
DoubleScanMode) {
*vmode = FB_VMODE_DOUBLE;
}
break;
}
j++;
}
}
return 1;
}
void XGIRegInit(struct vb_device_info *XGI_Pr, unsigned long BaseAddr)
{
XGI_Pr->P3c4 = BaseAddr + 0x14;
XGI_Pr->P3d4 = BaseAddr + 0x24;
XGI_Pr->P3c0 = BaseAddr + 0x10;
XGI_Pr->P3ce = BaseAddr + 0x1e;
XGI_Pr->P3c2 = BaseAddr + 0x12;
XGI_Pr->P3cc = BaseAddr + 0x1c;
XGI_Pr->P3ca = BaseAddr + 0x1a;
XGI_Pr->P3c6 = BaseAddr + 0x16;
XGI_Pr->P3c7 = BaseAddr + 0x17;
XGI_Pr->P3c8 = BaseAddr + 0x18;
XGI_Pr->P3c9 = BaseAddr + 0x19;
XGI_Pr->P3da = BaseAddr + 0x2A;
XGI_Pr->Part0Port = BaseAddr + XGI_CRT2_PORT_00;
/* Digital video interface registers (LCD) */
XGI_Pr->Part1Port = BaseAddr + SIS_CRT2_PORT_04;
/* 301 TV Encoder registers */
XGI_Pr->Part2Port = BaseAddr + SIS_CRT2_PORT_10;
/* 301 Macrovision registers */
XGI_Pr->Part3Port = BaseAddr + SIS_CRT2_PORT_12;
/* 301 VGA2 (and LCD) registers */
XGI_Pr->Part4Port = BaseAddr + SIS_CRT2_PORT_14;
/* 301 palette address port registers */
XGI_Pr->Part5Port = BaseAddr + SIS_CRT2_PORT_14 + 2;
}
/* ------------------ Internal helper routines ----------------- */
static int XGIfb_GetXG21DefaultLVDSModeIdx(struct xgifb_video_info *xgifb_info)
{
int i = 0;
while ((XGIbios_mode[i].mode_no != 0) &&
(XGIbios_mode[i].xres <= xgifb_info->lvds_data.LVDSHDE)) {
if ((XGIbios_mode[i].xres == xgifb_info->lvds_data.LVDSHDE) &&
(XGIbios_mode[i].yres == xgifb_info->lvds_data.LVDSVDE) &&
(XGIbios_mode[i].bpp == 8)) {
return i;
}
i++;
}
return -1;
}
static void XGIfb_search_mode(struct xgifb_video_info *xgifb_info,
const char *name)
{
unsigned int xres;
unsigned int yres;
unsigned int bpp;
int i;
if (sscanf(name, "%ux%ux%u", &xres, &yres, &bpp) != 3)
goto invalid_mode;
if (bpp == 24)
bpp = 32; /* That's for people who mix up color and fb depth. */
for (i = 0; XGIbios_mode[i].mode_no != 0; i++)
if (XGIbios_mode[i].xres == xres &&
XGIbios_mode[i].yres == yres &&
XGIbios_mode[i].bpp == bpp) {
xgifb_info->mode_idx = i;
return;
}
invalid_mode:
pr_info("Invalid mode '%s'\n", name);
}
static void XGIfb_search_vesamode(struct xgifb_video_info *xgifb_info,
unsigned int vesamode)
{
int i = 0;
if (vesamode == 0)
goto invalid;
vesamode &= 0x1dff; /* Clean VESA mode number from other flags */
while (XGIbios_mode[i].mode_no != 0) {
if ((XGIbios_mode[i].vesa_mode_no_1 == vesamode) ||
(XGIbios_mode[i].vesa_mode_no_2 == vesamode)) {
xgifb_info->mode_idx = i;
return;
}
i++;
}
invalid:
pr_info("Invalid VESA mode 0x%x'\n", vesamode);
}
static int XGIfb_validate_mode(struct xgifb_video_info *xgifb_info, int myindex)
{
u16 xres, yres;
struct xgi_hw_device_info *hw_info = &xgifb_info->hw_info;
unsigned long required_mem;
if (xgifb_info->chip == XG21) {
if (xgifb_info->display2 == XGIFB_DISP_LCD) {
xres = xgifb_info->lvds_data.LVDSHDE;
yres = xgifb_info->lvds_data.LVDSVDE;
if (XGIbios_mode[myindex].xres > xres)
return -1;
if (XGIbios_mode[myindex].yres > yres)
return -1;
if ((XGIbios_mode[myindex].xres < xres) &&
(XGIbios_mode[myindex].yres < yres)) {
if (XGIbios_mode[myindex].bpp > 8)
return -1;
}
}
goto check_memory;
}
/* FIXME: for now, all is valid on XG27 */
if (xgifb_info->chip == XG27)
goto check_memory;
if (!(XGIbios_mode[myindex].chipset & MD_XGI315))
return -1;
switch (xgifb_info->display2) {
case XGIFB_DISP_LCD:
switch (hw_info->ulCRT2LCDType) {
case LCD_640x480:
xres = 640;
yres = 480;
break;
case LCD_800x600:
xres = 800;
yres = 600;
break;
case LCD_1024x600:
xres = 1024;
yres = 600;
break;
case LCD_1024x768:
xres = 1024;
yres = 768;
break;
case LCD_1152x768:
xres = 1152;
yres = 768;
break;
case LCD_1280x960:
xres = 1280;
yres = 960;
break;
case LCD_1280x768:
xres = 1280;
yres = 768;
break;
case LCD_1280x1024:
xres = 1280;
yres = 1024;
break;
case LCD_1400x1050:
xres = 1400;
yres = 1050;
break;
case LCD_1600x1200:
xres = 1600;
yres = 1200;
break;
default:
xres = 0;
yres = 0;
break;
}
if (XGIbios_mode[myindex].xres > xres)
return -1;
if (XGIbios_mode[myindex].yres > yres)
return -1;
if ((hw_info->ulExternalChip == 0x01) || /* LVDS */
(hw_info->ulExternalChip == 0x05)) { /* LVDS+Chrontel */
switch (XGIbios_mode[myindex].xres) {
case 512:
if (XGIbios_mode[myindex].yres != 512)
return -1;
if (hw_info->ulCRT2LCDType == LCD_1024x600)
return -1;
break;
case 640:
if ((XGIbios_mode[myindex].yres != 400) &&
(XGIbios_mode[myindex].yres != 480))
return -1;
break;
case 800:
if (XGIbios_mode[myindex].yres != 600)
return -1;
break;
case 1024:
if ((XGIbios_mode[myindex].yres != 600) &&
(XGIbios_mode[myindex].yres != 768))
return -1;
if ((XGIbios_mode[myindex].yres == 600) &&
(hw_info->ulCRT2LCDType != LCD_1024x600))
return -1;
break;
case 1152:
if ((XGIbios_mode[myindex].yres) != 768)
return -1;
if (hw_info->ulCRT2LCDType != LCD_1152x768)
return -1;
break;
case 1280:
if ((XGIbios_mode[myindex].yres != 768) &&
(XGIbios_mode[myindex].yres != 1024))
return -1;
if ((XGIbios_mode[myindex].yres == 768) &&
(hw_info->ulCRT2LCDType != LCD_1280x768))
return -1;
break;
case 1400:
if (XGIbios_mode[myindex].yres != 1050)
return -1;
break;
case 1600:
if (XGIbios_mode[myindex].yres != 1200)
return -1;
break;
default:
return -1;
}
} else {
switch (XGIbios_mode[myindex].xres) {
case 512:
if (XGIbios_mode[myindex].yres != 512)
return -1;
break;
case 640:
if ((XGIbios_mode[myindex].yres != 400) &&
(XGIbios_mode[myindex].yres != 480))
return -1;
break;
case 800:
if (XGIbios_mode[myindex].yres != 600)
return -1;
break;
case 1024:
if (XGIbios_mode[myindex].yres != 768)
return -1;
break;
case 1280:
if ((XGIbios_mode[myindex].yres != 960) &&
(XGIbios_mode[myindex].yres != 1024))
return -1;
if (XGIbios_mode[myindex].yres == 960) {
if (hw_info->ulCRT2LCDType ==
LCD_1400x1050)
return -1;
}
break;
case 1400:
if (XGIbios_mode[myindex].yres != 1050)
return -1;
break;
case 1600:
if (XGIbios_mode[myindex].yres != 1200)
return -1;
break;
default:
return -1;
}
}
break;
case XGIFB_DISP_TV:
switch (XGIbios_mode[myindex].xres) {
case 512:
case 640:
case 800:
break;
case 720:
if (xgifb_info->TV_type == TVMODE_NTSC) {
if (XGIbios_mode[myindex].yres != 480)
return -1;
} else if (xgifb_info->TV_type == TVMODE_PAL) {
if (XGIbios_mode[myindex].yres != 576)
return -1;
}
/* LVDS/CHRONTEL does not support 720 */
if (xgifb_info->hasVB == HASVB_LVDS_CHRONTEL ||
xgifb_info->hasVB == HASVB_CHRONTEL) {
return -1;
}
break;
case 1024:
if (xgifb_info->TV_type == TVMODE_NTSC) {
if (XGIbios_mode[myindex].bpp == 32)
return -1;
}
break;
default:
return -1;
}
break;
case XGIFB_DISP_CRT:
if (XGIbios_mode[myindex].xres > 1280)
return -1;
break;
case XGIFB_DISP_NONE:
break;
}
check_memory:
required_mem = XGIbios_mode[myindex].xres * XGIbios_mode[myindex].yres *
XGIbios_mode[myindex].bpp / 8;
if (required_mem > xgifb_info->video_size)
return -1;
return myindex;
}
static void XGIfb_search_crt2type(const char *name)
{
int i = 0;
if (!name)
return;
while (XGI_crt2type[i].type_no != -1) {
if (!strcmp(name, XGI_crt2type[i].name)) {
XGIfb_crt2type = XGI_crt2type[i].type_no;
XGIfb_tvplug = XGI_crt2type[i].tvplug_no;
break;
}
i++;
}
if (XGIfb_crt2type < 0)
pr_info("Invalid CRT2 type: %s\n", name);
}
static u8 XGIfb_search_refresh_rate(struct xgifb_video_info *xgifb_info,
unsigned int rate)
{
u16 xres, yres;
int i = 0;
xres = XGIbios_mode[xgifb_info->mode_idx].xres;
yres = XGIbios_mode[xgifb_info->mode_idx].yres;
xgifb_info->rate_idx = 0;
while (XGIfb_vrate[i].idx != 0 && XGIfb_vrate[i].xres <= xres) {
/* Skip values with xres or yres less than specified */
if ((XGIfb_vrate[i].yres != yres) ||
(XGIfb_vrate[i].xres != xres)) {
i++;
continue;
}
if (XGIfb_vrate[i].refresh == rate) {
xgifb_info->rate_idx = XGIfb_vrate[i].idx;
break;
} else if (XGIfb_vrate[i].refresh > rate) {
if (XGIfb_vrate[i].refresh - rate <= 3) {
pr_debug("Adjusting rate from %d up to %d\n",
rate, XGIfb_vrate[i].refresh);
xgifb_info->rate_idx = XGIfb_vrate[i].idx;
xgifb_info->refresh_rate =
XGIfb_vrate[i].refresh;
} else if ((XGIfb_vrate[i].idx != 1) &&
(rate - XGIfb_vrate[i - 1].refresh <= 2)) {
pr_debug("Adjusting rate from %d down to %d\n",
rate, XGIfb_vrate[i - 1].refresh);
xgifb_info->rate_idx = XGIfb_vrate[i - 1].idx;
xgifb_info->refresh_rate =
XGIfb_vrate[i - 1].refresh;
}
break;
} else if (rate - XGIfb_vrate[i].refresh <= 2) {
pr_debug("Adjusting rate from %d down to %d\n",
rate, XGIfb_vrate[i].refresh);
xgifb_info->rate_idx = XGIfb_vrate[i].idx;
break;
}
i++;
}
if (xgifb_info->rate_idx > 0)
return xgifb_info->rate_idx;
pr_info("Unsupported rate %d for %dx%d\n",
rate, xres, yres);
return 0;
}
static void XGIfb_search_tvstd(const char *name)
{
int i = 0;
if (!name)
return;
while (XGI_tvtype[i].type_no != -1) {
if (!strcmp(name, XGI_tvtype[i].name)) {
XGIfb_tvmode = XGI_tvtype[i].type_no;
break;
}
i++;
}
}
/* ----------- FBDev related routines for all series ----------- */
static void XGIfb_bpp_to_var(struct xgifb_video_info *xgifb_info,
struct fb_var_screeninfo *var)
{
switch (var->bits_per_pixel) {
case 8:
var->red.offset = 0;
var->green.offset = 0;
var->blue.offset = 0;
var->red.length = 6;
var->green.length = 6;
var->blue.length = 6;
xgifb_info->video_cmap_len = 256;
break;
case 16:
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
xgifb_info->video_cmap_len = 16;
break;
case 32:
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
xgifb_info->video_cmap_len = 16;
break;
}
}
/* --------------------- SetMode routines ------------------------- */
static void XGIfb_pre_setmode(struct xgifb_video_info *xgifb_info)
{
struct vb_device_info *vb = &xgifb_info->dev_info;
u8 cr30 = 0, cr31 = 0;
cr31 = xgifb_reg_get(vb->P3d4, 0x31);
cr31 &= ~0x60;
switch (xgifb_info->display2) {
case XGIFB_DISP_CRT:
cr30 = SIS_VB_OUTPUT_CRT2 | SIS_SIMULTANEOUS_VIEW_ENABLE;
cr31 |= SIS_DRIVER_MODE;
break;
case XGIFB_DISP_LCD:
cr30 = SIS_VB_OUTPUT_LCD | SIS_SIMULTANEOUS_VIEW_ENABLE;
cr31 |= SIS_DRIVER_MODE;
break;
case XGIFB_DISP_TV:
if (xgifb_info->TV_type == TVMODE_HIVISION)
cr30 = SIS_VB_OUTPUT_HIVISION
| SIS_SIMULTANEOUS_VIEW_ENABLE;
else if (xgifb_info->TV_plug == TVPLUG_SVIDEO)
cr30 = SIS_VB_OUTPUT_SVIDEO
| SIS_SIMULTANEOUS_VIEW_ENABLE;
else if (xgifb_info->TV_plug == TVPLUG_COMPOSITE)
cr30 = SIS_VB_OUTPUT_COMPOSITE
| SIS_SIMULTANEOUS_VIEW_ENABLE;
else if (xgifb_info->TV_plug == TVPLUG_SCART)
cr30 = SIS_VB_OUTPUT_SCART
| SIS_SIMULTANEOUS_VIEW_ENABLE;
cr31 |= SIS_DRIVER_MODE;
if (XGIfb_tvmode == 1 || xgifb_info->TV_type == TVMODE_PAL)
cr31 |= 0x01;
else
cr31 &= ~0x01;
break;
default: /* disable CRT2 */
cr30 = 0x00;
cr31 |= (SIS_DRIVER_MODE | SIS_VB_OUTPUT_DISABLE);
}
xgifb_reg_set(vb->P3d4, IND_XGI_SCRATCH_REG_CR30, cr30);
xgifb_reg_set(vb->P3d4, IND_XGI_SCRATCH_REG_CR31, cr31);
xgifb_reg_set(vb->P3d4, IND_XGI_SCRATCH_REG_CR33,
(xgifb_info->rate_idx & 0x0F));
}
static void XGIfb_post_setmode(struct xgifb_video_info *xgifb_info)
{
struct vb_device_info *vb = &xgifb_info->dev_info;
u8 reg;
unsigned char doit = 1;
if (xgifb_info->video_bpp == 8) {
/*
* We can't switch off CRT1 on LVDS/Chrontel
* in 8bpp Modes
*/
if ((xgifb_info->hasVB == HASVB_LVDS) ||
(xgifb_info->hasVB == HASVB_LVDS_CHRONTEL)) {
doit = 0;
}
/*
* We can't switch off CRT1 on 301B-DH
* in 8bpp Modes if using LCD
*/
if (xgifb_info->display2 == XGIFB_DISP_LCD)
doit = 0;
}
/* We can't switch off CRT1 if bridge is in slave mode */
if (xgifb_info->hasVB != HASVB_NONE) {
reg = xgifb_reg_get(vb->Part1Port, 0x00);
if ((reg & 0x50) == 0x10)
doit = 0;
} else {
XGIfb_crt1off = 0;
}
reg = xgifb_reg_get(vb->P3d4, 0x17);
if ((XGIfb_crt1off) && (doit))
reg &= ~0x80;
else
reg |= 0x80;
xgifb_reg_set(vb->P3d4, 0x17, reg);
xgifb_reg_and(vb->P3c4, IND_SIS_RAMDAC_CONTROL, ~0x04);
if (xgifb_info->display2 == XGIFB_DISP_TV &&
xgifb_info->hasVB == HASVB_301) {
reg = xgifb_reg_get(vb->Part4Port, 0x01);
if (reg < 0xB0) { /* Set filter for XGI301 */
int filter_tb;
switch (xgifb_info->video_width) {
case 320:
filter_tb = (xgifb_info->TV_type ==
TVMODE_NTSC) ? 4 : 12;
break;
case 640:
filter_tb = (xgifb_info->TV_type ==
TVMODE_NTSC) ? 5 : 13;
break;
case 720:
filter_tb = (xgifb_info->TV_type ==
TVMODE_NTSC) ? 6 : 14;
break;
case 800:
filter_tb = (xgifb_info->TV_type ==
TVMODE_NTSC) ? 7 : 15;
break;
default:
filter_tb = 0;
filter = -1;
break;
}
xgifb_reg_or(vb->Part1Port, SIS_CRT2_WENABLE_315, 0x01);
if (xgifb_info->TV_type == TVMODE_NTSC) {
xgifb_reg_and(vb->Part2Port, 0x3a, 0x1f);
if (xgifb_info->TV_plug == TVPLUG_SVIDEO) {
xgifb_reg_and(vb->Part2Port, 0x30, 0xdf);
} else if (xgifb_info->TV_plug
== TVPLUG_COMPOSITE) {
xgifb_reg_or(vb->Part2Port, 0x30, 0x20);
switch (xgifb_info->video_width) {
case 640:
xgifb_reg_set(vb->Part2Port,
0x35,
0xEB);
xgifb_reg_set(vb->Part2Port,
0x36,
0x04);
xgifb_reg_set(vb->Part2Port,
0x37,
0x25);
xgifb_reg_set(vb->Part2Port,
0x38,
0x18);
break;
case 720:
xgifb_reg_set(vb->Part2Port,
0x35,
0xEE);
xgifb_reg_set(vb->Part2Port,
0x36,
0x0C);
xgifb_reg_set(vb->Part2Port,
0x37,
0x22);
xgifb_reg_set(vb->Part2Port,
0x38,
0x08);
break;
case 800:
xgifb_reg_set(vb->Part2Port,
0x35,
0xEB);
xgifb_reg_set(vb->Part2Port,
0x36,
0x15);
xgifb_reg_set(vb->Part2Port,
0x37,
0x25);
xgifb_reg_set(vb->Part2Port,
0x38,
0xF6);
break;
}
}
} else if (xgifb_info->TV_type == TVMODE_PAL) {
xgifb_reg_and(vb->Part2Port, 0x3A, 0x1F);
if (xgifb_info->TV_plug == TVPLUG_SVIDEO) {
xgifb_reg_and(vb->Part2Port, 0x30, 0xDF);
} else if (xgifb_info->TV_plug
== TVPLUG_COMPOSITE) {
xgifb_reg_or(vb->Part2Port, 0x30, 0x20);
switch (xgifb_info->video_width) {
case 640:
xgifb_reg_set(vb->Part2Port,
0x35,
0xF1);
xgifb_reg_set(vb->Part2Port,
0x36,
0xF7);
xgifb_reg_set(vb->Part2Port,
0x37,
0x1F);
xgifb_reg_set(vb->Part2Port,
0x38,
0x32);
break;
case 720:
xgifb_reg_set(vb->Part2Port,
0x35,
0xF3);
xgifb_reg_set(vb->Part2Port,
0x36,
0x00);
xgifb_reg_set(vb->Part2Port,
0x37,
0x1D);
xgifb_reg_set(vb->Part2Port,
0x38,
0x20);
break;
case 800:
xgifb_reg_set(vb->Part2Port,
0x35,
0xFC);
xgifb_reg_set(vb->Part2Port,
0x36,
0xFB);
xgifb_reg_set(vb->Part2Port,
0x37,
0x14);
xgifb_reg_set(vb->Part2Port,
0x38,
0x2A);
break;
}
}
}
if ((filter >= 0) && (filter <= 7)) {
const u8 *f = XGI_TV_filter[filter_tb].filter[filter];
pr_debug("FilterTable[%d]-%d: %*ph\n",
filter_tb, filter, 4, f);
xgifb_reg_set(vb->Part2Port, 0x35, f[0]);
xgifb_reg_set(vb->Part2Port, 0x36, f[1]);
xgifb_reg_set(vb->Part2Port, 0x37, f[2]);
xgifb_reg_set(vb->Part2Port, 0x38, f[3]);
}
}
}
}
static int XGIfb_do_set_var(struct fb_var_screeninfo *var, int isactive,
struct fb_info *info)
{
struct xgifb_video_info *xgifb_info = info->par;
struct vb_device_info *vb = &xgifb_info->dev_info;
struct xgi_hw_device_info *hw_info = &xgifb_info->hw_info;
unsigned int htotal = var->left_margin + var->xres + var->right_margin
+ var->hsync_len;
unsigned int vtotal = var->upper_margin + var->yres + var->lower_margin
+ var->vsync_len;
#if defined(__BIG_ENDIAN)
u8 cr_data;
#endif
unsigned int drate = 0, hrate = 0;
int found_mode = 0;
int old_mode;
info->var.xres_virtual = var->xres_virtual;
info->var.yres_virtual = var->yres_virtual;
info->var.bits_per_pixel = var->bits_per_pixel;
if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_NONINTERLACED)
vtotal <<= 1;
else if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
vtotal <<= 2;
if (!htotal || !vtotal) {
pr_debug("Invalid 'var' information\n");
return -EINVAL;
}
pr_debug("var->pixclock=%d, htotal=%d, vtotal=%d\n",
var->pixclock, htotal, vtotal);
if (var->pixclock) {
drate = 1000000000 / var->pixclock;
hrate = (drate * 1000) / htotal;
xgifb_info->refresh_rate = (unsigned int)(hrate * 2
/ vtotal);
} else {
xgifb_info->refresh_rate = 60;
}
pr_debug("Change mode to %dx%dx%d-%dHz\n",
var->xres, var->yres, var->bits_per_pixel,
xgifb_info->refresh_rate);
old_mode = xgifb_info->mode_idx;
xgifb_info->mode_idx = 0;
while ((XGIbios_mode[xgifb_info->mode_idx].mode_no != 0) &&
(XGIbios_mode[xgifb_info->mode_idx].xres <= var->xres)) {
if ((XGIbios_mode[xgifb_info->mode_idx].xres == var->xres) &&
(XGIbios_mode[xgifb_info->mode_idx].yres == var->yres) &&
(XGIbios_mode[xgifb_info->mode_idx].bpp
== var->bits_per_pixel)) {
found_mode = 1;
break;
}
xgifb_info->mode_idx++;
}
if (found_mode)
xgifb_info->mode_idx = XGIfb_validate_mode(xgifb_info,
xgifb_info->mode_idx);
else
xgifb_info->mode_idx = -1;
if (xgifb_info->mode_idx < 0) {
pr_err("Mode %dx%dx%d not supported\n",
var->xres, var->yres, var->bits_per_pixel);
xgifb_info->mode_idx = old_mode;
return -EINVAL;
}
if (XGIfb_search_refresh_rate(xgifb_info,
xgifb_info->refresh_rate) == 0) {
xgifb_info->rate_idx = 1;
xgifb_info->refresh_rate = 60;
}
if (isactive) {
XGIfb_pre_setmode(xgifb_info);
if (XGISetModeNew(xgifb_info, hw_info,
XGIbios_mode[xgifb_info->mode_idx].mode_no)
== 0) {
pr_err("Setting mode[0x%x] failed\n",
XGIbios_mode[xgifb_info->mode_idx].mode_no);
return -EINVAL;
}
info->fix.line_length = (info->var.xres_virtual
* info->var.bits_per_pixel) >> 6;
xgifb_reg_set(vb->P3c4, IND_SIS_PASSWORD, SIS_PASSWORD);
xgifb_reg_set(vb->P3d4, 0x13, (info->fix.line_length & 0x00ff));
xgifb_reg_set(vb->P3c4, 0x0E,
(info->fix.line_length & 0xff00) >> 8);
XGIfb_post_setmode(xgifb_info);
pr_debug("Set new mode: %dx%dx%d-%d\n",
XGIbios_mode[xgifb_info->mode_idx].xres,
XGIbios_mode[xgifb_info->mode_idx].yres,
XGIbios_mode[xgifb_info->mode_idx].bpp,
xgifb_info->refresh_rate);
xgifb_info->video_bpp = XGIbios_mode[xgifb_info->mode_idx].bpp;
xgifb_info->video_vwidth = info->var.xres_virtual;
xgifb_info->video_width =
XGIbios_mode[xgifb_info->mode_idx].xres;
xgifb_info->video_vheight = info->var.yres_virtual;
xgifb_info->video_height =
XGIbios_mode[xgifb_info->mode_idx].yres;
xgifb_info->org_x = 0;
xgifb_info->org_y = 0;
xgifb_info->video_linelength = info->var.xres_virtual
* (xgifb_info->video_bpp >> 3);
switch (xgifb_info->video_bpp) {
case 8:
xgifb_info->DstColor = 0x0000;
xgifb_info->XGI310_AccelDepth = 0x00000000;
xgifb_info->video_cmap_len = 256;
#if defined(__BIG_ENDIAN)
cr_data = xgifb_reg_get(vb->P3d4, 0x4D);
xgifb_reg_set(vb->P3d4, 0x4D, (cr_data & 0xE0));
#endif
break;
case 16:
xgifb_info->DstColor = 0x8000;
xgifb_info->XGI310_AccelDepth = 0x00010000;
#if defined(__BIG_ENDIAN)
cr_data = xgifb_reg_get(vb->P3d4, 0x4D);
xgifb_reg_set(vb->P3d4, 0x4D, ((cr_data & 0xE0) | 0x0B));
#endif
xgifb_info->video_cmap_len = 16;
break;
case 32:
xgifb_info->DstColor = 0xC000;
xgifb_info->XGI310_AccelDepth = 0x00020000;
xgifb_info->video_cmap_len = 16;
#if defined(__BIG_ENDIAN)
cr_data = xgifb_reg_get(vb->P3d4, 0x4D);
xgifb_reg_set(vb->P3d4, 0x4D, ((cr_data & 0xE0) | 0x15));
#endif
break;
default:
xgifb_info->video_cmap_len = 16;
pr_err("Unsupported depth %d\n",
xgifb_info->video_bpp);
break;
}
}
XGIfb_bpp_to_var(xgifb_info, var); /* update ARGB info */
dumpVGAReg(xgifb_info);
return 0;
}
static int XGIfb_pan_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct xgifb_video_info *xgifb_info = info->par;
struct vb_device_info *vb = &xgifb_info->dev_info;
unsigned int base;
base = var->yoffset * info->var.xres_virtual + var->xoffset;
/* calculate base bpp dep. */
switch (info->var.bits_per_pixel) {
case 16:
base >>= 1;
break;
case 32:
break;
case 8:
default:
base >>= 2;
break;
}
xgifb_reg_set(vb->P3c4, IND_SIS_PASSWORD, SIS_PASSWORD);
xgifb_reg_set(vb->P3d4, 0x0D, base & 0xFF);
xgifb_reg_set(vb->P3d4, 0x0C, (base >> 8) & 0xFF);
xgifb_reg_set(vb->P3c4, 0x0D, (base >> 16) & 0xFF);
xgifb_reg_set(vb->P3c4, 0x37, (base >> 24) & 0x03);
xgifb_reg_and_or(vb->P3c4, 0x37, 0xDF, (base >> 21) & 0x04);
if (xgifb_info->display2 != XGIFB_DISP_NONE) {
xgifb_reg_or(vb->Part1Port, SIS_CRT2_WENABLE_315, 0x01);
xgifb_reg_set(vb->Part1Port, 0x06, (base & 0xFF));
xgifb_reg_set(vb->Part1Port, 0x05, ((base >> 8) & 0xFF));
xgifb_reg_set(vb->Part1Port, 0x04, ((base >> 16) & 0xFF));
xgifb_reg_and_or(vb->Part1Port, 0x02, 0x7F,
((base >> 24) & 0x01) << 7);
}
return 0;
}
static int XGIfb_open(struct fb_info *info, int user)
{
return 0;
}
static int XGIfb_release(struct fb_info *info, int user)
{
return 0;
}
/* similar to sisfb_get_cmap_len */
static int XGIfb_get_cmap_len(const struct fb_var_screeninfo *var)
{
return (var->bits_per_pixel == 8) ? 256 : 16;
}
static int XGIfb_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
struct xgifb_video_info *xgifb_info = info->par;
struct vb_device_info *vb = &xgifb_info->dev_info;
if (regno >= XGIfb_get_cmap_len(&info->var))
return 1;
switch (info->var.bits_per_pixel) {
case 8:
outb(regno, vb->P3c8);
outb((red >> 10), vb->P3c9);
outb((green >> 10), vb->P3c9);
outb((blue >> 10), vb->P3c9);
if (xgifb_info->display2 != XGIFB_DISP_NONE) {
outb(regno, vb->Part5Port);
outb((red >> 8), (vb->Part5Port + 1));
outb((green >> 8), (vb->Part5Port + 1));
outb((blue >> 8), (vb->Part5Port + 1));
}
break;
case 16:
((u32 *)(info->pseudo_palette))[regno] = ((red & 0xf800))
| ((green & 0xfc00) >> 5) | ((blue & 0xf800)
>> 11);
break;
case 32:
red >>= 8;
green >>= 8;
blue >>= 8;
((u32 *)(info->pseudo_palette))[regno] = (red << 16) | (green
<< 8) | (blue);
break;
}
return 0;
}
/* ----------- FBDev related routines for all series ---------- */
static int XGIfb_get_fix(struct fb_fix_screeninfo *fix, int con,
struct fb_info *info)
{
struct xgifb_video_info *xgifb_info = info->par;
memset(fix, 0, sizeof(struct fb_fix_screeninfo));
strncpy(fix->id, "XGI", sizeof(fix->id) - 1);
/* if register_framebuffer has been called, we must lock */
if (atomic_read(&info->count))
mutex_lock(&info->mm_lock);
fix->smem_start = xgifb_info->video_base;
fix->smem_len = xgifb_info->video_size;
/* if register_framebuffer has been called, we can unlock */
if (atomic_read(&info->count))
mutex_unlock(&info->mm_lock);
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
if (xgifb_info->video_bpp == 8)
fix->visual = FB_VISUAL_PSEUDOCOLOR;
else
fix->visual = FB_VISUAL_DIRECTCOLOR;
fix->xpanstep = 0;
if (XGIfb_ypan)
fix->ypanstep = 1;
fix->ywrapstep = 0;
fix->line_length = xgifb_info->video_linelength;
fix->mmio_start = xgifb_info->mmio_base;
fix->mmio_len = xgifb_info->mmio_size;
fix->accel = FB_ACCEL_SIS_XABRE;
return 0;
}
static int XGIfb_set_par(struct fb_info *info)
{
int err;
err = XGIfb_do_set_var(&info->var, 1, info);
if (err)
return err;
XGIfb_get_fix(&info->fix, -1, info);
return 0;
}
static int XGIfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct xgifb_video_info *xgifb_info = info->par;
unsigned int htotal = var->left_margin + var->xres + var->right_margin
+ var->hsync_len;
unsigned int vtotal = 0;
unsigned int drate = 0, hrate = 0;
int found_mode = 0;
int search_idx;
if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_NONINTERLACED) {
vtotal = var->upper_margin + var->yres + var->lower_margin
+ var->vsync_len;
vtotal <<= 1;
} else if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
vtotal = var->upper_margin + var->yres + var->lower_margin
+ var->vsync_len;
vtotal <<= 2;
} else if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
vtotal = var->upper_margin + (var->yres / 2)
+ var->lower_margin + var->vsync_len;
} else
vtotal = var->upper_margin + var->yres + var->lower_margin
+ var->vsync_len;
if (!(htotal) || !(vtotal)) {
pr_debug("No valid timing data\n");
return -EINVAL;
}
if (var->pixclock && htotal && vtotal) {
drate = 1000000000 / var->pixclock;
hrate = (drate * 1000) / htotal;
xgifb_info->refresh_rate =
(unsigned int)(hrate * 2 / vtotal);
pr_debug(
"%s: pixclock = %d ,htotal=%d, vtotal=%d\n"
"%s: drate=%d, hrate=%d, refresh_rate=%d\n",
__func__, var->pixclock, htotal, vtotal,
__func__, drate, hrate, xgifb_info->refresh_rate);
} else {
xgifb_info->refresh_rate = 60;
}
search_idx = 0;
while ((XGIbios_mode[search_idx].mode_no != 0) &&
(XGIbios_mode[search_idx].xres <= var->xres)) {
if ((XGIbios_mode[search_idx].xres == var->xres) &&
(XGIbios_mode[search_idx].yres == var->yres) &&
(XGIbios_mode[search_idx].bpp == var->bits_per_pixel)) {
if (XGIfb_validate_mode(xgifb_info, search_idx) > 0) {
found_mode = 1;
break;
}
}
search_idx++;
}
if (!found_mode) {
pr_err("%dx%dx%d is no valid mode\n",
var->xres, var->yres, var->bits_per_pixel);
search_idx = 0;
while (XGIbios_mode[search_idx].mode_no != 0) {
if ((var->xres <= XGIbios_mode[search_idx].xres) &&
(var->yres <= XGIbios_mode[search_idx].yres) &&
(var->bits_per_pixel ==
XGIbios_mode[search_idx].bpp)) {
if (XGIfb_validate_mode(xgifb_info,
search_idx) > 0) {
found_mode = 1;
break;
}
}
search_idx++;
}
if (found_mode) {
var->xres = XGIbios_mode[search_idx].xres;
var->yres = XGIbios_mode[search_idx].yres;
pr_debug("Adapted to mode %dx%dx%d\n",
var->xres, var->yres, var->bits_per_pixel);
} else {
pr_err("Failed to find similar mode to %dx%dx%d\n",
var->xres, var->yres, var->bits_per_pixel);
return -EINVAL;
}
}
/* Adapt RGB settings */
XGIfb_bpp_to_var(xgifb_info, var);
if (!XGIfb_ypan) {
if (var->xres != var->xres_virtual)
var->xres_virtual = var->xres;
if (var->yres != var->yres_virtual)
var->yres_virtual = var->yres;
}
/* Truncate offsets to maximum if too high */
if (var->xoffset > var->xres_virtual - var->xres)
var->xoffset = var->xres_virtual - var->xres - 1;
if (var->yoffset > var->yres_virtual - var->yres)
var->yoffset = var->yres_virtual - var->yres - 1;
/* Set everything else to 0 */
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.offset = 0;
var->transp.length = 0;
var->transp.msb_right = 0;
return 0;
}
static int XGIfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int err;
if (var->xoffset > (info->var.xres_virtual - info->var.xres))
return -EINVAL;
if (var->yoffset > (info->var.yres_virtual - info->var.yres))
return -EINVAL;
if (var->vmode & FB_VMODE_YWRAP) {
if (var->yoffset >= info->var.yres_virtual || var->xoffset)
return -EINVAL;
} else if (var->xoffset + info->var.xres > info->var.xres_virtual ||
var->yoffset + info->var.yres > info->var.yres_virtual) {
return -EINVAL;
}
err = XGIfb_pan_var(var, info);
if (err < 0)
return err;
info->var.xoffset = var->xoffset;
info->var.yoffset = var->yoffset;
if (var->vmode & FB_VMODE_YWRAP)
info->var.vmode |= FB_VMODE_YWRAP;
else
info->var.vmode &= ~FB_VMODE_YWRAP;
return 0;
}
static int XGIfb_blank(int blank, struct fb_info *info)
{
struct xgifb_video_info *xgifb_info = info->par;
struct vb_device_info *vb = &xgifb_info->dev_info;
u8 reg;
reg = xgifb_reg_get(vb->P3d4, 0x17);
if (blank > 0)
reg &= 0x7f;
else
reg |= 0x80;
xgifb_reg_set(vb->P3d4, 0x17, reg);
xgifb_reg_set(vb->P3c4, 0x00, 0x01); /* Synchronous Reset */
xgifb_reg_set(vb->P3c4, 0x00, 0x03); /* End Reset */
return 0;
}
static struct fb_ops XGIfb_ops = {
.owner = THIS_MODULE,
.fb_open = XGIfb_open,
.fb_release = XGIfb_release,
.fb_check_var = XGIfb_check_var,
.fb_set_par = XGIfb_set_par,
.fb_setcolreg = XGIfb_setcolreg,
.fb_pan_display = XGIfb_pan_display,
.fb_blank = XGIfb_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
/* ---------------- Chip generation dependent routines ---------------- */
/* for XGI 315/550/650/740/330 */
static int XGIfb_get_dram_size(struct xgifb_video_info *xgifb_info)
{
struct vb_device_info *vb = &xgifb_info->dev_info;
u8 ChannelNum, tmp;
u8 reg = 0;
/* xorg driver sets 32MB * 1 channel */
if (xgifb_info->chip == XG27)
xgifb_reg_set(vb->P3c4, IND_SIS_DRAM_SIZE, 0x51);
reg = xgifb_reg_get(vb->P3c4, IND_SIS_DRAM_SIZE);
if (!reg)
return -1;
switch ((reg & XGI_DRAM_SIZE_MASK) >> 4) {
case XGI_DRAM_SIZE_1MB:
xgifb_info->video_size = 0x100000;
break;
case XGI_DRAM_SIZE_2MB:
xgifb_info->video_size = 0x200000;
break;
case XGI_DRAM_SIZE_4MB:
xgifb_info->video_size = 0x400000;
break;
case XGI_DRAM_SIZE_8MB:
xgifb_info->video_size = 0x800000;
break;
case XGI_DRAM_SIZE_16MB:
xgifb_info->video_size = 0x1000000;
break;
case XGI_DRAM_SIZE_32MB:
xgifb_info->video_size = 0x2000000;
break;
case XGI_DRAM_SIZE_64MB:
xgifb_info->video_size = 0x4000000;
break;
case XGI_DRAM_SIZE_128MB:
xgifb_info->video_size = 0x8000000;
break;
case XGI_DRAM_SIZE_256MB:
xgifb_info->video_size = 0x10000000;
break;
default:
return -1;
}
tmp = (reg & 0x0c) >> 2;
switch (xgifb_info->chip) {
case XG20:
case XG21:
case XG27:
ChannelNum = 1;
break;
case XG42:
if (reg & 0x04)
ChannelNum = 2;
else
ChannelNum = 1;
break;
case XG40:
default:
if (tmp == 2)
ChannelNum = 2;
else if (tmp == 3)
ChannelNum = 3;
else
ChannelNum = 1;
break;
}
xgifb_info->video_size = xgifb_info->video_size * ChannelNum;
pr_info("SR14=%x DramSzie %x ChannelNum %x\n",
reg, xgifb_info->video_size, ChannelNum);
return 0;
}
static void XGIfb_detect_VB(struct xgifb_video_info *xgifb_info)
{
struct vb_device_info *vb = &xgifb_info->dev_info;
u8 cr32, temp = 0;
xgifb_info->TV_plug = 0;
xgifb_info->TV_type = 0;
cr32 = xgifb_reg_get(vb->P3d4, IND_XGI_SCRATCH_REG_CR32);
if ((cr32 & SIS_CRT1) && !XGIfb_crt1off) {
XGIfb_crt1off = 0;
} else {
if (cr32 & 0x5F)
XGIfb_crt1off = 1;
else
XGIfb_crt1off = 0;
}
if (!xgifb_info->display2_force) {
if (cr32 & SIS_VB_TV)
xgifb_info->display2 = XGIFB_DISP_TV;
else if (cr32 & SIS_VB_LCD)
xgifb_info->display2 = XGIFB_DISP_LCD;
else if (cr32 & SIS_VB_CRT2)
xgifb_info->display2 = XGIFB_DISP_CRT;
else
xgifb_info->display2 = XGIFB_DISP_NONE;
}
if (XGIfb_tvplug != -1) {
/* Override with option */
xgifb_info->TV_plug = XGIfb_tvplug;
} else if (cr32 & SIS_VB_HIVISION) {
xgifb_info->TV_type = TVMODE_HIVISION;
xgifb_info->TV_plug = TVPLUG_SVIDEO;
} else if (cr32 & SIS_VB_SVIDEO) {
xgifb_info->TV_plug = TVPLUG_SVIDEO;
} else if (cr32 & SIS_VB_COMPOSITE) {
xgifb_info->TV_plug = TVPLUG_COMPOSITE;
} else if (cr32 & SIS_VB_SCART) {
xgifb_info->TV_plug = TVPLUG_SCART;
}
if (xgifb_info->TV_type == 0) {
temp = xgifb_reg_get(vb->P3d4, 0x38);
if (temp & 0x10)
xgifb_info->TV_type = TVMODE_PAL;
else
xgifb_info->TV_type = TVMODE_NTSC;
}
/* Copy forceCRT1 option to CRT1off if option is given */
if (XGIfb_forcecrt1 != -1) {
if (XGIfb_forcecrt1)
XGIfb_crt1off = 0;
else
XGIfb_crt1off = 1;
}
}
static bool XGIfb_has_VB(struct xgifb_video_info *xgifb_info)
{
u8 vb_chipid;
vb_chipid = xgifb_reg_get(xgifb_info->dev_info.Part4Port, 0x00);
switch (vb_chipid) {
case 0x01:
xgifb_info->hasVB = HASVB_301;
break;
case 0x02:
xgifb_info->hasVB = HASVB_302;
break;
default:
xgifb_info->hasVB = HASVB_NONE;
return false;
}
return true;
}
static void XGIfb_get_VB_type(struct xgifb_video_info *xgifb_info)
{
u8 reg;
if (!XGIfb_has_VB(xgifb_info)) {
reg = xgifb_reg_get(xgifb_info->dev_info.P3d4,
IND_XGI_SCRATCH_REG_CR37);
switch ((reg & SIS_EXTERNAL_CHIP_MASK) >> 1) {
case SIS_EXTERNAL_CHIP_LVDS:
xgifb_info->hasVB = HASVB_LVDS;
break;
case SIS_EXTERNAL_CHIP_LVDS_CHRONTEL:
xgifb_info->hasVB = HASVB_LVDS_CHRONTEL;
break;
default:
break;
}
}
}
static int __init xgifb_optval(char *fullopt, int validx)
{
unsigned long lres;
if (kstrtoul(fullopt + validx, 0, &lres) < 0 || lres > INT_MAX) {
pr_err("Invalid value for option: %s\n", fullopt);
return 0;
}
return lres;
}
static int __init XGIfb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
pr_info("Options: %s\n", options);
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
if (!strncmp(this_opt, "mode:", 5)) {
mode = this_opt + 5;
} else if (!strncmp(this_opt, "vesa:", 5)) {
vesa = xgifb_optval(this_opt, 5);
} else if (!strncmp(this_opt, "vrate:", 6)) {
refresh_rate = xgifb_optval(this_opt, 6);
} else if (!strncmp(this_opt, "rate:", 5)) {
refresh_rate = xgifb_optval(this_opt, 5);
} else if (!strncmp(this_opt, "crt1off", 7)) {
XGIfb_crt1off = 1;
} else if (!strncmp(this_opt, "filter:", 7)) {
filter = xgifb_optval(this_opt, 7);
} else if (!strncmp(this_opt, "forcecrt2type:", 14)) {
XGIfb_search_crt2type(this_opt + 14);
} else if (!strncmp(this_opt, "forcecrt1:", 10)) {
XGIfb_forcecrt1 = xgifb_optval(this_opt, 10);
} else if (!strncmp(this_opt, "tvmode:", 7)) {
XGIfb_search_tvstd(this_opt + 7);
} else if (!strncmp(this_opt, "tvstandard:", 11)) {
XGIfb_search_tvstd(this_opt + 7);
} else if (!strncmp(this_opt, "dstn", 4)) {
enable_dstn = 1;
/* DSTN overrules forcecrt2type */
XGIfb_crt2type = XGIFB_DISP_LCD;
} else if (!strncmp(this_opt, "noypan", 6)) {
XGIfb_ypan = 0;
} else {
mode = this_opt;
}
}
return 0;
}
static int xgifb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
u8 reg, reg1;
u8 CR48, CR38;
int ret;
struct fb_info *fb_info;
struct xgifb_video_info *xgifb_info;
struct vb_device_info *vb;
struct xgi_hw_device_info *hw_info;
unsigned long video_size_max;
fb_info = framebuffer_alloc(sizeof(*xgifb_info), &pdev->dev);
if (!fb_info)
return -ENOMEM;
xgifb_info = fb_info->par;
vb = &xgifb_info->dev_info;
hw_info = &xgifb_info->hw_info;
xgifb_info->fb_info = fb_info;
xgifb_info->chip_id = pdev->device;
pci_read_config_byte(pdev,
PCI_REVISION_ID,
&xgifb_info->revision_id);
hw_info->jChipRevision = xgifb_info->revision_id;
xgifb_info->pcibus = pdev->bus->number;
xgifb_info->pcislot = PCI_SLOT(pdev->devfn);
xgifb_info->pcifunc = PCI_FUNC(pdev->devfn);
xgifb_info->subsysvendor = pdev->subsystem_vendor;
xgifb_info->subsysdevice = pdev->subsystem_device;
video_size_max = pci_resource_len(pdev, 0);
xgifb_info->video_base = pci_resource_start(pdev, 0);
xgifb_info->mmio_base = pci_resource_start(pdev, 1);
xgifb_info->mmio_size = pci_resource_len(pdev, 1);
xgifb_info->vga_base = pci_resource_start(pdev, 2) + 0x30;
dev_info(&pdev->dev, "Relocate IO address: %llx [%08lx]\n",
(u64)pci_resource_start(pdev, 2),
xgifb_info->vga_base);
if (pci_enable_device(pdev)) {
ret = -EIO;
goto error;
}
if (XGIfb_crt2type != -1) {
xgifb_info->display2 = XGIfb_crt2type;
xgifb_info->display2_force = true;
}
XGIRegInit(vb, xgifb_info->vga_base);
xgifb_reg_set(vb->P3c4,
IND_SIS_PASSWORD, SIS_PASSWORD);
reg1 = xgifb_reg_get(vb->P3c4, IND_SIS_PASSWORD);
if (reg1 != 0xa1) { /* I/O error */
dev_err(&pdev->dev, "I/O error\n");
ret = -EIO;
goto error_disable;
}
switch (xgifb_info->chip_id) {
case PCI_DEVICE_ID_XGI_20:
xgifb_reg_or(vb->P3d4,
Index_CR_GPIO_Reg3, GPIOG_EN);
CR48 = xgifb_reg_get(vb->P3d4,
Index_CR_GPIO_Reg1);
if (CR48 & GPIOG_READ)
xgifb_info->chip = XG21;
else
xgifb_info->chip = XG20;
break;
case PCI_DEVICE_ID_XGI_40:
xgifb_info->chip = XG40;
break;
case PCI_DEVICE_ID_XGI_42:
xgifb_info->chip = XG42;
break;
case PCI_DEVICE_ID_XGI_27:
xgifb_info->chip = XG27;
break;
default:
ret = -ENODEV;
goto error_disable;
}
dev_info(&pdev->dev, "chipid = %x\n", xgifb_info->chip);
hw_info->jChipType = xgifb_info->chip;
if (XGIfb_get_dram_size(xgifb_info)) {
xgifb_info->video_size = min_t(unsigned long, video_size_max,
SZ_16M);
} else if (xgifb_info->video_size > video_size_max) {
xgifb_info->video_size = video_size_max;
}
/* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */
xgifb_reg_or(vb->P3c4,
IND_SIS_PCI_ADDRESS_SET,
(SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE));
/* Enable 2D accelerator engine */
xgifb_reg_or(vb->P3c4,
IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D);
hw_info->ulVideoMemorySize = xgifb_info->video_size;
if (!request_mem_region(xgifb_info->video_base,
xgifb_info->video_size,
"XGIfb FB")) {
dev_err(&pdev->dev, "Unable request memory size %x\n",
xgifb_info->video_size);
dev_err(&pdev->dev,
"Fatal error: Unable to reserve frame buffer memory. Is there another framebuffer driver active?\n");
ret = -ENODEV;
goto error_disable;
}
if (!request_mem_region(xgifb_info->mmio_base,
xgifb_info->mmio_size,
"XGIfb MMIO")) {
dev_err(&pdev->dev,
"Fatal error: Unable to reserve MMIO region\n");
ret = -ENODEV;
goto error_0;
}
xgifb_info->video_vbase =
ioremap_wc(xgifb_info->video_base, xgifb_info->video_size);
hw_info->pjVideoMemoryAddress =
ioremap_wc(xgifb_info->video_base, xgifb_info->video_size);
xgifb_info->mmio_vbase = ioremap(xgifb_info->mmio_base,
xgifb_info->mmio_size);
dev_info(&pdev->dev,
"Framebuffer at 0x%llx, mapped to 0x%p, size %dk\n",
(u64)xgifb_info->video_base,
xgifb_info->video_vbase,
xgifb_info->video_size / 1024);
dev_info(&pdev->dev,
"MMIO at 0x%llx, mapped to 0x%p, size %ldk\n",
(u64)xgifb_info->mmio_base, xgifb_info->mmio_vbase,
xgifb_info->mmio_size / 1024);
pci_set_drvdata(pdev, xgifb_info);
if (!XGIInitNew(pdev))
dev_err(&pdev->dev, "XGIInitNew() failed!\n");
xgifb_info->mtrr = -1;
xgifb_info->hasVB = HASVB_NONE;
if ((xgifb_info->chip == XG20) ||
(xgifb_info->chip == XG27)) {
xgifb_info->hasVB = HASVB_NONE;
} else if (xgifb_info->chip == XG21) {
CR38 = xgifb_reg_get(vb->P3d4, 0x38);
if ((CR38 & 0xE0) == 0xC0)
xgifb_info->display2 = XGIFB_DISP_LCD;
else if ((CR38 & 0xE0) == 0x60)
xgifb_info->hasVB = HASVB_CHRONTEL;
else
xgifb_info->hasVB = HASVB_NONE;
} else {
XGIfb_get_VB_type(xgifb_info);
}
hw_info->ujVBChipID = VB_CHIP_UNKNOWN;
hw_info->ulExternalChip = 0;
switch (xgifb_info->hasVB) {
case HASVB_301:
reg = xgifb_reg_get(vb->Part4Port, 0x01);
if (reg >= 0xE0) {
hw_info->ujVBChipID = VB_CHIP_302LV;
dev_info(&pdev->dev,
"XGI302LV bridge detected (revision 0x%02x)\n",
reg);
} else if (reg >= 0xD0) {
hw_info->ujVBChipID = VB_CHIP_301LV;
dev_info(&pdev->dev,
"XGI301LV bridge detected (revision 0x%02x)\n",
reg);
} else {
hw_info->ujVBChipID = VB_CHIP_301;
dev_info(&pdev->dev, "XGI301 bridge detected\n");
}
break;
case HASVB_302:
reg = xgifb_reg_get(vb->Part4Port, 0x01);
if (reg >= 0xE0) {
hw_info->ujVBChipID = VB_CHIP_302LV;
dev_info(&pdev->dev,
"XGI302LV bridge detected (revision 0x%02x)\n",
reg);
} else if (reg >= 0xD0) {
hw_info->ujVBChipID = VB_CHIP_301LV;
dev_info(&pdev->dev,
"XGI302LV bridge detected (revision 0x%02x)\n",
reg);
} else if (reg >= 0xB0) {
reg1 = xgifb_reg_get(vb->Part4Port,
0x23);
hw_info->ujVBChipID = VB_CHIP_302B;
} else {
hw_info->ujVBChipID = VB_CHIP_302;
dev_info(&pdev->dev, "XGI302 bridge detected\n");
}
break;
case HASVB_LVDS:
hw_info->ulExternalChip = 0x1;
dev_info(&pdev->dev, "LVDS transmitter detected\n");
break;
case HASVB_TRUMPION:
hw_info->ulExternalChip = 0x2;
dev_info(&pdev->dev, "Trumpion Zurac LVDS scaler detected\n");
break;
case HASVB_CHRONTEL:
hw_info->ulExternalChip = 0x4;
dev_info(&pdev->dev, "Chrontel TV encoder detected\n");
break;
case HASVB_LVDS_CHRONTEL:
hw_info->ulExternalChip = 0x5;
dev_info(&pdev->dev,
"LVDS transmitter and Chrontel TV encoder detected\n");
break;
default:
dev_info(&pdev->dev, "No or unknown bridge type detected\n");
break;
}
if (xgifb_info->hasVB != HASVB_NONE)
XGIfb_detect_VB(xgifb_info);
else if (xgifb_info->chip != XG21)
xgifb_info->display2 = XGIFB_DISP_NONE;
if (xgifb_info->display2 == XGIFB_DISP_LCD) {
if (!enable_dstn) {
reg = xgifb_reg_get(vb->P3d4,
IND_XGI_LCD_PANEL);
reg &= 0x0f;
hw_info->ulCRT2LCDType = XGI310paneltype[reg];
}
}
xgifb_info->mode_idx = -1;
if (mode)
XGIfb_search_mode(xgifb_info, mode);
else if (vesa != -1)
XGIfb_search_vesamode(xgifb_info, vesa);
if (xgifb_info->mode_idx >= 0)
xgifb_info->mode_idx =
XGIfb_validate_mode(xgifb_info, xgifb_info->mode_idx);
if (xgifb_info->mode_idx < 0) {
if (xgifb_info->display2 == XGIFB_DISP_LCD &&
xgifb_info->chip == XG21)
xgifb_info->mode_idx =
XGIfb_GetXG21DefaultLVDSModeIdx(xgifb_info);
else
xgifb_info->mode_idx = DEFAULT_MODE;
}
if (xgifb_info->mode_idx < 0) {
dev_err(&pdev->dev, "No supported video mode found\n");
ret = -EINVAL;
goto error_1;
}
/* set default refresh rate */
xgifb_info->refresh_rate = refresh_rate;
if (xgifb_info->refresh_rate == 0)
xgifb_info->refresh_rate = 60;
if (XGIfb_search_refresh_rate(xgifb_info, xgifb_info->refresh_rate) == 0) {
xgifb_info->rate_idx = 1;
xgifb_info->refresh_rate = 60;
}
xgifb_info->video_bpp = XGIbios_mode[xgifb_info->mode_idx].bpp;
xgifb_info->video_vwidth =
xgifb_info->video_width =
XGIbios_mode[xgifb_info->mode_idx].xres;
xgifb_info->video_vheight =
xgifb_info->video_height =
XGIbios_mode[xgifb_info->mode_idx].yres;
xgifb_info->org_x = 0;
xgifb_info->org_y = 0;
xgifb_info->video_linelength =
xgifb_info->video_width *
(xgifb_info->video_bpp >> 3);
switch (xgifb_info->video_bpp) {
case 8:
xgifb_info->DstColor = 0x0000;
xgifb_info->XGI310_AccelDepth = 0x00000000;
xgifb_info->video_cmap_len = 256;
break;
case 16:
xgifb_info->DstColor = 0x8000;
xgifb_info->XGI310_AccelDepth = 0x00010000;
xgifb_info->video_cmap_len = 16;
break;
case 32:
xgifb_info->DstColor = 0xC000;
xgifb_info->XGI310_AccelDepth = 0x00020000;
xgifb_info->video_cmap_len = 16;
break;
default:
xgifb_info->video_cmap_len = 16;
pr_info("Unsupported depth %d\n",
xgifb_info->video_bpp);
break;
}
pr_info("Default mode is %dx%dx%d (%dHz)\n",
xgifb_info->video_width, xgifb_info->video_height,
xgifb_info->video_bpp, xgifb_info->refresh_rate);
fb_info->var.red.length = 8;
fb_info->var.green.length = 8;
fb_info->var.blue.length = 8;
fb_info->var.activate = FB_ACTIVATE_NOW;
fb_info->var.height = -1;
fb_info->var.width = -1;
fb_info->var.vmode = FB_VMODE_NONINTERLACED;
fb_info->var.xres = xgifb_info->video_width;
fb_info->var.xres_virtual = xgifb_info->video_width;
fb_info->var.yres = xgifb_info->video_height;
fb_info->var.yres_virtual = xgifb_info->video_height;
fb_info->var.bits_per_pixel = xgifb_info->video_bpp;
XGIfb_bpp_to_var(xgifb_info, &fb_info->var);
fb_info->var.pixclock = (u32)(1000000000 / XGIfb_mode_rate_to_dclock
(vb, hw_info,
XGIbios_mode[xgifb_info->mode_idx].mode_no));
if (XGIfb_mode_rate_to_ddata(vb, hw_info,
XGIbios_mode[xgifb_info->mode_idx].mode_no,
&fb_info->var.left_margin,
&fb_info->var.right_margin,
&fb_info->var.upper_margin,
&fb_info->var.lower_margin,
&fb_info->var.hsync_len,
&fb_info->var.vsync_len,
&fb_info->var.sync,
&fb_info->var.vmode)) {
if ((fb_info->var.vmode & FB_VMODE_MASK) ==
FB_VMODE_INTERLACED) {
fb_info->var.yres <<= 1;
fb_info->var.yres_virtual <<= 1;
} else if ((fb_info->var.vmode & FB_VMODE_MASK) ==
FB_VMODE_DOUBLE) {
fb_info->var.pixclock >>= 1;
fb_info->var.yres >>= 1;
fb_info->var.yres_virtual >>= 1;
}
}
fb_info->flags = FBINFO_FLAG_DEFAULT;
fb_info->screen_base = xgifb_info->video_vbase;
fb_info->fbops = &XGIfb_ops;
XGIfb_get_fix(&fb_info->fix, -1, fb_info);
fb_info->pseudo_palette = xgifb_info->pseudo_palette;
fb_alloc_cmap(&fb_info->cmap, 256, 0);
xgifb_info->mtrr = arch_phys_wc_add(xgifb_info->video_base,
xgifb_info->video_size);
if (register_framebuffer(fb_info) < 0) {
ret = -EINVAL;
goto error_mtrr;
}
dumpVGAReg(xgifb_info);
return 0;
error_mtrr:
arch_phys_wc_del(xgifb_info->mtrr);
error_1:
iounmap(xgifb_info->mmio_vbase);
iounmap(xgifb_info->video_vbase);
release_mem_region(xgifb_info->mmio_base, xgifb_info->mmio_size);
error_0:
release_mem_region(xgifb_info->video_base, xgifb_info->video_size);
error_disable:
pci_disable_device(pdev);
error:
framebuffer_release(fb_info);
return ret;
}
/* -------------------- PCI DEVICE HANDLING -------------------- */
static void xgifb_remove(struct pci_dev *pdev)
{
struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
struct fb_info *fb_info = xgifb_info->fb_info;
unregister_framebuffer(fb_info);
arch_phys_wc_del(xgifb_info->mtrr);
iounmap(xgifb_info->mmio_vbase);
iounmap(xgifb_info->video_vbase);
release_mem_region(xgifb_info->mmio_base, xgifb_info->mmio_size);
release_mem_region(xgifb_info->video_base, xgifb_info->video_size);
pci_disable_device(pdev);
framebuffer_release(fb_info);
}
static struct pci_driver xgifb_driver = {
.name = "xgifb",
.id_table = xgifb_pci_table,
.probe = xgifb_probe,
.remove = xgifb_remove
};
/* -------------------- MODULE -------------------- */
module_param(mode, charp, 0000);
MODULE_PARM_DESC(mode,
"Selects the desired default display mode in the format XxYxDepth (eg. 1024x768x16).");
module_param(forcecrt2type, charp, 0000);
MODULE_PARM_DESC(forcecrt2type,
"Force the second display output type. Possible values are NONE, LCD, TV, VGA, SVIDEO or COMPOSITE.");
module_param(vesa, int, 0000);
MODULE_PARM_DESC(vesa,
"Selects the desired default display mode by VESA mode number (eg. 0x117).");
module_param(filter, int, 0000);
MODULE_PARM_DESC(filter,
"Selects TV flicker filter type (only for systems with a SiS301 video bridge). Possible values 0-7. Default: [no filter]).");
static int __init xgifb_init(void)
{
char *option = NULL;
if (forcecrt2type)
XGIfb_search_crt2type(forcecrt2type);
if (fb_get_options("xgifb", &option))
return -ENODEV;
XGIfb_setup(option);
return pci_register_driver(&xgifb_driver);
}
static void __exit xgifb_remove_module(void)
{
pci_unregister_driver(&xgifb_driver);
pr_debug("Module unloaded\n");
}
MODULE_DESCRIPTION("Z7 Z9 Z9S Z11 framebuffer device driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("XGITECH , Others");
module_init(xgifb_init);
module_exit(xgifb_remove_module);
drivers/staging/xgifb/XGIfb.h deleted 100644 → 0
View file @ 9a413526
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _LINUX_XGIFB
#define _LINUX_XGIFB
#include "vgatypes.h"
#include "vb_struct.h"
enum xgifb_display_type {
XGIFB_DISP_NONE = 0,
XGIFB_DISP_CRT,
XGIFB_DISP_LCD,
XGIFB_DISP_TV,
};
#define HASVB_NONE 0x00
#define HASVB_301 0x01
#define HASVB_LVDS 0x02
#define HASVB_TRUMPION 0x04
#define HASVB_LVDS_CHRONTEL 0x10
#define HASVB_302 0x20
#define HASVB_CHRONTEL 0x80
enum XGI_CHIP_TYPE {
XG40 = 32,
XG42,
XG20 = 48,
XG21,
XG27,
};
enum xgi_tvtype {
TVMODE_NTSC = 0,
TVMODE_PAL,
TVMODE_HIVISION,
TVTYPE_PALM,
TVTYPE_PALN,
TVTYPE_NTSCJ,
TVMODE_TOTAL
};
enum xgi_tv_plug {
TVPLUG_UNKNOWN = 0,
TVPLUG_COMPOSITE = 1,
TVPLUG_SVIDEO = 2,
TVPLUG_COMPOSITE_AND_SVIDEO = 3,
TVPLUG_SCART = 4,
TVPLUG_YPBPR_525i = 5,
TVPLUG_YPBPR_525P = 6,
TVPLUG_YPBPR_750P = 7,
TVPLUG_YPBPR_1080i = 8,
TVPLUG_TOTAL
};
struct xgifb_video_info {
struct fb_info *fb_info;
struct xgi_hw_device_info hw_info;
struct vb_device_info dev_info;
int mode_idx;
int rate_idx;
u32 pseudo_palette[17];
int chip_id;
unsigned int video_size;
phys_addr_t video_base;
void __iomem *video_vbase;
phys_addr_t mmio_base;
unsigned long mmio_size;
void __iomem *mmio_vbase;
unsigned long vga_base;
int mtrr;
int video_bpp;
int video_cmap_len;
int video_width;
int video_height;
int video_vwidth;
int video_vheight;
int org_x;
int org_y;
int video_linelength;
unsigned int refresh_rate;
enum xgifb_display_type display2; /* the second display output type */
bool display2_force;
unsigned char hasVB;
unsigned char TV_type;
unsigned char TV_plug;
struct XGI21_LVDSCapStruct lvds_data;
enum XGI_CHIP_TYPE chip;
unsigned char revision_id;
unsigned short DstColor;
unsigned long XGI310_AccelDepth;
unsigned long CommandReg;
unsigned int pcibus;
unsigned int pcislot;
unsigned int pcifunc;
unsigned short subsysvendor;
unsigned short subsysdevice;
char reserved[236];
};
#endif
drivers/staging/xgifb/vb_def.h deleted 100644 → 0
View file @ 9a413526
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _VB_DEF_
#define _VB_DEF_
#include "../../video/fbdev/sis/initdef.h"
#define VB_XGI301C 0x0020 /* for 301C */
#define SupportCRT2in301C 0x0100 /* for 301C */
#define SetCHTVOverScan 0x8000
#define PanelResInfo 0x1F /* CR36 Panel Type/LCDResInfo */
#define Panel_1024x768x75 0x22
#define Panel_1280x1024x75 0x23
#define PanelRef60Hz 0x00
#define PanelRef75Hz 0x20
#define YPbPr525iVCLK 0x03B
#define YPbPr525iVCLK_2 0x03A
#define XGI_CRT2_PORT_00 (0x00 - 0x030)
#define SupportAllCRT2 0x0078
#define NoSupportTV 0x0070
#define NoSupportHiVisionTV 0x0060
#define NoSupportLCD 0x0058
/* -------------- SetMode Stack/Scratch */
#define XGI_SetCRT2ToLCDA 0x0100
#define SetCRT2ToDualEdge 0x8000
#define ReserveTVOption 0x0008
#define SetTVLowResolution 0x0400
#define TVSimuMode 0x0800
#define RPLLDIV2XO 0x1000
#define NTSC1024x768 0x2000
#define SetTVLockMode 0x4000
#define XGI_LCDVESATiming 0x0001 /* LCD Info/CR37 */
#define XGI_EnableLVDSDDA 0x0002
#define EnableScalingLCD 0x0008
#define SetPWDEnable 0x0004
#define SetLCDtoNonExpanding 0x0010
#define SetLCDDualLink 0x0100
#define SetLCDLowResolution 0x0200
/* LCD Capability shampoo */
#define DefaultLCDCap 0x80ea
#define EnableLCD24bpp 0x0004 /* default */
#define LCDPolarity 0x00c0 /* default: SyncNN */
#define XGI_LCDDualLink 0x0100
#define EnableSpectrum 0x0200
#define PWDEnable 0x0400
#define EnableVBCLKDRVLOW 0x4000
#define EnablePLLSPLOW 0x8000
#define AVIDEOSense 0x01 /* CR32 */
#define SVIDEOSense 0x02
#define SCARTSense 0x04
#define LCDSense 0x08
#define Monitor2Sense 0x10
#define Monitor1Sense 0x20
#define HiTVSense 0x40
#define YPbPrSense 0x80 /* NEW SCRATCH */
#define TVSense 0xc7
#define YPbPrMode 0xe0
#define YPbPrMode525i 0x00
#define YPbPrMode525p 0x20
#define YPbPrMode750p 0x40
#define YPbPrMode1080i 0x60
#define ScalingLCD 0x08
#define SetYPbPr 0x04
/* ---------------------- VUMA Information */
#define DisplayDeviceFromCMOS 0x10
/* ---------------------- HK Evnet Definition */
#define XGI_ModeSwitchStatus 0xf0
#define ActiveCRT1 0x10
#define ActiveLCD 0x0020
#define ActiveTV 0x40
#define ActiveCRT2 0x80
#define ActiveAVideo 0x01
#define ActiveSVideo 0x02
#define ActiveSCART 0x04
#define ActiveHiTV 0x08
#define ActiveYPbPr 0x10
#define NTSC1024x768HT 1908
#define YPbPrTV525iHT 1716 /* YPbPr */
#define YPbPrTV525iVT 525
#define YPbPrTV525pHT 1716
#define YPbPrTV525pVT 525
#define YPbPrTV750pHT 1650
#define YPbPrTV750pVT 750
#define VCLK25_175 0x00
#define VCLK28_322 0x01
#define VCLK31_5 0x02
#define VCLK36 0x03
#define VCLK43_163 0x05
#define VCLK44_9 0x06
#define VCLK49_5 0x07
#define VCLK50 0x08
#define VCLK52_406 0x09
#define VCLK56_25 0x0A
#define VCLK68_179 0x0D
#define VCLK72_852 0x0E
#define VCLK75 0x0F
#define VCLK78_75 0x11
#define VCLK79_411 0x12
#define VCLK83_95 0x13
#define VCLK86_6 0x15
#define VCLK94_5 0x16
#define VCLK113_309 0x1B
#define VCLK116_406 0x1C
#define VCLK135_5 0x1E
#define VCLK139_054 0x1F
#define VCLK157_5 0x20
#define VCLK162 0x21
#define VCLK175 0x22
#define VCLK189 0x23
#define VCLK202_5 0x25
#define VCLK229_5 0x26
#define VCLK234 0x27
#define VCLK254_817 0x29
#define VCLK266_952 0x2B
#define VCLK269_655 0x2C
#define VCLK277_015 0x2E
#define VCLK291_132 0x30
#define VCLK291_766 0x31
#define VCLK315_195 0x33
#define VCLK323_586 0x34
#define VCLK330_615 0x35
#define VCLK340_477 0x37
#define VCLK375_847 0x38
#define VCLK388_631 0x39
#define VCLK125_999 0x51
#define VCLK148_5 0x52
#define VCLK217_325 0x55
#define XGI_YPbPr750pVCLK 0x57
#define VCLK39_77 0x40
#define YPbPr525pVCLK 0x3A
#define NTSC1024VCLK 0x41
#define VCLK35_2 0x49 /* ; 800x480 */
#define VCLK122_61 0x4A
#define VCLK80_350 0x4B
#define VCLK107_385 0x4C
#define RES320x200 0x00
#define RES320x240 0x01
#define RES400x300 0x02
#define RES512x384 0x03
#define RES640x400 0x04
#define RES640x480x60 0x05
#define RES640x480x72 0x06
#define RES640x480x75 0x07
#define RES640x480x85 0x08
#define RES640x480x100 0x09
#define RES640x480x120 0x0A
#define RES640x480x160 0x0B
#define RES640x480x200 0x0C
#define RES800x600x56 0x0D
#define RES800x600x60 0x0E
#define RES800x600x72 0x0F
#define RES800x600x75 0x10
#define RES800x600x85 0x11
#define RES800x600x100 0x12
#define RES800x600x120 0x13
#define RES800x600x160 0x14
#define RES1024x768x43 0x15
#define RES1024x768x60 0x16
#define RES1024x768x70 0x17
#define RES1024x768x75 0x18
#define RES1024x768x85 0x19
#define RES1024x768x100 0x1A
#define RES1024x768x120 0x1B
#define RES1280x1024x43 0x1C
#define RES1280x1024x60 0x1D
#define RES1280x1024x75 0x1E
#define RES1280x1024x85 0x1F
#define RES1600x1200x60 0x20
#define RES1600x1200x65 0x21
#define RES1600x1200x70 0x22
#define RES1600x1200x75 0x23
#define RES1600x1200x85 0x24
#define RES1600x1200x100 0x25
#define RES1600x1200x120 0x26
#define RES1920x1440x60 0x27
#define RES1920x1440x65 0x28
#define RES1920x1440x70 0x29
#define RES1920x1440x75 0x2A
#define RES1920x1440x85 0x2B
#define RES1920x1440x100 0x2C
#define RES2048x1536x60 0x2D
#define RES2048x1536x65 0x2E
#define RES2048x1536x70 0x2F
#define RES2048x1536x75 0x30
#define RES2048x1536x85 0x31
#define RES800x480x60 0x32
#define RES800x480x75 0x33
#define RES800x480x85 0x34
#define RES1024x576x60 0x35
#define RES1024x576x75 0x36
#define RES1024x576x85 0x37
#define RES1280x720x60 0x38
#define RES1280x720x75 0x39
#define RES1280x720x85 0x3A
#define RES1280x960x60 0x3B
#define RES720x480x60 0x3C
#define RES720x576x56 0x3D
#define RES856x480x79I 0x3E
#define RES856x480x60 0x3F
#define RES1280x768x60 0x40
#define RES1400x1050x60 0x41
#define RES1152x864x60 0x42
#define RES1152x864x75 0x43
#define RES1024x768x160 0x44
#define RES1280x960x75 0x45
#define RES1280x960x85 0x46
#define RES1280x960x120 0x47
#define XG27_CR8F 0x0C
#define XG27_SR36 0x30
#define XG27_SR40 0x04
#define XG27_SR41 0x00
#define XG40_CRCF 0x13
#define XGI330_CRT2Data_1_2 0
#define XGI330_CRT2Data_4_D 0
#define XGI330_CRT2Data_4_E 0
#define XGI330_CRT2Data_4_10 0x80
#define XGI330_SR07 0x18
#define XGI330_SR1F 0
#define XGI330_SR23 0xf6
#define XGI330_SR24 0x0d
#define XGI330_SR31 0xc0
#define XGI330_SR32 0x11
#define XGI330_SR33 0
extern const struct XGI_ExtStruct XGI330_EModeIDTable[];
extern const struct XGI_Ext2Struct XGI330_RefIndex[];
extern const struct XGI_CRT1TableStruct XGI_CRT1Table[];
extern const struct XGI_ECLKDataStruct XGI340_ECLKData[];
extern const struct SiS_VCLKData XGI_VCLKData[];
extern const unsigned char XGI340_CR6B[][4];
extern const unsigned char XGI340_AGPReg[];
#endif
drivers/staging/xgifb/vb_init.c deleted 100644 → 0
View file @ 9a413526
// SPDX-License-Identifier: GPL-2.0
#include <linux/delay.h>
#include <linux/vmalloc.h>
#include "XGIfb.h"
#include "vb_def.h"
#include "vb_util.h"
#include "vb_setmode.h"
#include "vb_init.h"
static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
{ 16, 0x45},
{ 8, 0x35},
{ 4, 0x31},
{ 2, 0x21} };
static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
{ 128, 0x5D},
{ 64, 0x59},
{ 64, 0x4D},
{ 32, 0x55},
{ 32, 0x49},
{ 32, 0x3D},
{ 16, 0x51},
{ 16, 0x45},
{ 16, 0x39},
{ 8, 0x41},
{ 8, 0x35},
{ 4, 0x31} };
#define XGIFB_ROM_SIZE 65536
static unsigned char
XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
struct vb_device_info *pVBInfo)
{
unsigned char data, temp;
if (HwDeviceExtension->jChipType < XG20) {
data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
if (data == 0)
data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
0x02) >> 1;
return data;
} else if (HwDeviceExtension->jChipType == XG27) {
temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
/* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
data = 0; /* DDR */
else
data = 1; /* DDRII */
return data;
} else if (HwDeviceExtension->jChipType == XG21) {
/* Independent GPIO control */
xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
usleep_range(800, 1800);
xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
/* GPIOF 0:DVI 1:DVO */
data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
/*
* HOTPLUG_SUPPORT
* for current XG20 & XG21, GPIOH is floating, driver will
* fix DDR temporarily
*/
/* DVI read GPIOH */
data &= 0x01; /* 1=DDRII, 0=DDR */
/* ~HOTPLUG_SUPPORT */
xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
return data;
}
data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
if (data == 1)
data++;
return data;
}
static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
struct vb_device_info *pVBInfo)
{
xgifb_reg_set(P3c4, 0x18, 0x01);
xgifb_reg_set(P3c4, 0x19, 0x20);
xgifb_reg_set(P3c4, 0x16, 0x00);
xgifb_reg_set(P3c4, 0x16, 0x80);
usleep_range(3, 1003);
xgifb_reg_set(P3c4, 0x18, 0x00);
xgifb_reg_set(P3c4, 0x19, 0x20);
xgifb_reg_set(P3c4, 0x16, 0x00);
xgifb_reg_set(P3c4, 0x16, 0x80);
usleep_range(60, 1060);
xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
xgifb_reg_set(P3c4, 0x19, 0x01);
xgifb_reg_set(P3c4, 0x16, 0x03);
xgifb_reg_set(P3c4, 0x16, 0x83);
usleep_range(1, 1001);
xgifb_reg_set(P3c4, 0x1B, 0x03);
usleep_range(500, 1500);
xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
xgifb_reg_set(P3c4, 0x19, 0x00);
xgifb_reg_set(P3c4, 0x16, 0x03);
xgifb_reg_set(P3c4, 0x16, 0x83);
xgifb_reg_set(P3c4, 0x1B, 0x00);
}
static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
{
xgifb_reg_set(pVBInfo->P3c4,
0x28,
pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
xgifb_reg_set(pVBInfo->P3c4,
0x29,
pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
xgifb_reg_set(pVBInfo->P3c4,
0x2A,
pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
xgifb_reg_set(pVBInfo->P3c4,
0x2E,
XGI340_ECLKData[pVBInfo->ram_type].SR2E);
xgifb_reg_set(pVBInfo->P3c4,
0x2F,
XGI340_ECLKData[pVBInfo->ram_type].SR2F);
xgifb_reg_set(pVBInfo->P3c4,
0x30,
XGI340_ECLKData[pVBInfo->ram_type].SR30);
}
static void XGINew_DDRII_Bootup_XG27(
struct xgi_hw_device_info *HwDeviceExtension,
unsigned long P3c4, struct vb_device_info *pVBInfo)
{
unsigned long P3d4 = P3c4 + 0x10;
pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
XGINew_SetMemoryClock(pVBInfo);
/* Set Double Frequency */
xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
usleep_range(200, 1200);
xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
usleep_range(15, 1015);
xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
usleep_range(15, 1015);
xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
usleep_range(15, 1015);
xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
usleep_range(15, 1015);
xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
usleep_range(30, 1030);
xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
usleep_range(15, 1015);
xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
usleep_range(30, 1030);
xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
usleep_range(60, 1060);
xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
usleep_range(30, 1030);
xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
usleep_range(15, 1015);
xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
usleep_range(30, 1030);
xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
usleep_range(15, 1015);
xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
usleep_range(30, 1030);
xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
usleep_range(15, 1015);
/* Set SR1B refresh control 000:close; 010:open */
xgifb_reg_set(P3c4, 0x1B, 0x04);
usleep_range(200, 1200);
}
static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
unsigned long P3c4,
struct vb_device_info *pVBInfo)
{
unsigned long P3d4 = P3c4 + 0x10;
pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
XGINew_SetMemoryClock(pVBInfo);
xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
usleep_range(200, 1200);
xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
xgifb_reg_set(P3c4, 0x19, 0x80);
xgifb_reg_set(P3c4, 0x16, 0x05);
xgifb_reg_set(P3c4, 0x16, 0x85);
xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
xgifb_reg_set(P3c4, 0x19, 0xC0);
xgifb_reg_set(P3c4, 0x16, 0x05);
xgifb_reg_set(P3c4, 0x16, 0x85);
xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
xgifb_reg_set(P3c4, 0x19, 0x40);
xgifb_reg_set(P3c4, 0x16, 0x05);
xgifb_reg_set(P3c4, 0x16, 0x85);
xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
xgifb_reg_set(P3c4, 0x19, 0x02);
xgifb_reg_set(P3c4, 0x16, 0x05);
xgifb_reg_set(P3c4, 0x16, 0x85);
usleep_range(15, 1015);
xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
usleep_range(30, 1030);
xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
usleep_range(100, 1100);
xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
xgifb_reg_set(P3c4, 0x19, 0x00);
xgifb_reg_set(P3c4, 0x16, 0x05);
xgifb_reg_set(P3c4, 0x16, 0x85);
usleep_range(200, 1200);
}
static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
struct vb_device_info *pVBInfo)
{
xgifb_reg_set(P3c4, 0x18, 0x01);
xgifb_reg_set(P3c4, 0x19, 0x40);
xgifb_reg_set(P3c4, 0x16, 0x00);
xgifb_reg_set(P3c4, 0x16, 0x80);
usleep_range(60, 1060);
xgifb_reg_set(P3c4, 0x18, 0x00);
xgifb_reg_set(P3c4, 0x19, 0x40);
xgifb_reg_set(P3c4, 0x16, 0x00);
xgifb_reg_set(P3c4, 0x16, 0x80);
usleep_range(60, 1060);
xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
xgifb_reg_set(P3c4, 0x19, 0x01);
xgifb_reg_set(P3c4, 0x16, 0x03);
xgifb_reg_set(P3c4, 0x16, 0x83);
usleep_range(1, 1001);
xgifb_reg_set(P3c4, 0x1B, 0x03);
usleep_range(500, 1500);
xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
xgifb_reg_set(P3c4, 0x19, 0x00);
xgifb_reg_set(P3c4, 0x16, 0x03);
xgifb_reg_set(P3c4, 0x16, 0x83);
xgifb_reg_set(P3c4, 0x1B, 0x00);
}
static void XGINew_DDR1x_DefaultRegister(
struct xgi_hw_device_info *HwDeviceExtension,
unsigned long Port, struct vb_device_info *pVBInfo)
{
unsigned long P3d4 = Port, P3c4 = Port - 0x10;
if (HwDeviceExtension->jChipType >= XG20) {
XGINew_SetMemoryClock(pVBInfo);
xgifb_reg_set(P3d4,
0x82,
pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
xgifb_reg_set(P3d4,
0x85,
pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
xgifb_reg_set(P3d4,
0x86,
pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
xgifb_reg_set(P3d4, 0x98, 0x01);
xgifb_reg_set(P3d4, 0x9A, 0x02);
XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
} else {
XGINew_SetMemoryClock(pVBInfo);
switch (HwDeviceExtension->jChipType) {
case XG42:
/* CR82 */
xgifb_reg_set(P3d4,
0x82,
pVBInfo->CR40[11][pVBInfo->ram_type]);
/* CR85 */
xgifb_reg_set(P3d4,
0x85,
pVBInfo->CR40[12][pVBInfo->ram_type]);
/* CR86 */
xgifb_reg_set(P3d4,
0x86,
pVBInfo->CR40[13][pVBInfo->ram_type]);
break;
default:
xgifb_reg_set(P3d4, 0x82, 0x88);
xgifb_reg_set(P3d4, 0x86, 0x00);
/* Insert read command for delay */
xgifb_reg_get(P3d4, 0x86);
xgifb_reg_set(P3d4, 0x86, 0x88);
xgifb_reg_get(P3d4, 0x86);
xgifb_reg_set(P3d4,
0x86,
pVBInfo->CR40[13][pVBInfo->ram_type]);
xgifb_reg_set(P3d4, 0x82, 0x77);
xgifb_reg_set(P3d4, 0x85, 0x00);
/* Insert read command for delay */
xgifb_reg_get(P3d4, 0x85);
xgifb_reg_set(P3d4, 0x85, 0x88);
/* Insert read command for delay */
xgifb_reg_get(P3d4, 0x85);
/* CR85 */
xgifb_reg_set(P3d4,
0x85,
pVBInfo->CR40[12][pVBInfo->ram_type]);
/* CR82 */
xgifb_reg_set(P3d4,
0x82,
pVBInfo->CR40[11][pVBInfo->ram_type]);
break;
}
xgifb_reg_set(P3d4, 0x97, 0x00);
xgifb_reg_set(P3d4, 0x98, 0x01);
xgifb_reg_set(P3d4, 0x9A, 0x02);
XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
}
}
static void XGINew_DDR2_DefaultRegister(
struct xgi_hw_device_info *HwDeviceExtension,
unsigned long Port, struct vb_device_info *pVBInfo)
{
unsigned long P3d4 = Port, P3c4 = Port - 0x10;
/*
* keep following setting sequence, each setting in
* the same reg insert idle
*/
xgifb_reg_set(P3d4, 0x82, 0x77);
xgifb_reg_set(P3d4, 0x86, 0x00);
xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
xgifb_reg_set(P3d4, 0x86, 0x88);
xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
/* CR86 */
xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
xgifb_reg_set(P3d4, 0x82, 0x77);
xgifb_reg_set(P3d4, 0x85, 0x00);
xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
xgifb_reg_set(P3d4, 0x85, 0x88);
xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
xgifb_reg_set(P3d4,
0x85,
pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
if (HwDeviceExtension->jChipType == XG27)
/* CR82 */
xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
else
xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
xgifb_reg_set(P3d4, 0x98, 0x01);
xgifb_reg_set(P3d4, 0x9A, 0x02);
if (HwDeviceExtension->jChipType == XG27)
XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
else
XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
}
static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
u8 shift_factor, u8 mask1, u8 mask2)
{
u8 j;
for (j = 0; j < 4; j++) {
temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
xgifb_reg_set(P3d4, reg, temp2);
xgifb_reg_get(P3d4, reg);
temp2 &= mask1;
temp2 += mask2;
}
}
static void XGINew_SetDRAMDefaultRegister340(
struct xgi_hw_device_info *HwDeviceExtension,
unsigned long Port, struct vb_device_info *pVBInfo)
{
unsigned char temp, temp1, temp2, temp3, j, k;
unsigned long P3d4 = Port, P3c4 = Port - 0x10;
xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
/* CR6B DQS fine tune delay */
temp = 0xaa;
XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
/* CR6E DQM fine tune delay */
XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
temp3 = 0;
for (k = 0; k < 4; k++) {
/* CR6E_D[1:0] select channel */
xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
temp3 += 0x01;
}
xgifb_reg_set(P3d4,
0x80,
pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
xgifb_reg_set(P3d4,
0x81,
pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
temp2 = 0x80;
/* CR89 terminator type select */
XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
temp = 0;
temp1 = temp & 0x03;
temp2 |= temp1;
xgifb_reg_set(P3d4, 0x89, temp2);
temp = pVBInfo->CR40[3][pVBInfo->ram_type];
temp1 = temp & 0x0F;
temp2 = (temp >> 4) & 0x07;
temp3 = temp & 0x80;
xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
xgifb_reg_set(P3d4,
0x41,
pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
if (HwDeviceExtension->jChipType == XG27)
xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
for (j = 0; j <= 6; j++) /* CR90 - CR96 */
xgifb_reg_set(P3d4, (0x90 + j),
pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
xgifb_reg_set(P3d4, (0xC3 + j),
pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
for (j = 0; j < 2; j++) /* CR8A - CR8B */
xgifb_reg_set(P3d4, (0x8A + j),
pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
if (HwDeviceExtension->jChipType == XG42)
xgifb_reg_set(P3d4, 0x8C, 0x87);
xgifb_reg_set(P3d4,
0x59,
pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
if (pVBInfo->ram_type) {
xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
if (HwDeviceExtension->jChipType == XG27)
xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
} else {
xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
}
xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
if (temp == 0) {
XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
} else {
xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
}
xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
}
static unsigned short XGINew_SetDRAMSize20Reg(
unsigned short dram_size,
struct vb_device_info *pVBInfo)
{
unsigned short data = 0, memsize = 0;
int RankSize;
unsigned char ChannelNo;
RankSize = dram_size * pVBInfo->ram_bus / 8;
data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
data &= 0x80;
if (data == 0x80)
RankSize *= 2;
data = 0;
if (pVBInfo->ram_channel == 3)
ChannelNo = 4;
else
ChannelNo = pVBInfo->ram_channel;
if (ChannelNo * RankSize <= 256) {
while ((RankSize >>= 1) > 0)
data += 0x10;
memsize = data >> 4;
/* Fix DRAM Sizing Error */
xgifb_reg_set(pVBInfo->P3c4,
0x14,
(xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
(data & 0xF0));
usleep_range(15, 1015);
}
return memsize;
}
static int XGINew_ReadWriteRest(unsigned short StopAddr,
unsigned short StartAddr,
struct vb_device_info *pVBInfo)
{
int i;
unsigned long Position = 0;
void __iomem *fbaddr = pVBInfo->FBAddr;
writel(Position, fbaddr + Position);
for (i = StartAddr; i <= StopAddr; i++) {
Position = 1 << i;
writel(Position, fbaddr + Position);
}
/* Fix #1759 Memory Size error in Multi-Adapter. */
usleep_range(500, 1500);
Position = 0;
if (readl(fbaddr + Position) != Position)
return 0;
for (i = StartAddr; i <= StopAddr; i++) {
Position = 1 << i;
if (readl(fbaddr + Position) != Position)
return 0;
}
return 1;
}
static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
{
unsigned char data;
data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
if ((data & 0x10) == 0) {
data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
return (data & 0x02) >> 1;
}
return data & 0x01;
}
static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
struct vb_device_info *pVBInfo)
{
unsigned char data;
switch (HwDeviceExtension->jChipType) {
case XG20:
case XG21:
data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
data = data & 0x01;
pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
if (data == 0) { /* Single_32_16 */
if ((HwDeviceExtension->ulVideoMemorySize - 1)
> 0x1000000) {
pVBInfo->ram_bus = 32; /* 32 bits */
/* 22bit + 2 rank + 32bit */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
usleep_range(15, 1015);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
return;
if ((HwDeviceExtension->ulVideoMemorySize - 1) >
0x800000) {
/* 22bit + 1 rank + 32bit */
xgifb_reg_set(pVBInfo->P3c4,
0x13,
0x31);
xgifb_reg_set(pVBInfo->P3c4,
0x14,
0x42);
usleep_range(15, 1015);
if (XGINew_ReadWriteRest(23,
23,
pVBInfo) == 1)
return;
}
}
if ((HwDeviceExtension->ulVideoMemorySize - 1) >
0x800000) {
pVBInfo->ram_bus = 16; /* 16 bits */
/* 22bit + 2 rank + 16bit */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
usleep_range(15, 1015);
if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
return;
xgifb_reg_set(pVBInfo->P3c4,
0x13,
0x31);
usleep_range(15, 1015);
}
} else { /* Dual_16_8 */
if ((HwDeviceExtension->ulVideoMemorySize - 1) >
0x800000) {
pVBInfo->ram_bus = 16; /* 16 bits */
/* (0x31:12x8x2) 22bit + 2 rank */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
/* 0x41:16Mx16 bit */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
usleep_range(15, 1015);
if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
return;
if ((HwDeviceExtension->ulVideoMemorySize - 1) >
0x400000) {
/* (0x31:12x8x2) 22bit + 1 rank */
xgifb_reg_set(pVBInfo->P3c4,
0x13,
0x31);
/* 0x31:8Mx16 bit */
xgifb_reg_set(pVBInfo->P3c4,
0x14,
0x31);
usleep_range(15, 1015);
if (XGINew_ReadWriteRest(22,
22,
pVBInfo) == 1)
return;
}
}
if ((HwDeviceExtension->ulVideoMemorySize - 1) >
0x400000) {
pVBInfo->ram_bus = 8; /* 8 bits */
/* (0x31:12x8x2) 22bit + 2 rank */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
/* 0x30:8Mx8 bit */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
usleep_range(15, 1015);
if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
return;
/* (0x31:12x8x2) 22bit + 1 rank */
xgifb_reg_set(pVBInfo->P3c4,
0x13,
0x31);
usleep_range(15, 1015);
}
}
break;
case XG27:
pVBInfo->ram_bus = 16; /* 16 bits */
pVBInfo->ram_channel = 1; /* Single channel */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit */
break;
case XG42:
/*
* XG42 SR14 D[3] Reserve
* D[2] = 1, Dual Channel
* = 0, Single Channel
*
* It's Different from Other XG40 Series.
*/
if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
pVBInfo->ram_bus = 32; /* 32 bits */
pVBInfo->ram_channel = 2; /* 2 Channel */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
return;
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
return;
pVBInfo->ram_channel = 1; /* Single Channel */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
return;
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
} else { /* DDR */
pVBInfo->ram_bus = 64; /* 64 bits */
pVBInfo->ram_channel = 1; /* 1 channels */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
return;
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
}
break;
default: /* XG40 */
if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
pVBInfo->ram_bus = 32; /* 32 bits */
pVBInfo->ram_channel = 3;
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
return;
pVBInfo->ram_channel = 2; /* 2 channels */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
return;
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
pVBInfo->ram_channel = 3; /* 4 channels */
} else {
pVBInfo->ram_channel = 2; /* 2 channels */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
}
} else { /* DDR */
pVBInfo->ram_bus = 64; /* 64 bits */
pVBInfo->ram_channel = 2; /* 2 channels */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
return;
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
}
break;
}
}
static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
struct vb_device_info *pVBInfo)
{
u8 i, size;
unsigned short memsize, start_addr;
const unsigned short (*dram_table)[2];
xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
if (HwDeviceExtension->jChipType >= XG20) {
dram_table = XGINew_DDRDRAM_TYPE20;
size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
start_addr = 5;
} else {
dram_table = XGINew_DDRDRAM_TYPE340;
size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
start_addr = 9;
}
for (i = 0; i < size; i++) {
/* SetDRAMSizingType */
xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
usleep_range(50, 1050); /* should delay 50 ns */
memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
if (memsize == 0)
continue;
memsize += (pVBInfo->ram_channel - 2) + 20;
if ((HwDeviceExtension->ulVideoMemorySize - 1) <
(unsigned long)(1 << memsize))
continue;
if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
return 1;
}
return 0;
}
static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
struct xgi_hw_device_info *HwDeviceExtension,
struct vb_device_info *pVBInfo)
{
unsigned short data;
pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
/* disable read cache */
xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF));
XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
/* enable read cache */
xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20));
}
static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
{
void __iomem *rom_address;
u8 *rom_copy;
rom_address = pci_map_rom(dev, rom_size);
if (!rom_address)
return NULL;
rom_copy = vzalloc(XGIFB_ROM_SIZE);
if (!rom_copy)
goto done;
*rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
memcpy_fromio(rom_copy, rom_address, *rom_size);
done:
pci_unmap_rom(dev, rom_address);
return rom_copy;
}
static bool xgifb_read_vbios(struct pci_dev *pdev)
{
struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
u8 *vbios;
unsigned long i;
unsigned char j;
struct XGI21_LVDSCapStruct *lvds;
size_t vbios_size;
int entry;
vbios = xgifb_copy_rom(pdev, &vbios_size);
if (!vbios) {
dev_err(&pdev->dev, "Video BIOS not available\n");
return false;
}
if (vbios_size <= 0x65)
goto error;
/*
* The user can ignore the LVDS bit in the BIOS and force the display
* type.
*/
if (!(vbios[0x65] & 0x1) &&
(!xgifb_info->display2_force ||
xgifb_info->display2 != XGIFB_DISP_LCD)) {
vfree(vbios);
return false;
}
if (vbios_size <= 0x317)
goto error;
i = vbios[0x316] | (vbios[0x317] << 8);
if (vbios_size <= i - 1)
goto error;
j = vbios[i - 1];
if (j == 0)
goto error;
if (j == 0xff)
j = 1;
/* Read the LVDS table index scratch register set by the BIOS. */
entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
if (entry >= j)
entry = 0;
i += entry * 25;
lvds = &xgifb_info->lvds_data;
if (vbios_size <= i + 24)
goto error;
lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8);
lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8);
lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8);
lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8);
lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8);
lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8);
lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8);
lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8);
lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8);
lvds->VCLKData1 = vbios[i + 18];
lvds->VCLKData2 = vbios[i + 19];
lvds->PSC_S1 = vbios[i + 20];
lvds->PSC_S2 = vbios[i + 21];
lvds->PSC_S3 = vbios[i + 22];
lvds->PSC_S4 = vbios[i + 23];
lvds->PSC_S5 = vbios[i + 24];
vfree(vbios);
return true;
error:
dev_err(&pdev->dev, "Video BIOS corrupted\n");
vfree(vbios);
return false;
}
static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
{
unsigned short tempbx = 0, temp, tempcx, CR3CData;
temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
if (temp & Monitor1Sense)
tempbx |= ActiveCRT1;
if (temp & LCDSense)
tempbx |= ActiveLCD;
if (temp & Monitor2Sense)
tempbx |= ActiveCRT2;
if (temp & TVSense) {
tempbx |= ActiveTV;
if (temp & AVIDEOSense)
tempbx |= (ActiveAVideo << 8);
if (temp & SVIDEOSense)
tempbx |= (ActiveSVideo << 8);
if (temp & SCARTSense)
tempbx |= (ActiveSCART << 8);
if (temp & HiTVSense)
tempbx |= (ActiveHiTV << 8);
if (temp & YPbPrSense)
tempbx |= (ActiveYPbPr << 8);
}
tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
if (tempbx & tempcx) {
CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
if (!(CR3CData & DisplayDeviceFromCMOS))
tempcx = 0x1FF0;
} else {
tempcx = 0x1FF0;
}
tempbx &= tempcx;
xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
}
static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
{
unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
if (temp & ActiveCRT2)
tempcl = SetCRT2ToRAMDAC;
}
if (temp & ActiveLCD) {
tempcl |= SetCRT2ToLCD;
if (temp & DriverMode) {
if (temp & ActiveTV) {
tempch = SetToLCDA | EnableDualEdge;
temp ^= SetCRT2ToLCD;
if ((temp >> 8) & ActiveAVideo)
tempcl |= SetCRT2ToAVIDEO;
if ((temp >> 8) & ActiveSVideo)
tempcl |= SetCRT2ToSVIDEO;
if ((temp >> 8) & ActiveSCART)
tempcl |= SetCRT2ToSCART;
if (pVBInfo->IF_DEF_HiVision == 1) {
if ((temp >> 8) & ActiveHiTV)
tempcl |= SetCRT2ToHiVision;
}
if (pVBInfo->IF_DEF_YPbPr == 1) {
if ((temp >> 8) & ActiveYPbPr)
tempch |= SetYPbPr;
}
}
}
} else {
if ((temp >> 8) & ActiveAVideo)
tempcl |= SetCRT2ToAVIDEO;
if ((temp >> 8) & ActiveSVideo)
tempcl |= SetCRT2ToSVIDEO;
if ((temp >> 8) & ActiveSCART)
tempcl |= SetCRT2ToSCART;
if (pVBInfo->IF_DEF_HiVision == 1) {
if ((temp >> 8) & ActiveHiTV)
tempcl |= SetCRT2ToHiVision;
}
if (pVBInfo->IF_DEF_YPbPr == 1) {
if ((temp >> 8) & ActiveYPbPr)
tempch |= SetYPbPr;
}
}
tempcl |= SetSimuScanMode;
if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) ||
(temp & ActiveTV) ||
(temp & ActiveCRT2)))
tempcl ^= (SetSimuScanMode | SwitchCRT2);
if ((temp & ActiveLCD) && (temp & ActiveTV))
tempcl ^= (SetSimuScanMode | SwitchCRT2);
xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
CR31Data &= ~(SetNotSimuMode >> 8);
if (!(temp & ActiveCRT1))
CR31Data |= (SetNotSimuMode >> 8);
CR31Data &= ~(DisableCRT2Display >> 8);
if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
CR31Data |= (DisableCRT2Display >> 8);
xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
CR38Data &= ~SetYPbPr;
CR38Data |= tempch;
xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
}
static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
*HwDeviceExtension,
struct vb_device_info *pVBInfo)
{
unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
switch (HwDeviceExtension->ulCRT2LCDType) {
case LCD_640x480:
case LCD_1024x600:
case LCD_1152x864:
case LCD_1280x960:
case LCD_1152x768:
case LCD_1920x1440:
case LCD_2048x1536:
temp = 0; /* overwrite used ulCRT2LCDType */
break;
case LCD_UNKNOWN: /* unknown lcd, do nothing */
return 0;
}
xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
return 1;
}
static void XGINew_GetXG21Sense(struct pci_dev *pdev,
struct vb_device_info *pVBInfo)
{
struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
unsigned char Temp;
if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
/* LVDS on chip */
xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
} else {
/* Enable GPIOA/B read */
xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
/* Enable read GPIOF */
xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
Temp = 0xA0; /* Only DVO on chip */
else
Temp = 0x80; /* TMDS on chip */
xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
/* Disable read GPIOF */
xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
}
}
}
static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
{
unsigned char Temp, bCR4A;
bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
/* Enable GPIOA/B/C read */
xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
if (Temp <= 0x02) {
/* LVDS setting */
xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
} else {
/* TMDS/DVO setting */
xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
}
xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
}
static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
{
unsigned char CR38, CR4A, temp;
CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
/* enable GPIOE read */
xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
temp = 0;
if ((CR38 & 0xE0) > 0x80) {
temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
temp &= 0x08;
temp >>= 3;
}
xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
return temp;
}
static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
{
unsigned char CR4A, temp;
CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
/* enable GPIOA/B/C read */
xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
if (temp > 2)
temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
return temp;
}
static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
{
u8 flag;
flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
return flag == 1 || flag == 2;
}
unsigned char XGIInitNew(struct pci_dev *pdev)
{
struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
struct vb_device_info VBINF;
struct vb_device_info *pVBInfo = &VBINF;
unsigned char i, temp = 0, temp1;
pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
if (!pVBInfo->FBAddr) {
dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
return 0;
}
XGIRegInit(pVBInfo, xgifb_info->vga_base);
outb(0x67, pVBInfo->P3c2);
InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
/* Openkey */
xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
/* GetXG21Sense (GPIO) */
if (HwDeviceExtension->jChipType == XG21)
XGINew_GetXG21Sense(pdev, pVBInfo);
if (HwDeviceExtension->jChipType == XG27)
XGINew_GetXG27Sense(pVBInfo);
/* Reset Extended register */
for (i = 0x06; i < 0x20; i++)
xgifb_reg_set(pVBInfo->P3c4, i, 0);
for (i = 0x21; i <= 0x27; i++)
xgifb_reg_set(pVBInfo->P3c4, i, 0);
for (i = 0x31; i <= 0x3B; i++)
xgifb_reg_set(pVBInfo->P3c4, i, 0);
/* Auto over driver for XG42 */
if (HwDeviceExtension->jChipType == XG42)
xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
for (i = 0x79; i <= 0x7C; i++)
xgifb_reg_set(pVBInfo->P3d4, i, 0);
if (HwDeviceExtension->jChipType >= XG20)
xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
/* SetDefExt1Regs begin */
xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
if (HwDeviceExtension->jChipType == XG27) {
xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
}
xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
/* Frame buffer can read/write SR20 */
xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
/* H/W request for slow corner chip */
xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
if (HwDeviceExtension->jChipType == XG27)
xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
if (HwDeviceExtension->jChipType < XG20) {
u32 Temp;
/* Set AGP customize registers (in SetDefAGPRegs) Start */
for (i = 0x47; i <= 0x4C; i++)
xgifb_reg_set(pVBInfo->P3d4,
i,
XGI340_AGPReg[i - 0x47]);
for (i = 0x70; i <= 0x71; i++)
xgifb_reg_set(pVBInfo->P3d4,
i,
XGI340_AGPReg[6 + i - 0x70]);
for (i = 0x74; i <= 0x77; i++)
xgifb_reg_set(pVBInfo->P3d4,
i,
XGI340_AGPReg[8 + i - 0x74]);
pci_read_config_dword(pdev, 0x50, &Temp);
Temp >>= 20;
Temp &= 0xF;
if (Temp == 1)
xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
} /* != XG20 */
/* Set PCI */
xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
if (HwDeviceExtension->jChipType < XG20) {
/* Set VB */
XGI_UnLockCRT2(pVBInfo);
/* disable VideoCapture */
xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
/* chk if BCLK>=100MHz */
temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
xgifb_reg_set(pVBInfo->Part1Port,
0x02, XGI330_CRT2Data_1_2);
xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
} /* != XG20 */
xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
if ((HwDeviceExtension->jChipType == XG42) &&
XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
/* Not DDR */
xgifb_reg_set(pVBInfo->P3c4,
0x31,
(XGI330_SR31 & 0x3F) | 0x40);
xgifb_reg_set(pVBInfo->P3c4,
0x32,
(XGI330_SR32 & 0xFC) | 0x01);
} else {
xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
}
xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
if (HwDeviceExtension->jChipType < XG20) {
if (xgifb_bridge_is_on(pVBInfo)) {
xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
xgifb_reg_set(pVBInfo->Part4Port,
0x0D, XGI330_CRT2Data_4_D);
xgifb_reg_set(pVBInfo->Part4Port,
0x0E, XGI330_CRT2Data_4_E);
xgifb_reg_set(pVBInfo->Part4Port,
0x10, XGI330_CRT2Data_4_10);
xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
XGI_LockCRT2(pVBInfo);
}
} /* != XG20 */
XGI_SenseCRT1(pVBInfo);
if (HwDeviceExtension->jChipType == XG21) {
xgifb_reg_and_or(pVBInfo->P3d4,
0x32,
~Monitor1Sense,
Monitor1Sense); /* Z9 default has CRT */
temp = GetXG21FPBits(pVBInfo);
xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
}
if (HwDeviceExtension->jChipType == XG27) {
xgifb_reg_and_or(pVBInfo->P3d4,
0x32,
~Monitor1Sense,
Monitor1Sense); /* Z9 default has CRT */
temp = GetXG27FPBits(pVBInfo);
xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
}
pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
pVBInfo->P3d4,
pVBInfo);
XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
XGINew_ChkSenseStatus(pVBInfo);
XGINew_SetModeScratch(pVBInfo);
xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
return 1;
} /* end of init */
drivers/staging/xgifb/vb_init.h deleted 100644 → 0
View file @ 9a413526
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _VBINIT_
#define _VBINIT_
unsigned char XGIInitNew(struct pci_dev *pdev);
void XGIRegInit(struct vb_device_info *XGI_Pr, unsigned long BaseAddr);
#endif
drivers/staging/xgifb/vb_setmode.c deleted 100644 → 0
View file @ 9a413526
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/staging/xgifb/vb_setmode.h deleted 100644 → 0
View file @ 9a413526
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _VBSETMODE_
#define _VBSETMODE_
void InitTo330Pointer(unsigned char ChipType, struct vb_device_info *pVBInfo);
void XGI_UnLockCRT2(struct vb_device_info *pVBInfo);
void XGI_LockCRT2(struct vb_device_info *pVBInfo);
void XGI_DisplayOff(struct xgifb_video_info *xgifb_info,
struct xgi_hw_device_info *pXGIHWDE,
struct vb_device_info *pVBInfo);
void XGI_GetVBType(struct vb_device_info *pVBInfo);
void XGI_SenseCRT1(struct vb_device_info *pVBInfo);
unsigned char XGISetModeNew(struct xgifb_video_info *xgifb_info,
struct xgi_hw_device_info *HwDeviceExtension,
unsigned short ModeNo);
unsigned char XGI_SearchModeID(unsigned short ModeNo,
unsigned short *ModeIdIndex);
unsigned short XGI_GetRatePtrCRT2(struct xgi_hw_device_info *pXGIHWDE,
unsigned short ModeNo,
unsigned short ModeIdIndex,
struct vb_device_info *pVBInfo);
#endif
drivers/staging/xgifb/vb_struct.h deleted 100644 → 0
View file @ 9a413526
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _VB_STRUCT_
#define _VB_STRUCT_
#include "../../video/fbdev/sis/vstruct.h"
struct XGI_LVDSCRT1HDataStruct {
unsigned char Reg[8];
};
struct XGI_LVDSCRT1VDataStruct {
unsigned char Reg[7];
};
struct XGI_ExtStruct {
unsigned char Ext_ModeID;
unsigned short Ext_ModeFlag;
unsigned short Ext_ModeInfo;
unsigned char Ext_RESINFO;
unsigned char VB_ExtTVYFilterIndex;
unsigned char REFindex;
};
struct XGI_Ext2Struct {
unsigned short Ext_InfoFlag;
unsigned char Ext_CRT1CRTC;
unsigned char Ext_CRTVCLK;
unsigned char Ext_CRT2CRTC;
unsigned char Ext_CRT2CRTC2;
unsigned char ModeID;
unsigned short XRes;
unsigned short YRes;
};
struct XGI_ECLKDataStruct {
unsigned char SR2E, SR2F, SR30;
unsigned short CLOCK;
};
/*add for new UNIVGABIOS*/
struct XGI_LCDDesStruct {
unsigned short LCDHDES;
unsigned short LCDHRS;
unsigned short LCDVDES;
unsigned short LCDVRS;
};
struct XGI330_LCDDataDesStruct2 {
unsigned short LCDHDES;
unsigned short LCDHRS;
unsigned short LCDVDES;
unsigned short LCDVRS;
unsigned short LCDHSync;
unsigned short LCDVSync;
};
struct XGI330_LCDDataTablStruct {
unsigned char PANELID;
unsigned short MASK;
unsigned short CAP;
void const *DATAPTR;
};
struct XGI330_TVDataTablStruct {
unsigned short MASK;
unsigned short CAP;
struct SiS_TVData const *DATAPTR;
};
struct XGI_TimingHStruct {
unsigned char data[8];
};
struct XGI_TimingVStruct {
unsigned char data[7];
};
struct XGI_XG21CRT1Struct {
unsigned char ModeID, CR02, CR03, CR15, CR16;
};
struct XGI330_LCDCapStruct {
unsigned char LCD_ID;
unsigned short LCD_Capability;
unsigned char LCD_HSyncWidth;
unsigned char LCD_VSyncWidth;
unsigned char LCD_VCLK;
unsigned char LCDA_VCLKData1;
unsigned char LCDA_VCLKData2;
unsigned char LCUCHAR_VCLKData1;
unsigned char LCUCHAR_VCLKData2;
unsigned char Spectrum_31;
unsigned char Spectrum_32;
unsigned char Spectrum_33;
unsigned char Spectrum_34;
};
struct XGI21_LVDSCapStruct {
unsigned short LVDS_Capability;
unsigned short LVDSHT;
unsigned short LVDSVT;
unsigned short LVDSHDE;
unsigned short LVDSVDE;
unsigned short LVDSHFP;
unsigned short LVDSVFP;
unsigned short LVDSHSYNC;
unsigned short LVDSVSYNC;
unsigned char VCLKData1;
unsigned char VCLKData2;
unsigned char PSC_S1; /* Duration between CPL on and signal on */
unsigned char PSC_S2; /* Duration signal on and Vdd on */
unsigned char PSC_S3; /* Duration between CPL off and signal off */
unsigned char PSC_S4; /* Duration signal off and Vdd off */
unsigned char PSC_S5;
};
struct XGI_CRT1TableStruct {
unsigned char CR[16];
};
struct XGI301C_Tap4TimingStruct {
unsigned short DE;
unsigned char Reg[64]; /* C0-FF */
};
struct vb_device_info {
unsigned long P3c4, P3d4, P3c0, P3ce, P3c2, P3cc;
unsigned long P3ca, P3c6, P3c7, P3c8, P3c9, P3da;
unsigned long Part0Port, Part1Port, Part2Port;
unsigned long Part3Port, Part4Port, Part5Port;
unsigned short RVBHCFACT, RVBHCMAX, RVBHRS;
unsigned short VGAVT, VGAHT, VGAVDE, VGAHDE;
unsigned short VT, HT, VDE, HDE;
unsigned short LCDHRS, LCDVRS, LCDHDES, LCDVDES;
unsigned short ModeType;
unsigned short IF_DEF_LVDS;
unsigned short IF_DEF_CRT2Monitor;
unsigned short IF_DEF_YPbPr;
unsigned short IF_DEF_HiVision;
unsigned short LCDResInfo, LCDTypeInfo, VBType;/*301b*/
unsigned short VBInfo, TVInfo, LCDInfo;
unsigned short SetFlag;
unsigned short NewFlickerMode;
unsigned short SelectCRT2Rate;
void __iomem *FBAddr;
unsigned char const *SR18;
unsigned char const (*CR40)[3];
struct SiS_MCLKData const *MCLKData;
unsigned char XGINew_CR97;
struct XGI330_LCDCapStruct const *LCDCapList;
struct XGI_TimingHStruct TimingH;
struct XGI_TimingVStruct TimingV;
int ram_type;
int ram_channel;
int ram_bus;
}; /* _struct vb_device_info */
#endif /* _VB_STRUCT_ */
drivers/staging/xgifb/vb_table.h deleted 100644 → 0
View file @ 9a413526
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/staging/xgifb/vb_util.h deleted 100644 → 0
View file @ 9a413526
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _VBUTIL_
#define _VBUTIL_
static inline void xgifb_reg_set(unsigned long port, u8 index, u8 data)
{
outb(index, port);
outb(data, port + 1);
}
static inline u8 xgifb_reg_get(unsigned long port, u8 index)
{
outb(index, port);
return inb(port + 1);
}
static inline void xgifb_reg_and_or(unsigned long port, u8 index,
unsigned int data_and, unsigned int data_or)
{
u8 temp;
temp = xgifb_reg_get(port, index);
temp = (u8)((temp & data_and) | data_or);
xgifb_reg_set(port, index, temp);
}
static inline void xgifb_reg_and(unsigned long port, u8 index,
unsigned int data_and)
{
u8 temp;
temp = xgifb_reg_get(port, index);
temp = (u8)(temp & data_and);
xgifb_reg_set(port, index, temp);
}
static inline void xgifb_reg_or(unsigned long port, u8 index,
unsigned int data_or)
{
u8 temp;
temp = xgifb_reg_get(port, index);
temp |= data_or;
xgifb_reg_set(port, index, temp);
}
#endif
drivers/staging/xgifb/vgatypes.h deleted 100644 → 0
View file @ 9a413526
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _VGATYPES_
#define _VGATYPES_
#include <linux/fb.h> /* for struct fb_var_screeninfo for sis.h */
#include "../../video/fbdev/sis/vgatypes.h"
#include "../../video/fbdev/sis/sis.h" /* for LCD_TYPE */
enum XGI_VB_CHIP_TYPE {
VB_CHIP_Legacy = 0,
VB_CHIP_301,
VB_CHIP_301B,
VB_CHIP_301LV,
VB_CHIP_302,
VB_CHIP_302B,
VB_CHIP_302LV,
VB_CHIP_301C,
VB_CHIP_302ELV,
VB_CHIP_UNKNOWN, /* other video bridge or no video bridge */
MAX_VB_CHIP
};
struct xgi_hw_device_info {
unsigned long ulExternalChip; /* NO VB or other video bridge*/
/* if ujVBChipID = VB_CHIP_UNKNOWN, */
void __iomem *pjVideoMemoryAddress;/* base virtual memory address */
/* of Linear VGA memory */
unsigned long ulVideoMemorySize; /* size, in bytes, of the
* memory on the board
*/
unsigned char jChipType; /* Used to Identify Graphics Chip */
/* defined in the data structure type */
/* "XGI_CHIP_TYPE" */
unsigned char jChipRevision; /* Used to Identify Graphics
* Chip Revision
*/
unsigned char ujVBChipID; /* the ID of video bridge */
/* defined in the data structure type */
/* "XGI_VB_CHIP_TYPE" */
unsigned long ulCRT2LCDType; /* defined in the data structure type */
};
/* Additional IOCTL for communication xgifb <> X driver */
/* If changing this, xgifb.h must also be changed (for xgifb) */
#endif
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7