Commit b2520dbc authored by Ranjani Sridharan's avatar Ranjani Sridharan Committed by Mark Brown

ASoC: SOF: Intel: define and set the disable_interrupts op for cavs platforms

Disable the IPC and SDW nterrupts in the disable_interrupts op for
cavs platforms.
Signed-off-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220922213644.666315-7-ranjani.sridharan@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 423693a6
...@@ -105,6 +105,7 @@ const struct sof_intel_dsp_desc apl_chip_info = { ...@@ -105,6 +105,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
.check_ipc_irq = hda_dsp_check_ipc_irq, .check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init, .cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp, .power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS, .hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS,
}; };
EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -413,6 +413,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = { ...@@ -413,6 +413,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
.check_ipc_irq = hda_dsp_check_ipc_irq, .check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init, .cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp, .power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_1_8, .hw_ip_version = SOF_INTEL_CAVS_1_8,
}; };
EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -444,6 +445,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = { ...@@ -444,6 +445,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
.check_ipc_irq = hda_dsp_check_ipc_irq, .check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init, .cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp, .power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_0, .hw_ip_version = SOF_INTEL_CAVS_2_0,
}; };
EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -989,3 +989,11 @@ int hda_dsp_core_get(struct snd_sof_dev *sdev, int core) ...@@ -989,3 +989,11 @@ int hda_dsp_core_get(struct snd_sof_dev *sdev, int core)
return ret; return ret;
} }
int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev)
{
hda_sdw_int_enable(sdev, false);
hda_dsp_ipc_int_disable(sdev);
return 0;
}
...@@ -587,6 +587,7 @@ void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); ...@@ -587,6 +587,7 @@ void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
void hda_ipc_dump(struct snd_sof_dev *sdev); void hda_ipc_dump(struct snd_sof_dev *sdev);
void hda_ipc_irq_dump(struct snd_sof_dev *sdev); void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
void hda_dsp_d0i3_work(struct work_struct *work); void hda_dsp_d0i3_work(struct work_struct *work);
int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev);
/* /*
* DSP PCM Operations. * DSP PCM Operations.
......
...@@ -176,6 +176,7 @@ const struct sof_intel_dsp_desc icl_chip_info = { ...@@ -176,6 +176,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
.check_ipc_irq = hda_dsp_check_ipc_irq, .check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init, .cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp, .power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_0, .hw_ip_version = SOF_INTEL_CAVS_2_0,
}; };
EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -112,6 +112,7 @@ const struct sof_intel_dsp_desc skl_chip_info = { ...@@ -112,6 +112,7 @@ const struct sof_intel_dsp_desc skl_chip_info = {
.rom_init_timeout = 300, .rom_init_timeout = 300,
.check_ipc_irq = hda_dsp_check_ipc_irq, .check_ipc_irq = hda_dsp_check_ipc_irq,
.power_down_dsp = hda_power_down_dsp, .power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_1_5, .hw_ip_version = SOF_INTEL_CAVS_1_5,
}; };
EXPORT_SYMBOL_NS(skl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(skl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -131,6 +131,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = { ...@@ -131,6 +131,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
.check_ipc_irq = hda_dsp_check_ipc_irq, .check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init, .cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp, .power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_5, .hw_ip_version = SOF_INTEL_CAVS_2_5,
}; };
EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -155,6 +156,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = { ...@@ -155,6 +156,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
.check_ipc_irq = hda_dsp_check_ipc_irq, .check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init, .cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp, .power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_5, .hw_ip_version = SOF_INTEL_CAVS_2_5,
}; };
EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -179,6 +181,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = { ...@@ -179,6 +181,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
.check_ipc_irq = hda_dsp_check_ipc_irq, .check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init, .cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp, .power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_5, .hw_ip_version = SOF_INTEL_CAVS_2_5,
}; };
EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -203,6 +206,7 @@ const struct sof_intel_dsp_desc adls_chip_info = { ...@@ -203,6 +206,7 @@ const struct sof_intel_dsp_desc adls_chip_info = {
.check_ipc_irq = hda_dsp_check_ipc_irq, .check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init, .cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp, .power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_5, .hw_ip_version = SOF_INTEL_CAVS_2_5,
}; };
EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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