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Commit b3ab8adc authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Update Broadwell events to V22 

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20180118234518.GA27753@tassilo.jf.intel.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent b3fa3896
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tools/perf/pmu-events/arch/x86/broadwell/cache.json
View file @ b3ab8adc
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tools/perf/pmu-events/arch/x86/broadwell/floating-point.json
View file @ b3ab8adc
[ [
{ {
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", "PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
"EventCode": "0xC1", "EventCode": "0xC1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "UMask": "0x8",
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", "PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
"EventCode": "0xC1", "EventCode": "0xC1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "UMask": "0x10",
...@@ -22,7 +22,6 @@ ...@@ -22,7 +22,6 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PEBS": "1",
"EventCode": "0xC7", "EventCode": "0xC7",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x1",
...@@ -32,7 +31,6 @@ ...@@ -32,7 +31,6 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PEBS": "1",
"EventCode": "0xC7", "EventCode": "0xC7",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x2",
...@@ -42,7 +40,15 @@ ...@@ -42,7 +40,15 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PEBS": "1", "EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xC7", "EventCode": "0xC7",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x4",
...@@ -52,7 +58,6 @@ ...@@ -52,7 +58,6 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PEBS": "1",
"EventCode": "0xC7", "EventCode": "0xC7",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "UMask": "0x8",
...@@ -62,7 +67,6 @@ ...@@ -62,7 +67,6 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PEBS": "1",
"EventCode": "0xC7", "EventCode": "0xC7",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "UMask": "0x10",
...@@ -72,7 +76,43 @@ ...@@ -72,7 +76,43 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", "EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x15",
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
"SampleAfterValue": "2000006",
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xc7",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x2a",
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
"SampleAfterValue": "2000005",
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x3c",
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
"SampleAfterValue": "2000004",
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"CounterHTOff": "0,1,2,3"
},
{
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
"EventCode": "0xCA", "EventCode": "0xCA",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x2",
...@@ -82,7 +122,7 @@ ...@@ -82,7 +122,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
"EventCode": "0xCA", "EventCode": "0xCA",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x4",
...@@ -92,7 +132,7 @@ ...@@ -92,7 +132,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
"EventCode": "0xCA", "EventCode": "0xCA",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "UMask": "0x8",
...@@ -102,7 +142,7 @@ ...@@ -102,7 +142,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
"EventCode": "0xCA", "EventCode": "0xCA",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "UMask": "0x10",
...@@ -121,51 +161,5 @@ ...@@ -121,51 +161,5 @@
"BriefDescription": "Cycles with any input/output SSE or FP assist", "BriefDescription": "Cycles with any input/output SSE or FP assist",
"CounterMask": "1", "CounterMask": "1",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
},
{
"PEBS": "1",
"EventCode": "0xc7",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x3c",
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
"SampleAfterValue": "2000004",
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x2a",
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
"SampleAfterValue": "2000005",
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x15",
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
"SampleAfterValue": "2000006",
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
"CounterHTOff": "0,1,2,3"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/broadwell/frontend.json
View file @ b3ab8adc
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x4",
...@@ -20,80 +20,49 @@ ...@@ -20,80 +20,49 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "UMask": "0x4",
"EventName": "IDQ.DSB_UOPS", "EventName": "IDQ.MITE_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "IDQ.MS_DSB_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "IDQ.MS_MITE_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "IDQ.MS_UOPS",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x30", "UMask": "0x8",
"EventName": "IDQ.MS_CYCLES", "EventName": "IDQ.DSB_UOPS",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ.", "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x8",
"EventName": "IDQ.MITE_CYCLES", "EventName": "IDQ.DSB_CYCLES",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
"CounterMask": "1", "CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "UMask": "0x10",
"EventName": "IDQ.DSB_CYCLES", "EventName": "IDQ.MS_DSB_UOPS",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "UMask": "0x10",
...@@ -104,7 +73,7 @@ ...@@ -104,7 +73,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "UMask": "0x10",
...@@ -116,7 +85,7 @@ ...@@ -116,7 +85,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x18", "UMask": "0x18",
...@@ -127,7 +96,7 @@ ...@@ -127,7 +96,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x18", "UMask": "0x18",
...@@ -138,7 +107,17 @@ ...@@ -138,7 +107,17 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "IDQ.MS_MITE_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x24", "UMask": "0x24",
...@@ -149,7 +128,7 @@ ...@@ -149,7 +128,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x24", "UMask": "0x24",
...@@ -160,7 +139,39 @@ ...@@ -160,7 +139,39 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "IDQ.MS_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "IDQ.MS_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EdgeDetect": "1",
"EventName": "IDQ.MS_SWITCHES",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x3c", "UMask": "0x3c",
...@@ -200,7 +211,7 @@ ...@@ -200,7 +211,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding ?4 ? x? when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
"EventCode": "0x9C", "EventCode": "0x9C",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x1",
...@@ -263,7 +274,7 @@ ...@@ -263,7 +274,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0?2 cycles.", "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
"EventCode": "0xAB", "EventCode": "0xAB",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x2",
...@@ -271,16 +282,5 @@ ...@@ -271,16 +282,5 @@
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EdgeDetect": "1",
"EventName": "IDQ.MS_SWITCHES",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/broadwell/memory.json
View file @ b3ab8adc
...@@ -90,7 +90,6 @@ ...@@ -90,7 +90,6 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "Unfriendly TSX abort triggered by a flowmarker.",
"EventCode": "0x5d", "EventCode": "0x5d",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x1",
...@@ -170,13 +169,13 @@ ...@@ -170,13 +169,13 @@
}, },
{ {
"PEBS": "1", "PEBS": "1",
"PublicDescription": "Number of times HLE abort was triggered.", "PublicDescription": "Number of times HLE abort was triggered (PEBS).",
"EventCode": "0xc8", "EventCode": "0xc8",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x4",
"EventName": "HLE_RETIRED.ABORTED", "EventName": "HLE_RETIRED.ABORTED",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of times HLE abort was triggered", "BriefDescription": "Number of times HLE abort was triggered (PEBS)",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
...@@ -251,13 +250,13 @@ ...@@ -251,13 +250,13 @@
}, },
{ {
"PEBS": "1", "PEBS": "1",
"PublicDescription": "Number of times RTM abort was triggered .", "PublicDescription": "Number of times RTM abort was triggered (PEBS).",
"EventCode": "0xc9", "EventCode": "0xc9",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x4",
"EventName": "RTM_RETIRED.ABORTED", "EventName": "RTM_RETIRED.ABORTED",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of times RTM abort was triggered", "BriefDescription": "Number of times RTM abort was triggered (PEBS)",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
...@@ -431,6 +430,7 @@ ...@@ -431,6 +430,7 @@
"CounterHTOff": "3" "CounterHTOff": "3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020001 ", "MSRValue": "0x2000020001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -443,6 +443,7 @@ ...@@ -443,6 +443,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts demand data reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0001 ", "MSRValue": "0x20003c0001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -455,6 +456,7 @@ ...@@ -455,6 +456,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000001 ", "MSRValue": "0x0084000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -467,6 +469,7 @@ ...@@ -467,6 +469,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000001 ", "MSRValue": "0x0104000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -479,6 +482,7 @@ ...@@ -479,6 +482,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000001 ", "MSRValue": "0x0204000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -491,6 +495,7 @@ ...@@ -491,6 +495,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000001 ", "MSRValue": "0x0404000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -503,6 +508,7 @@ ...@@ -503,6 +508,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000001 ", "MSRValue": "0x1004000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -515,6 +521,7 @@ ...@@ -515,6 +521,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000001 ", "MSRValue": "0x2004000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -527,6 +534,7 @@ ...@@ -527,6 +534,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000001 ", "MSRValue": "0x3f84000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -539,6 +547,7 @@ ...@@ -539,6 +547,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts demand data reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000001 ", "MSRValue": "0x00bc000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -551,6 +560,7 @@ ...@@ -551,6 +560,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000001 ", "MSRValue": "0x013c000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -563,6 +573,7 @@ ...@@ -563,6 +573,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts demand data reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000001 ", "MSRValue": "0x023c000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -575,6 +586,7 @@ ...@@ -575,6 +586,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000001 ", "MSRValue": "0x043c000001 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -587,6 +599,7 @@ ...@@ -587,6 +599,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0002 ", "MSRValue": "0x20003c0002 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -599,6 +612,7 @@ ...@@ -599,6 +612,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000002 ", "MSRValue": "0x3f84000002 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -611,6 +625,7 @@ ...@@ -611,6 +625,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000002 ", "MSRValue": "0x00bc000002 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -623,6 +638,7 @@ ...@@ -623,6 +638,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000002 ", "MSRValue": "0x013c000002 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -635,6 +651,7 @@ ...@@ -635,6 +651,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000002 ", "MSRValue": "0x023c000002 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -647,6 +664,7 @@ ...@@ -647,6 +664,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000002 ", "MSRValue": "0x043c000002 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -659,6 +677,7 @@ ...@@ -659,6 +677,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020004 ", "MSRValue": "0x2000020004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -671,6 +690,7 @@ ...@@ -671,6 +690,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand code reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0004 ", "MSRValue": "0x20003c0004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -683,6 +703,7 @@ ...@@ -683,6 +703,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000004 ", "MSRValue": "0x0084000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -695,6 +716,7 @@ ...@@ -695,6 +716,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000004 ", "MSRValue": "0x0104000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -707,6 +729,7 @@ ...@@ -707,6 +729,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000004 ", "MSRValue": "0x0204000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -719,6 +742,7 @@ ...@@ -719,6 +742,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000004 ", "MSRValue": "0x0404000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -731,6 +755,7 @@ ...@@ -731,6 +755,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000004 ", "MSRValue": "0x1004000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -743,6 +768,7 @@ ...@@ -743,6 +768,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000004 ", "MSRValue": "0x2004000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -755,6 +781,7 @@ ...@@ -755,6 +781,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000004 ", "MSRValue": "0x3f84000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -767,6 +794,7 @@ ...@@ -767,6 +794,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand code reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000004 ", "MSRValue": "0x00bc000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -779,6 +807,7 @@ ...@@ -779,6 +807,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000004 ", "MSRValue": "0x013c000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -791,6 +820,7 @@ ...@@ -791,6 +820,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand code reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000004 ", "MSRValue": "0x023c000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -803,6 +833,7 @@ ...@@ -803,6 +833,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000004 ", "MSRValue": "0x043c000004 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -815,6 +846,7 @@ ...@@ -815,6 +846,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020008 ", "MSRValue": "0x2000020008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -827,6 +859,7 @@ ...@@ -827,6 +859,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0008 ", "MSRValue": "0x20003c0008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -839,6 +872,7 @@ ...@@ -839,6 +872,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000008 ", "MSRValue": "0x0084000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -851,6 +885,7 @@ ...@@ -851,6 +885,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000008 ", "MSRValue": "0x0104000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -863,6 +898,7 @@ ...@@ -863,6 +898,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000008 ", "MSRValue": "0x0204000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -875,6 +911,7 @@ ...@@ -875,6 +911,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000008 ", "MSRValue": "0x0404000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -887,6 +924,7 @@ ...@@ -887,6 +924,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000008 ", "MSRValue": "0x1004000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -899,6 +937,7 @@ ...@@ -899,6 +937,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000008 ", "MSRValue": "0x2004000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -911,6 +950,7 @@ ...@@ -911,6 +950,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000008 ", "MSRValue": "0x3f84000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -923,6 +963,7 @@ ...@@ -923,6 +963,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts writebacks (modified to exclusive) that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000008 ", "MSRValue": "0x00bc000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -935,6 +976,7 @@ ...@@ -935,6 +976,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000008 ", "MSRValue": "0x013c000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -947,6 +989,7 @@ ...@@ -947,6 +989,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts writebacks (modified to exclusive) that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000008 ", "MSRValue": "0x023c000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -959,6 +1002,7 @@ ...@@ -959,6 +1002,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000008 ", "MSRValue": "0x043c000008 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -971,6 +1015,7 @@ ...@@ -971,6 +1015,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020010 ", "MSRValue": "0x2000020010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -983,6 +1028,7 @@ ...@@ -983,6 +1028,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0010 ", "MSRValue": "0x20003c0010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -995,6 +1041,7 @@ ...@@ -995,6 +1041,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000010 ", "MSRValue": "0x0084000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1007,6 +1054,7 @@ ...@@ -1007,6 +1054,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000010 ", "MSRValue": "0x0104000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1019,6 +1067,7 @@ ...@@ -1019,6 +1067,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000010 ", "MSRValue": "0x0204000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1031,6 +1080,7 @@ ...@@ -1031,6 +1080,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000010 ", "MSRValue": "0x0404000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1043,6 +1093,7 @@ ...@@ -1043,6 +1093,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000010 ", "MSRValue": "0x1004000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1055,6 +1106,7 @@ ...@@ -1055,6 +1106,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000010 ", "MSRValue": "0x2004000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1067,6 +1119,7 @@ ...@@ -1067,6 +1119,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000010 ", "MSRValue": "0x3f84000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1079,6 +1132,7 @@ ...@@ -1079,6 +1132,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000010 ", "MSRValue": "0x00bc000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1091,6 +1145,7 @@ ...@@ -1091,6 +1145,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000010 ", "MSRValue": "0x013c000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1103,6 +1158,7 @@ ...@@ -1103,6 +1158,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000010 ", "MSRValue": "0x023c000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1115,6 +1171,7 @@ ...@@ -1115,6 +1171,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000010 ", "MSRValue": "0x043c000010 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1127,6 +1184,7 @@ ...@@ -1127,6 +1184,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020020 ", "MSRValue": "0x2000020020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1139,6 +1197,7 @@ ...@@ -1139,6 +1197,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0020 ", "MSRValue": "0x20003c0020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1151,6 +1210,7 @@ ...@@ -1151,6 +1210,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000020 ", "MSRValue": "0x0084000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1163,6 +1223,7 @@ ...@@ -1163,6 +1223,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000020 ", "MSRValue": "0x0104000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1175,6 +1236,7 @@ ...@@ -1175,6 +1236,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000020 ", "MSRValue": "0x0204000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1187,6 +1249,7 @@ ...@@ -1187,6 +1249,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000020 ", "MSRValue": "0x0404000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1199,6 +1262,7 @@ ...@@ -1199,6 +1262,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000020 ", "MSRValue": "0x1004000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1211,6 +1275,7 @@ ...@@ -1211,6 +1275,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000020 ", "MSRValue": "0x2004000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1223,6 +1288,7 @@ ...@@ -1223,6 +1288,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000020 ", "MSRValue": "0x3f84000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1235,6 +1301,7 @@ ...@@ -1235,6 +1301,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000020 ", "MSRValue": "0x00bc000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1247,6 +1314,7 @@ ...@@ -1247,6 +1314,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000020 ", "MSRValue": "0x013c000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1259,6 +1327,7 @@ ...@@ -1259,6 +1327,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000020 ", "MSRValue": "0x023c000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1271,6 +1340,7 @@ ...@@ -1271,6 +1340,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000020 ", "MSRValue": "0x043c000020 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1283,6 +1353,7 @@ ...@@ -1283,6 +1353,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020040 ", "MSRValue": "0x2000020040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1295,6 +1366,7 @@ ...@@ -1295,6 +1366,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0040 ", "MSRValue": "0x20003c0040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1307,6 +1379,7 @@ ...@@ -1307,6 +1379,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000040 ", "MSRValue": "0x0084000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1319,6 +1392,7 @@ ...@@ -1319,6 +1392,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000040 ", "MSRValue": "0x0104000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1331,6 +1405,7 @@ ...@@ -1331,6 +1405,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000040 ", "MSRValue": "0x0204000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1343,6 +1418,7 @@ ...@@ -1343,6 +1418,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000040 ", "MSRValue": "0x0404000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1355,6 +1431,7 @@ ...@@ -1355,6 +1431,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000040 ", "MSRValue": "0x1004000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1367,6 +1444,7 @@ ...@@ -1367,6 +1444,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000040 ", "MSRValue": "0x2004000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1379,6 +1457,7 @@ ...@@ -1379,6 +1457,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000040 ", "MSRValue": "0x3f84000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1391,6 +1470,7 @@ ...@@ -1391,6 +1470,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000040 ", "MSRValue": "0x00bc000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1403,6 +1483,7 @@ ...@@ -1403,6 +1483,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000040 ", "MSRValue": "0x013c000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1415,6 +1496,7 @@ ...@@ -1415,6 +1496,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000040 ", "MSRValue": "0x023c000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1427,6 +1509,7 @@ ...@@ -1427,6 +1509,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000040 ", "MSRValue": "0x043c000040 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1439,6 +1522,7 @@ ...@@ -1439,6 +1522,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020080 ", "MSRValue": "0x2000020080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1451,6 +1535,7 @@ ...@@ -1451,6 +1535,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0080 ", "MSRValue": "0x20003c0080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1463,6 +1548,7 @@ ...@@ -1463,6 +1548,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000080 ", "MSRValue": "0x0084000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1475,6 +1561,7 @@ ...@@ -1475,6 +1561,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000080 ", "MSRValue": "0x0104000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1487,6 +1574,7 @@ ...@@ -1487,6 +1574,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000080 ", "MSRValue": "0x0204000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1499,6 +1587,7 @@ ...@@ -1499,6 +1587,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000080 ", "MSRValue": "0x0404000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1511,6 +1600,7 @@ ...@@ -1511,6 +1600,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000080 ", "MSRValue": "0x1004000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1523,6 +1613,7 @@ ...@@ -1523,6 +1613,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000080 ", "MSRValue": "0x2004000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1535,6 +1626,7 @@ ...@@ -1535,6 +1626,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000080 ", "MSRValue": "0x3f84000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1547,6 +1639,7 @@ ...@@ -1547,6 +1639,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000080 ", "MSRValue": "0x00bc000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1559,6 +1652,7 @@ ...@@ -1559,6 +1652,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000080 ", "MSRValue": "0x013c000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1571,6 +1665,7 @@ ...@@ -1571,6 +1665,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000080 ", "MSRValue": "0x023c000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1583,6 +1678,7 @@ ...@@ -1583,6 +1678,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000080 ", "MSRValue": "0x043c000080 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1595,6 +1691,7 @@ ...@@ -1595,6 +1691,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020100 ", "MSRValue": "0x2000020100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1607,6 +1704,7 @@ ...@@ -1607,6 +1704,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0100 ", "MSRValue": "0x20003c0100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1619,6 +1717,7 @@ ...@@ -1619,6 +1717,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000100 ", "MSRValue": "0x0084000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1631,6 +1730,7 @@ ...@@ -1631,6 +1730,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000100 ", "MSRValue": "0x0104000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1643,6 +1743,7 @@ ...@@ -1643,6 +1743,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000100 ", "MSRValue": "0x0204000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1655,6 +1756,7 @@ ...@@ -1655,6 +1756,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000100 ", "MSRValue": "0x0404000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1667,6 +1769,7 @@ ...@@ -1667,6 +1769,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000100 ", "MSRValue": "0x1004000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1679,6 +1782,7 @@ ...@@ -1679,6 +1782,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000100 ", "MSRValue": "0x2004000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1691,6 +1795,7 @@ ...@@ -1691,6 +1795,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000100 ", "MSRValue": "0x3f84000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1703,6 +1808,7 @@ ...@@ -1703,6 +1808,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000100 ", "MSRValue": "0x00bc000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1715,6 +1821,7 @@ ...@@ -1715,6 +1821,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000100 ", "MSRValue": "0x013c000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1727,6 +1834,7 @@ ...@@ -1727,6 +1834,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000100 ", "MSRValue": "0x023c000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1739,6 +1847,7 @@ ...@@ -1739,6 +1847,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000100 ", "MSRValue": "0x043c000100 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1751,6 +1860,7 @@ ...@@ -1751,6 +1860,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020200 ", "MSRValue": "0x2000020200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1763,6 +1873,7 @@ ...@@ -1763,6 +1873,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0200 ", "MSRValue": "0x20003c0200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1775,6 +1886,7 @@ ...@@ -1775,6 +1886,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000200 ", "MSRValue": "0x0084000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1787,6 +1899,7 @@ ...@@ -1787,6 +1899,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000200 ", "MSRValue": "0x0104000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1799,6 +1912,7 @@ ...@@ -1799,6 +1912,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000200 ", "MSRValue": "0x0204000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1811,6 +1925,7 @@ ...@@ -1811,6 +1925,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000200 ", "MSRValue": "0x0404000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1823,6 +1938,7 @@ ...@@ -1823,6 +1938,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000200 ", "MSRValue": "0x1004000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1835,6 +1951,7 @@ ...@@ -1835,6 +1951,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000200 ", "MSRValue": "0x2004000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1847,6 +1964,7 @@ ...@@ -1847,6 +1964,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000200 ", "MSRValue": "0x3f84000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1859,6 +1977,7 @@ ...@@ -1859,6 +1977,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000200 ", "MSRValue": "0x00bc000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1871,6 +1990,7 @@ ...@@ -1871,6 +1990,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000200 ", "MSRValue": "0x013c000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1883,6 +2003,7 @@ ...@@ -1883,6 +2003,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000200 ", "MSRValue": "0x023c000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1895,6 +2016,7 @@ ...@@ -1895,6 +2016,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000200 ", "MSRValue": "0x043c000200 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1907,6 +2029,7 @@ ...@@ -1907,6 +2029,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000028000 ", "MSRValue": "0x2000028000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1919,6 +2042,7 @@ ...@@ -1919,6 +2042,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts any other requests that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c8000 ", "MSRValue": "0x20003c8000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1931,6 +2055,7 @@ ...@@ -1931,6 +2055,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084008000 ", "MSRValue": "0x0084008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1943,6 +2068,7 @@ ...@@ -1943,6 +2068,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104008000 ", "MSRValue": "0x0104008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1955,6 +2081,7 @@ ...@@ -1955,6 +2081,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204008000 ", "MSRValue": "0x0204008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1967,6 +2094,7 @@ ...@@ -1967,6 +2094,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404008000 ", "MSRValue": "0x0404008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1979,6 +2107,7 @@ ...@@ -1979,6 +2107,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004008000 ", "MSRValue": "0x1004008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -1991,6 +2120,7 @@ ...@@ -1991,6 +2120,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004008000 ", "MSRValue": "0x2004008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2003,6 +2133,7 @@ ...@@ -2003,6 +2133,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84008000 ", "MSRValue": "0x3f84008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2015,6 +2146,7 @@ ...@@ -2015,6 +2146,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts any other requests that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc008000 ", "MSRValue": "0x00bc008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2027,6 +2159,7 @@ ...@@ -2027,6 +2159,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c008000 ", "MSRValue": "0x013c008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2039,6 +2172,7 @@ ...@@ -2039,6 +2172,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts any other requests that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c008000 ", "MSRValue": "0x023c008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2051,6 +2185,7 @@ ...@@ -2051,6 +2185,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c008000 ", "MSRValue": "0x043c008000 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2063,6 +2198,7 @@ ...@@ -2063,6 +2198,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020090 ", "MSRValue": "0x2000020090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2075,6 +2211,7 @@ ...@@ -2075,6 +2211,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch data reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0090 ", "MSRValue": "0x20003c0090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2087,6 +2224,7 @@ ...@@ -2087,6 +2224,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000090 ", "MSRValue": "0x0084000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2099,6 +2237,7 @@ ...@@ -2099,6 +2237,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000090 ", "MSRValue": "0x0104000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2111,6 +2250,7 @@ ...@@ -2111,6 +2250,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000090 ", "MSRValue": "0x0204000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2123,6 +2263,7 @@ ...@@ -2123,6 +2263,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000090 ", "MSRValue": "0x0404000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2135,6 +2276,7 @@ ...@@ -2135,6 +2276,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000090 ", "MSRValue": "0x1004000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2147,6 +2289,7 @@ ...@@ -2147,6 +2289,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000090 ", "MSRValue": "0x2004000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2159,6 +2302,7 @@ ...@@ -2159,6 +2302,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000090 ", "MSRValue": "0x3f84000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2171,6 +2315,7 @@ ...@@ -2171,6 +2315,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch data reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000090 ", "MSRValue": "0x00bc000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2183,6 +2328,7 @@ ...@@ -2183,6 +2328,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000090 ", "MSRValue": "0x013c000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2195,6 +2341,7 @@ ...@@ -2195,6 +2341,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch data reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000090 ", "MSRValue": "0x023c000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2207,6 +2354,7 @@ ...@@ -2207,6 +2354,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000090 ", "MSRValue": "0x043c000090 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2219,6 +2367,7 @@ ...@@ -2219,6 +2367,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020120 ", "MSRValue": "0x2000020120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2231,6 +2380,7 @@ ...@@ -2231,6 +2380,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts prefetch RFOs that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0120 ", "MSRValue": "0x20003c0120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2243,6 +2393,7 @@ ...@@ -2243,6 +2393,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000120 ", "MSRValue": "0x0084000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2255,6 +2406,7 @@ ...@@ -2255,6 +2406,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000120 ", "MSRValue": "0x0104000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2267,6 +2419,7 @@ ...@@ -2267,6 +2419,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000120 ", "MSRValue": "0x0204000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2279,6 +2432,7 @@ ...@@ -2279,6 +2432,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000120 ", "MSRValue": "0x0404000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2291,6 +2445,7 @@ ...@@ -2291,6 +2445,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000120 ", "MSRValue": "0x1004000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2303,6 +2458,7 @@ ...@@ -2303,6 +2458,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000120 ", "MSRValue": "0x2004000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2315,6 +2471,7 @@ ...@@ -2315,6 +2471,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000120 ", "MSRValue": "0x3f84000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2327,6 +2484,7 @@ ...@@ -2327,6 +2484,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts prefetch RFOs that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000120 ", "MSRValue": "0x00bc000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2339,6 +2497,7 @@ ...@@ -2339,6 +2497,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000120 ", "MSRValue": "0x013c000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2351,6 +2510,7 @@ ...@@ -2351,6 +2510,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts prefetch RFOs that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000120 ", "MSRValue": "0x023c000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2363,6 +2523,7 @@ ...@@ -2363,6 +2523,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000120 ", "MSRValue": "0x043c000120 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2375,6 +2536,7 @@ ...@@ -2375,6 +2536,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020240 ", "MSRValue": "0x2000020240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2387,6 +2549,7 @@ ...@@ -2387,6 +2549,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch code reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0240 ", "MSRValue": "0x20003c0240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2399,6 +2562,7 @@ ...@@ -2399,6 +2562,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000240 ", "MSRValue": "0x0084000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2411,6 +2575,7 @@ ...@@ -2411,6 +2575,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000240 ", "MSRValue": "0x0104000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2423,6 +2588,7 @@ ...@@ -2423,6 +2588,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000240 ", "MSRValue": "0x0204000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2435,6 +2601,7 @@ ...@@ -2435,6 +2601,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000240 ", "MSRValue": "0x0404000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2447,6 +2614,7 @@ ...@@ -2447,6 +2614,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000240 ", "MSRValue": "0x1004000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2459,6 +2627,7 @@ ...@@ -2459,6 +2627,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000240 ", "MSRValue": "0x2004000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2471,6 +2640,7 @@ ...@@ -2471,6 +2640,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000240 ", "MSRValue": "0x3f84000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2483,6 +2653,7 @@ ...@@ -2483,6 +2653,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch code reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000240 ", "MSRValue": "0x00bc000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2495,6 +2666,7 @@ ...@@ -2495,6 +2666,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000240 ", "MSRValue": "0x013c000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2507,6 +2679,7 @@ ...@@ -2507,6 +2679,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all prefetch code reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000240 ", "MSRValue": "0x023c000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2519,6 +2692,7 @@ ...@@ -2519,6 +2692,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000240 ", "MSRValue": "0x043c000240 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2531,6 +2705,7 @@ ...@@ -2531,6 +2705,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020091 ", "MSRValue": "0x2000020091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2543,6 +2718,7 @@ ...@@ -2543,6 +2718,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0091 ", "MSRValue": "0x20003c0091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2555,6 +2731,7 @@ ...@@ -2555,6 +2731,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000091 ", "MSRValue": "0x0084000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2567,6 +2744,7 @@ ...@@ -2567,6 +2744,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000091 ", "MSRValue": "0x0104000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2579,6 +2757,7 @@ ...@@ -2579,6 +2757,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000091 ", "MSRValue": "0x0204000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2591,6 +2770,7 @@ ...@@ -2591,6 +2770,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000091 ", "MSRValue": "0x0404000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2603,6 +2783,7 @@ ...@@ -2603,6 +2783,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000091 ", "MSRValue": "0x1004000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2615,6 +2796,7 @@ ...@@ -2615,6 +2796,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000091 ", "MSRValue": "0x2004000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2627,6 +2809,7 @@ ...@@ -2627,6 +2809,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000091 ", "MSRValue": "0x3f84000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2639,6 +2822,7 @@ ...@@ -2639,6 +2822,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand & prefetch data reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000091 ", "MSRValue": "0x00bc000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2651,6 +2835,7 @@ ...@@ -2651,6 +2835,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000091 ", "MSRValue": "0x013c000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2663,6 +2848,7 @@ ...@@ -2663,6 +2848,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand & prefetch data reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000091 ", "MSRValue": "0x023c000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2675,6 +2861,7 @@ ...@@ -2675,6 +2861,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000091 ", "MSRValue": "0x043c000091 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2687,6 +2874,7 @@ ...@@ -2687,6 +2874,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2000020122 ", "MSRValue": "0x2000020122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2699,6 +2887,7 @@ ...@@ -2699,6 +2887,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x20003c0122 ", "MSRValue": "0x20003c0122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2711,6 +2900,7 @@ ...@@ -2711,6 +2900,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0084000122 ", "MSRValue": "0x0084000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2723,6 +2913,7 @@ ...@@ -2723,6 +2913,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0104000122 ", "MSRValue": "0x0104000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2735,6 +2926,7 @@ ...@@ -2735,6 +2926,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0204000122 ", "MSRValue": "0x0204000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2747,6 +2939,7 @@ ...@@ -2747,6 +2939,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x0404000122 ", "MSRValue": "0x0404000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2759,6 +2952,7 @@ ...@@ -2759,6 +2952,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x1004000122 ", "MSRValue": "0x1004000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2771,6 +2965,7 @@ ...@@ -2771,6 +2965,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004000122 ", "MSRValue": "0x2004000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2783,6 +2978,7 @@ ...@@ -2783,6 +2978,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x3f84000122 ", "MSRValue": "0x3f84000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2795,6 +2991,7 @@ ...@@ -2795,6 +2991,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x00bc000122 ", "MSRValue": "0x00bc000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2807,6 +3004,7 @@ ...@@ -2807,6 +3004,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x013c000122 ", "MSRValue": "0x013c000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2819,6 +3017,7 @@ ...@@ -2819,6 +3017,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x023c000122 ", "MSRValue": "0x023c000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -2831,6 +3030,7 @@ ...@@ -2831,6 +3030,7 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"MSRValue": "0x043c000122 ", "MSRValue": "0x043c000122 ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
......
tools/perf/pmu-events/arch/x86/broadwell/other.json
View file @ b3ab8adc
...@@ -9,16 +9,6 @@ ...@@ -9,16 +9,6 @@
"BriefDescription": "Unhalted core cycles when the thread is in ring 0", "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
"EventCode": "0x5C", "EventCode": "0x5C",
...@@ -31,6 +21,16 @@ ...@@ -31,6 +21,16 @@
"CounterMask": "1", "CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
"EventCode": "0x63", "EventCode": "0x63",
......
tools/perf/pmu-events/arch/x86/broadwell/pipeline.json
View file @ b3ab8adc
...@@ -2,32 +2,42 @@ ...@@ -2,32 +2,42 @@
{ {
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"EventCode": "0x00", "EventCode": "0x00",
"Counter": "Fixed counter 1", "Counter": "Fixed counter 0",
"UMask": "0x1", "UMask": "0x1",
"EventName": "INST_RETIRED.ANY", "EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Instructions retired from execution.", "BriefDescription": "Instructions retired from execution.",
"CounterHTOff": "Fixed counter 1" "CounterHTOff": "Fixed counter 0"
}, },
{ {
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"EventCode": "0x00", "EventCode": "0x00",
"Counter": "Fixed counter 2", "Counter": "Fixed counter 1",
"UMask": "0x2", "UMask": "0x2",
"EventName": "CPU_CLK_UNHALTED.THREAD", "EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when the thread is not in halt state", "BriefDescription": "Core cycles when the thread is not in halt state",
"CounterHTOff": "Fixed counter 2" "CounterHTOff": "Fixed counter 1"
},
{
"EventCode": "0x00",
"Counter": "Fixed counter 1",
"UMask": "0x2",
"AnyThread": "1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"CounterHTOff": "Fixed counter 1"
}, },
{ {
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"EventCode": "0x00", "EventCode": "0x00",
"Counter": "Fixed counter 3", "Counter": "Fixed counter 2",
"UMask": "0x3", "UMask": "0x3",
"EventName": "CPU_CLK_UNHALTED.REF_TSC", "EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the core is not in halt state.", "BriefDescription": "Reference cycles when the core is not in halt state.",
"CounterHTOff": "Fixed counter 3" "CounterHTOff": "Fixed counter 2"
}, },
{ {
"PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
...@@ -59,26 +69,37 @@ ...@@ -59,26 +69,37 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.",
"EventCode": "0x0D", "EventCode": "0x0D",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "UMask": "0x3",
"EventName": "INT_MISC.RAT_STALL_CYCLES", "EventName": "INT_MISC.RECOVERY_CYCLES",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.",
"EventCode": "0x0D", "EventCode": "0x0D",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x3", "UMask": "0x3",
"EventName": "INT_MISC.RECOVERY_CYCLES", "AnyThread": "1",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)", "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
"CounterMask": "1", "CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
"EventCode": "0x0D",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "INT_MISC.RAT_STALL_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
"EventCode": "0x0E", "EventCode": "0x0E",
...@@ -89,6 +110,18 @@ ...@@ -89,6 +110,18 @@
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
"EventCode": "0x0E",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
},
{ {
"PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
"EventCode": "0x0E", "EventCode": "0x0E",
...@@ -117,18 +150,6 @@ ...@@ -117,18 +150,6 @@
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
"EventCode": "0x0E",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
},
{ {
"PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
"EventCode": "0x14", "EventCode": "0x14",
...@@ -139,6 +160,26 @@ ...@@ -139,6 +160,26 @@
"BriefDescription": "Cycles when divider is busy executing divide operations", "BriefDescription": "Cycles when divider is busy executing divide operations",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
"EventCode": "0x3C",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Thread cycles when thread is not in halt state",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x3C",
"Counter": "0,1,2,3",
"UMask": "0x0",
"AnyThread": "1",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
"EventCode": "0x3C", "EventCode": "0x3C",
...@@ -149,6 +190,36 @@ ...@@ -149,6 +190,36 @@
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"EventCode": "0x3C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"AnyThread": "1",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
"EventCode": "0x3C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x3C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"AnyThread": "1",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"EventCode": "0x3c", "EventCode": "0x3c",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -158,6 +229,15 @@ ...@@ -158,6 +229,15 @@
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{
"EventCode": "0x3C",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
"EventCode": "0x4c", "EventCode": "0x4c",
...@@ -224,6 +304,18 @@ ...@@ -224,6 +304,18 @@
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"EventCode": "0x5E",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EdgeDetect": "1",
"EventName": "RS_EVENTS.EMPTY_END",
"SampleAfterValue": "200003",
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
"EventCode": "0x87", "EventCode": "0x87",
...@@ -404,6 +496,15 @@ ...@@ -404,6 +496,15 @@
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0xa0",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
"EventCode": "0x89", "EventCode": "0x89",
...@@ -434,6 +535,16 @@ ...@@ -434,6 +535,16 @@
"BriefDescription": "Speculative and retired mispredicted macro conditional branches", "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",
"EventCode": "0xA0",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
"SampleAfterValue": "2000003",
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
"CounterHTOff": "0,1,2,3"
},
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
"EventCode": "0xA1", "EventCode": "0xA1",
...@@ -445,602 +556,472 @@ ...@@ -445,602 +556,472 @@
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
"EventCode": "0xA1", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1", "AnyThread": "1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are executed in port 1", "BriefDescription": "Cycles per core when uops are exectuted in port 0.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
"EventCode": "0xA1", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2", "EventName": "UOPS_EXECUTED_PORT.PORT_0",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are executed in port 2", "BriefDescription": "Cycles per thread when uops are executed in port 0",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
"EventCode": "0xA1", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "UMask": "0x2",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3", "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are executed in port 3", "BriefDescription": "Cycles per thread when uops are executed in port 1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
"EventCode": "0xA1", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "UMask": "0x2",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4", "AnyThread": "1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are executed in port 4", "BriefDescription": "Cycles per core when uops are exectuted in port 1.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
"EventCode": "0xA1", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "UMask": "0x2",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5", "EventName": "UOPS_EXECUTED_PORT.PORT_1",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are executed in port 5", "BriefDescription": "Cycles per thread when uops are executed in port 1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
"EventCode": "0xA1", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x40", "UMask": "0x4",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6", "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are executed in port 6", "BriefDescription": "Cycles per thread when uops are executed in port 2",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
"EventCode": "0xA1", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x80", "UMask": "0x4",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7", "AnyThread": "1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are executed in port 7", "BriefDescription": "Cycles per core when uops are dispatched to port 2.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
"EventCode": "0xA2", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x4",
"EventName": "RESOURCE_STALLS.ANY", "EventName": "UOPS_EXECUTED_PORT.PORT_2",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Resource-related stall cycles", "BriefDescription": "Cycles per thread when uops are executed in port 2",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
"EventCode": "0xA2", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x8",
"EventName": "RESOURCE_STALLS.RS", "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles stalled due to no eligible RS entry available.", "BriefDescription": "Cycles per thread when uops are executed in port 3",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", "EventCode": "0xA1",
"EventCode": "0xA2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "UMask": "0x8",
"EventName": "RESOURCE_STALLS.SB", "AnyThread": "1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
"EventCode": "0xA2", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "UMask": "0x8",
"EventName": "RESOURCE_STALLS.ROB", "EventName": "UOPS_EXECUTED_PORT.PORT_3",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles stalled due to re-order buffer full.", "BriefDescription": "Cycles per thread when uops are executed in port 3",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
"EventCode": "0xA3", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x10",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.",
"EventCode": "0xA3",
"Counter": "2",
"UMask": "0x8",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", "BriefDescription": "Cycles per thread when uops are executed in port 4",
"CounterMask": "8", "CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "2"
}, },
{ {
"PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", "EventCode": "0xA1",
"EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x10",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", "AnyThread": "1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles while memory subsystem has an outstanding load.", "BriefDescription": "Cycles per core when uops are exectuted in port 4.",
"CounterMask": "2",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "Counts number of cycles nothing is executed on any execution port.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
"EventCode": "0xA3", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x10",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", "EventName": "UOPS_EXECUTED_PORT.PORT_4",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Total execution stalls", "BriefDescription": "Cycles per thread when uops are executed in port 4",
"CounterMask": "4", "CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
"EventCode": "0xA3", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x5", "UMask": "0x20",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", "BriefDescription": "Cycles per thread when uops are executed in port 5",
"CounterMask": "5", "CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", "EventCode": "0xA1",
"EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x6", "UMask": "0x20",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", "AnyThread": "1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", "BriefDescription": "Cycles per core when uops are exectuted in port 5.",
"CounterMask": "6", "CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
"EventCode": "0xA3", "EventCode": "0xA1",
"Counter": "2", "Counter": "0,1,2,3",
"UMask": "0xc", "UMask": "0x20",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", "EventName": "UOPS_EXECUTED_PORT.PORT_5",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", "BriefDescription": "Cycles per thread when uops are executed in port 5",
"CounterMask": "12", "CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "2"
}, },
{ {
"PublicDescription": "Number of Uops delivered by the LSD. ", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
"EventCode": "0xA8", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x40",
"EventName": "LSD.UOPS", "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of Uops delivered by the LSD.", "BriefDescription": "Cycles per thread when uops are executed in port 6",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "Number of uops to be executed per-thread each cycle.", "EventCode": "0xA1",
"EventCode": "0xB1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x40",
"EventName": "UOPS_EXECUTED.THREAD", "AnyThread": "1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", "BriefDescription": "Cycles per core when uops are exectuted in port 6.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "Number of uops executed from any thread.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
"EventCode": "0xB1", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x40",
"EventName": "UOPS_EXECUTED.CORE", "EventName": "UOPS_EXECUTED_PORT.PORT_6",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of uops executed on the core.", "BriefDescription": "Cycles per thread when uops are executed in port 6",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
"EventCode": "0xB1", "EventCode": "0xA1",
"Invert": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x80",
"EventName": "UOPS_EXECUTED.STALL_CYCLES", "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", "BriefDescription": "Cycles per thread when uops are executed in port 7",
"CounterMask": "1", "CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", "EventCode": "0xA1",
"EventCode": "0xC0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x0", "UMask": "0x80",
"Errata": "BDM61", "AnyThread": "1",
"EventName": "INST_RETIRED.ANY_P", "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of instructions retired. General Counter - architectural event", "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
"EventCode": "0xC0", "EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x80",
"EventName": "INST_RETIRED.X87", "EventName": "UOPS_EXECUTED_PORT.PORT_7",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", "BriefDescription": "Cycles per thread when uops are executed in port 7",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PEBS": "2", "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", "EventCode": "0xA2",
"EventCode": "0xC0", "Counter": "0,1,2,3",
"Counter": "1",
"UMask": "0x1", "UMask": "0x1",
"Errata": "BDM11, BDM55", "EventName": "RESOURCE_STALLS.ANY",
"EventName": "INST_RETIRED.PREC_DIST",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", "BriefDescription": "Resource-related stall cycles",
"CounterHTOff": "1" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xC1", "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
"EventCode": "0xA2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x40", "UMask": "0x4",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", "EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "100003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PEBS": "1", "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
"PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", "EventCode": "0xA2",
"EventCode": "0xC2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x8",
"EventName": "UOPS_RETIRED.ALL", "EventName": "RESOURCE_STALLS.SB",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Actually retired uops.", "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7"
"Data_LA": "1"
}, },
{ {
"PEBS": "1", "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used.", "EventCode": "0xA2",
"EventCode": "0xC2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x10",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS", "EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Retirement slots used.", "BriefDescription": "Cycles stalled due to re-order buffer full.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.", "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.",
"EventCode": "0xC2", "EventCode": "0xA3",
"Invert": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x1",
"EventName": "UOPS_RETIRED.STALL_CYCLES", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles without actually retired uops.", "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
"CounterMask": "1", "CounterMask": "1",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", "EventCode": "0xA3",
"EventCode": "0xC2",
"Invert": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x1",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles with less than 10 actually retired uops.", "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
"CounterMask": "10", "CounterMask": "1",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).",
"EventCode": "0xC3", "EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x2",
"EventName": "MACHINE_CLEARS.CYCLES", "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
"CounterMask": "2",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", "EventCode": "0xA3",
"EventCode": "0xC3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x2",
"EventName": "MACHINE_CLEARS.SMC", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
"SampleAfterValue": "100003", "SampleAfterValue": "2000003",
"BriefDescription": "Self-modifying code (SMC) detected.", "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterMask": "2",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", "PublicDescription": "Counts number of cycles nothing is executed on any execution port.",
"EventCode": "0xC3", "EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "UMask": "0x4",
"EventName": "MACHINE_CLEARS.MASKMOV", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
"SampleAfterValue": "100003", "SampleAfterValue": "2000003",
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterMask": "4",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"PEBS": "1", "EventCode": "0xA3",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"SampleAfterValue": "400009",
"BriefDescription": "Conditional branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "1",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"SampleAfterValue": "100007",
"BriefDescription": "Direct and indirect near call instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts all (macro) branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009",
"BriefDescription": "All (macro) branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "1",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"SampleAfterValue": "100007",
"BriefDescription": "Return instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"SampleAfterValue": "400009",
"BriefDescription": "Not taken branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "1",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"SampleAfterValue": "400009",
"BriefDescription": "Taken branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x40",
"Errata": "BDW98",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"SampleAfterValue": "100007",
"BriefDescription": "Far branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "2",
"PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x4",
"Errata": "BDW98", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", "SampleAfterValue": "2000003",
"SampleAfterValue": "400009", "BriefDescription": "Total execution stalls.",
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", "CounterMask": "4",
"CounterHTOff": "0,1,2,3"
},
{
"PEBS": "1",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired.",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"SampleAfterValue": "400009",
"BriefDescription": "Mispredicted conditional branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009",
"BriefDescription": "All mispredicted macro branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "1",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "BR_MISP_RETIRED.RET",
"SampleAfterValue": "100007",
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PEBS": "2", "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.",
"PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", "EventCode": "0xA3",
"EventCode": "0xC5",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
"SampleAfterValue": "400009", "SampleAfterValue": "2000003",
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
"CounterMask": "5",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", "EventCode": "0xA3",
"EventCode": "0xCC",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "UMask": "0x5",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Count cases of saving new LBR", "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
"CounterMask": "5",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.",
"EventCode": "0x3C", "EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x0", "UMask": "0x6",
"EventName": "CPU_CLK_UNHALTED.THREAD_P", "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Thread cycles when thread is not in halt state", "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterMask": "6",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0x89", "EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xa0", "UMask": "0x6",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
"SampleAfterValue": "200003", "SampleAfterValue": "2000003",
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.", "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
"CounterMask": "6",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA1", "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.",
"Counter": "0,1,2,3", "EventCode": "0xA3",
"UMask": "0x1", "Counter": "2",
"AnyThread": "1", "UMask": "0x8",
"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are exectuted in port 0.", "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterMask": "8",
"CounterHTOff": "2"
}, },
{ {
"EventCode": "0xA1", "EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "2",
"UMask": "0x2", "UMask": "0x8",
"AnyThread": "1", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are exectuted in port 1.", "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterMask": "8",
"CounterHTOff": "2"
}, },
{ {
"EventCode": "0xA1", "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.",
"Counter": "0,1,2,3", "EventCode": "0xA3",
"UMask": "0x4", "Counter": "2",
"AnyThread": "1", "UMask": "0xc",
"EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are dispatched to port 2.", "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterMask": "12",
"CounterHTOff": "2"
}, },
{ {
"EventCode": "0xA1", "EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "2",
"UMask": "0x8", "UMask": "0xc",
"AnyThread": "1", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
"EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are dispatched to port 3.", "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterMask": "12",
"CounterHTOff": "2"
}, },
{ {
"EventCode": "0xA1", "EventCode": "0xA8",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "UMask": "0x1",
"AnyThread": "1", "EventName": "LSD.UOPS",
"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are exectuted in port 4.", "BriefDescription": "Number of Uops delivered by the LSD.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA1", "EventCode": "0xA8",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "UMask": "0x1",
"AnyThread": "1", "EventName": "LSD.CYCLES_4_UOPS",
"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are exectuted in port 5.", "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA1", "EventCode": "0xA8",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x40", "UMask": "0x1",
"AnyThread": "1", "EventName": "LSD.CYCLES_ACTIVE",
"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are exectuted in port 6.", "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA1", "PublicDescription": "Number of uops to be executed per-thread each cycle.",
"EventCode": "0xB1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x80", "UMask": "0x1",
"AnyThread": "1", "EventName": "UOPS_EXECUTED.THREAD",
"EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are dispatched to port 7.", "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PEBS": "1", "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
"PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", "EventCode": "0xB1",
"EventCode": "0xC5", "Invert": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "UMask": "0x1",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "EventName": "UOPS_EXECUTED.STALL_CYCLES",
"SampleAfterValue": "400009", "SampleAfterValue": "2000003",
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterMask": "1",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xB1", "EventCode": "0xB1",
...@@ -1083,335 +1064,364 @@ ...@@ -1083,335 +1064,364 @@
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xe6", "PublicDescription": "Number of uops executed from any thread.",
"EventCode": "0xB1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1f", "UMask": "0x2",
"EventName": "BACLEARS.ANY", "EventName": "UOPS_EXECUTED.CORE",
"SampleAfterValue": "100003", "SampleAfterValue": "2000003",
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "BriefDescription": "Number of uops executed on the core.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA3", "EventCode": "0xb1",
"Counter": "2", "Counter": "0,1,2,3",
"UMask": "0x8", "UMask": "0x2",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
"CounterMask": "8", "CounterMask": "1",
"CounterHTOff": "2" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA3", "EventCode": "0xb1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x2",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
"CounterMask": "1", "CounterMask": "2",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA3", "EventCode": "0xb1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x2",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles while memory subsystem has an outstanding load.", "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
"CounterMask": "2", "CounterMask": "3",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA3", "EventCode": "0xb1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x2",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Total execution stalls.", "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
"CounterMask": "4", "CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA3", "EventCode": "0xb1",
"Counter": "2", "Invert": "1",
"UMask": "0xc", "Counter": "0,1,2,3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "UMask": "0x2",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
"CounterMask": "12", "CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "2"
}, },
{ {
"EventCode": "0xA3", "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).",
"EventCode": "0xC0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x5", "UMask": "0x0",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "Errata": "BDM61",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", "BriefDescription": "Number of instructions retired. General Counter - architectural event",
"CounterMask": "5",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA3", "PEBS": "2",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.",
"EventCode": "0xC0",
"Counter": "1",
"UMask": "0x1",
"Errata": "BDM11, BDM55",
"EventName": "INST_RETIRED.PREC_DIST",
"SampleAfterValue": "2000003",
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
"CounterHTOff": "1"
},
{
"PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
"EventCode": "0xC0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x6", "UMask": "0x2",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "EventName": "INST_RETIRED.X87",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:",
"CounterMask": "6",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xC3", "EventCode": "0xC1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x40",
"EdgeDetect": "1", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"EventName": "MACHINE_CLEARS.COUNT",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Number of machine clears (nukes) of any type.", "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xA8", "PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.",
"EventCode": "0xC2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x1",
"EventName": "LSD.CYCLES_4_UOPS", "EventName": "UOPS_RETIRED.ALL",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", "BriefDescription": "Actually retired uops. (Precise Event - PEBS)",
"CounterMask": "4", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterHTOff": "0,1,2,3,4,5,6,7" "Data_LA": "1"
}, },
{ {
"EventCode": "0x5E", "PublicDescription": "This event counts cycles without actually retired uops.",
"EventCode": "0xC2",
"Invert": "1", "Invert": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x1",
"EdgeDetect": "1", "EventName": "UOPS_RETIRED.STALL_CYCLES",
"EventName": "RS_EVENTS.EMPTY_END",
"SampleAfterValue": "200003",
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xA8",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LSD.CYCLES_ACTIVE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", "BriefDescription": "Cycles without actually retired uops.",
"CounterMask": "1", "CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
"EventCode": "0xA1", "EventCode": "0xC2",
"Invert": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0", "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are executed in port 0", "BriefDescription": "Cycles with less than 10 actually retired uops.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterMask": "10",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", "PEBS": "1",
"EventCode": "0xA1", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used.",
"EventCode": "0xC2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x2",
"EventName": "UOPS_EXECUTED_PORT.PORT_1", "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are executed in port 1", "BriefDescription": "Retirement slots used. (Precise Event - PEBS)",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
"EventCode": "0xA1", "EventCode": "0xC3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "UMask": "0x1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2", "EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are executed in port 2", "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", "EventCode": "0xC3",
"EventCode": "0xA1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "UMask": "0x1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3", "EdgeDetect": "1",
"SampleAfterValue": "2000003", "EventName": "MACHINE_CLEARS.COUNT",
"BriefDescription": "Cycles per thread when uops are executed in port 3", "SampleAfterValue": "100003",
"BriefDescription": "Number of machine clears (nukes) of any type.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
"EventCode": "0xA1", "EventCode": "0xC3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "UMask": "0x4",
"EventName": "UOPS_EXECUTED_PORT.PORT_4", "EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Cycles per thread when uops are executed in port 4", "BriefDescription": "Self-modifying code (SMC) detected.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
"EventCode": "0xA1", "EventCode": "0xC3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "UMask": "0x20",
"EventName": "UOPS_EXECUTED_PORT.PORT_5", "EventName": "MACHINE_CLEARS.MASKMOV",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Cycles per thread when uops are executed in port 5", "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", "PublicDescription": "This event counts all (macro) branch instructions retired.",
"EventCode": "0xA1", "EventCode": "0xC4",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x40", "UMask": "0x0",
"EventName": "UOPS_EXECUTED_PORT.PORT_6", "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009",
"BriefDescription": "Cycles per thread when uops are executed in port 6", "BriefDescription": "All (macro) branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", "PEBS": "1",
"EventCode": "0xA1", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x80", "UMask": "0x1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7", "EventName": "BR_INST_RETIRED.CONDITIONAL",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009",
"BriefDescription": "Cycles per thread when uops are executed in port 7", "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", "PEBS": "1",
"EventCode": "0xA0", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x3", "UMask": "0x2",
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", "EventName": "BR_INST_RETIRED.NEAR_CALL",
"SampleAfterValue": "2000003", "SampleAfterValue": "100007",
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0x00", "PEBS": "1",
"Counter": "Fixed counter 2", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x2",
"AnyThread": "1", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "100007",
"SampleAfterValue": "2000003", "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", "CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "Fixed counter 2"
}, },
{ {
"EventCode": "0x3C", "PEBS": "2",
"PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x0", "UMask": "0x4",
"AnyThread": "1", "Errata": "BDW98",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0x3C", "PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x8",
"AnyThread": "1", "EventName": "BR_INST_RETIRED.NEAR_RETURN",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "100007",
"SampleAfterValue": "2000003", "BriefDescription": "Return instructions retired. (Precise Event - PEBS)",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0x0D", "PublicDescription": "This event counts not taken branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x3", "UMask": "0x10",
"AnyThread": "1", "EventName": "BR_INST_RETIRED.NOT_TAKEN",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "400009",
"SampleAfterValue": "2000003", "BriefDescription": "Not taken branch instructions retired.",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xb1", "PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x20",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009",
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xb1", "PublicDescription": "This event counts far branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x40",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "Errata": "BDW98",
"SampleAfterValue": "2000003", "EventName": "BR_INST_RETIRED.FAR_BRANCH",
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", "SampleAfterValue": "100007",
"CounterMask": "2", "BriefDescription": "Far branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xb1", "PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
"EventCode": "0xC5",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x0",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009",
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", "BriefDescription": "All mispredicted macro branch instructions retired.",
"CounterMask": "3",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xb1", "PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.",
"EventCode": "0xC5",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "EventName": "BR_MISP_RETIRED.CONDITIONAL",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009",
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0xb1", "PEBS": "2",
"Invert": "1", "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.",
"EventCode": "0xC5",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x4",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009",
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
"CounterHTOff": "0,1,2,3"
},
{
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired.",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "BR_MISP_RETIRED.RET",
"SampleAfterValue": "100007",
"BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", "PEBS": "1",
"EventCode": "0x3C", "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
"EventCode": "0xC5",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x20",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009",
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0x3C", "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
"EventCode": "0xCC",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "UMask": "0x20",
"AnyThread": "1", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "BriefDescription": "Count cases of saving new LBR",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{ {
"EventCode": "0x3C", "EventCode": "0xe6",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "UMask": "0x1f",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "EventName": "BACLEARS.ANY",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json
View file @ b3ab8adc
...@@ -43,6 +43,16 @@ ...@@ -43,6 +43,16 @@
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0xe",
"Errata": "BDM69",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
"EventCode": "0x08", "EventCode": "0x08",
...@@ -72,6 +82,15 @@ ...@@ -72,6 +82,15 @@
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x60",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
"EventCode": "0x49", "EventCode": "0x49",
...@@ -116,6 +135,16 @@ ...@@ -116,6 +135,16 @@
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0xe",
"Errata": "BDM69",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
"EventCode": "0x49", "EventCode": "0x49",
...@@ -145,6 +174,15 @@ ...@@ -145,6 +174,15 @@
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x60",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
"EventCode": "0x4F", "EventCode": "0x4F",
...@@ -199,6 +237,16 @@ ...@@ -199,6 +237,16 @@
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0xe",
"Errata": "BDM69",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
"EventCode": "0x85", "EventCode": "0x85",
...@@ -228,6 +276,15 @@ ...@@ -228,6 +276,15 @@
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
}, },
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x60",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{ {
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
"EventCode": "0xAE", "EventCode": "0xAE",
...@@ -251,61 +308,61 @@ ...@@ -251,61 +308,61 @@
{ {
"EventCode": "0xBC", "EventCode": "0xBC",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x21", "UMask": "0x12",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1", "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.", "BriefDescription": "Number of DTLB page walker hits in the L2.",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xBC", "EventCode": "0xBC",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x12", "UMask": "0x14",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2", "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of DTLB page walker hits in the L2.", "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xBC", "EventCode": "0xBC",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x22", "UMask": "0x18",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of ITLB page walker hits in the L2.", "BriefDescription": "Number of DTLB page walker hits in Memory.",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xBC", "EventCode": "0xBC",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x14", "UMask": "0x21",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3", "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", "BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xBC", "EventCode": "0xBC",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x24", "UMask": "0x22",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3", "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", "BriefDescription": "Number of ITLB page walker hits in the L2.",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xBC", "EventCode": "0xBC",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x18", "UMask": "0x24",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of DTLB page walker hits in Memory.", "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
"CounterHTOff": "0,1,2,3" "CounterHTOff": "0,1,2,3"
}, },
{ {
...@@ -327,62 +384,5 @@ ...@@ -327,62 +384,5 @@
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "STLB flush attempts", "BriefDescription": "STLB flush attempts",
"CounterHTOff": "0,1,2,3,4,5,6,7" "CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0xe",
"Errata": "BDM69",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x60",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0xe",
"Errata": "BDM69",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x60",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0xe",
"Errata": "BDM69",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x60",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
} }
] ]
\ No newline at end of file
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