Skip to content

L
linux
Commit b3d42bf1 authored by Xenia Ragiadakou's avatar Xenia Ragiadakou Committed by Greg Kroah-Hartman
Browse files
Options

staging: rtl8192u: fix read_nic_* functions 

read_nic_*() functions are defined in r8192U_core.c.
They call internally usb_control_msg() to read the
nic registers and return the value read.
Following a remark made by Dan Carpenter, if usb_control_msg()
fails, the value returned will be invalid.

To accommodate for this, this patch changes the functions
to take a pointer as argument to set the value read and
return 0 on success and the error status on failure, so
that callers of read_nic_*() can check the return status.

Some other fixes introduced in read_nic_*() functions are:

The expressions (1<<EPROM_*_SHIFT) used to address and set
the individual bits of the eeprom register were replaced
with EPROM_*_BIT bitmasks to make the code more intuitive.
EPROM_*_BIT bitmasks were defined in r8192U_hw.h and
EPROM_*_SHIFT were removed.

In netdev_err(), which is called in case of failure,
the hardcoded function name in the error log message was
replaced with __func__ to reduce line size.
Also, from the error log message, it was omitted the word
"Timeout" and it is just reported the error code since the
failure can not only be due to timeout expiration but also
due to a memory allocation failure. In case of timeout
expiration, usb_start_wait_urb() prints an appropriate log
message when debug is enabled.

Finally, some minor fixes to the coding style were applied in
lines affected by the above changes, including the removal
of ifdef DEBUG_RX (the debugging of reads and writes of the
nic registers shall be done with explicit check on their
return status which will be added in a follow on patch).
Signed-off-by: default avatarXenia Ragiadakou <burzalodowa@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c2ac90b9
Expand all Show whitespace changes
Inline Side-by-side
Showing with 172 additions and 139 deletions
drivers/staging/rtl8192u/r8180_93cx6.c
View file @ b3d42bf1
......@@ -22,13 +22,15 @@
void eprom_cs(struct net_device *dev, short bit)
{
u8 cmdreg;
read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
if (bit)
write_nic_byte_E(dev, EPROM_CMD,
(1<<EPROM_CS_SHIFT) | \
read_nic_byte_E(dev, EPROM_CMD)); //enable EPROM
/* enable EPROM */
write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_CS_BIT);
else
write_nic_byte_E(dev, EPROM_CMD, read_nic_byte_E(dev, EPROM_CMD)\
& ~(1<<EPROM_CS_SHIFT)); //disable EPROM
/* disable EPROM */
write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_CS_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
......@@ -37,12 +39,15 @@ void eprom_cs(struct net_device *dev, short bit)
void eprom_ck_cycle(struct net_device *dev)
{
write_nic_byte_E(dev, EPROM_CMD,
(1<<EPROM_CK_SHIFT) | read_nic_byte_E(dev,EPROM_CMD));
u8 cmdreg;
read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_CK_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
write_nic_byte_E(dev, EPROM_CMD,
read_nic_byte_E(dev, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT));
read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_CK_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
}
......@@ -50,12 +55,13 @@ void eprom_ck_cycle(struct net_device *dev)
void eprom_w(struct net_device *dev,short bit)
{
u8 cmdreg;
read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
if (bit)
write_nic_byte_E(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) | \
read_nic_byte_E(dev,EPROM_CMD));
write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_W_BIT);
else
write_nic_byte_E(dev, EPROM_CMD, read_nic_byte_E(dev,EPROM_CMD)\
& ~(1<<EPROM_W_SHIFT));
write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_W_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
......@@ -64,12 +70,14 @@ void eprom_w(struct net_device *dev,short bit)
short eprom_r(struct net_device *dev)
{
short bit;
u8 bit;
bit=(read_nic_byte_E(dev, EPROM_CMD) & (1<<EPROM_R_SHIFT) );
read_nic_byte_E(dev, EPROM_CMD, &bit);
udelay(EPROM_DELAY);
if (bit) return 1;
if (bit & EPROM_R_BIT)
return 1;
return 0;
}
......
drivers/staging/rtl8192u/r8192U.h
View file @ b3d42bf1
......@@ -1205,10 +1205,10 @@ short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
u32 read_cam(struct net_device *dev, u8 addr);
void write_cam(struct net_device *dev, u8 addr, u32 data);
u8 read_nic_byte(struct net_device *dev, int x);
u8 read_nic_byte_E(struct net_device *dev, int x);
u32 read_nic_dword(struct net_device *dev, int x);
u16 read_nic_word(struct net_device *dev, int x) ;
int read_nic_byte(struct net_device *dev, int x, u8 *data);
int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
int read_nic_dword(struct net_device *dev, int x, u32 *data);
int read_nic_word(struct net_device *dev, int x, u16 *data);
void write_nic_byte(struct net_device *dev, int x,u8 y);
void write_nic_byte_E(struct net_device *dev, int x,u8 y);
void write_nic_word(struct net_device *dev, int x,u16 y);
......
drivers/staging/rtl8192u/r8192U_core.c
View file @ b3d42bf1
This diff is collapsed.
drivers/staging/rtl8192u/r8192U_dm.c
View file @ b3d42bf1
......@@ -480,7 +480,7 @@ static void dm_check_rate_adaptive(struct net_device *dev)
//
// Check whether updating of RATR0 is required
//
currentRATR = read_nic_dword(dev, RATR0);
read_nic_dword(dev, RATR0, &currentRATR);
if(targetRATR != currentRATR)
{
u32 ratr_value;
......@@ -634,7 +634,7 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
//DbgPrint("hi, vivi, strange\n");
for(i = 0;i <= 30; i++)
{
Pwr_Flag = read_nic_byte(dev, 0x1ba);
read_nic_byte(dev, 0x1ba, &Pwr_Flag);
if (Pwr_Flag == 0)
{
......@@ -642,9 +642,9 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
continue;
}
#ifdef RTL8190P
Avg_TSSI_Meas = read_nic_word(dev, 0x1bc);
read_nic_word(dev, 0x1bc, &Avg_TSSI_Meas);
#else
Avg_TSSI_Meas = read_nic_word(dev, 0x13c);
read_nic_word(dev, 0x13c, &Avg_TSSI_Meas);
#endif
if(Avg_TSSI_Meas == 0)
{
......@@ -655,12 +655,12 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
for(k = 0;k < 5; k++)
{
#ifdef RTL8190P
tmp_report[k] = read_nic_byte(dev, 0x1d8+k);
read_nic_byte(dev, 0x1d8+k, &tmp_report[k]);
#else
if(k !=4)
tmp_report[k] = read_nic_byte(dev, 0x134+k);
read_nic_byte(dev, 0x134+k, &tmp_report[k]);
else
tmp_report[k] = read_nic_byte(dev, 0x13e);
read_nic_byte(dev, 0x13e, &tmp_report[k]);
#endif
RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
}
......@@ -2397,6 +2397,7 @@ static void dm_initial_gain(
u8 initial_gain=0;
static u8 initialized, force_write;
static u32 reset_cnt;
u8 tmp;
if(dm_digtable.dig_algorithm_switch)
{
......@@ -2437,7 +2438,8 @@ static void dm_initial_gain(
reset_cnt = priv->reset_count;
}
if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1))
read_nic_byte(dev, rOFDM0_XAAGCCore1, &tmp);
if (dm_digtable.pre_ig_value != tmp)
force_write = 1;
{
......@@ -2727,7 +2729,8 @@ static void dm_check_edca_turbo(
// TODO: Modified this part and try to set acm control in only 1 IO processing!!
PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
u8 AcmCtrl = read_nic_byte(dev, AcmHwCtrl);
u8 AcmCtrl;
read_nic_byte(dev, AcmHwCtrl, &AcmCtrl);
if(pAciAifsn->f.ACM)
{ // ACM bit is 1.
AcmCtrl |= AcmHw_BeqEn;
......@@ -2881,7 +2884,7 @@ static void dm_check_pbc_gpio(struct net_device *dev)
u8 tmp1byte;
tmp1byte = read_nic_byte(dev,GPI);
read_nic_byte(dev, GPI, &tmp1byte);
if(tmp1byte == 0xff)
return;
......@@ -2933,7 +2936,7 @@ extern void dm_gpio_change_rf_callback(struct work_struct *work)
{
// 0x108 GPIO input register is read only
//set 0x108 B1= 1: RF-ON; 0: RF-OFF.
tmp1byte = read_nic_byte(dev,GPI);
read_nic_byte(dev, GPI, &tmp1byte);
eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff;
......@@ -2996,7 +2999,7 @@ extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
/* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
always be the same. We only read 0xc04 now. */
rfpath = read_nic_byte(dev, 0xc04);
read_nic_byte(dev, 0xc04, &rfpath);
// Check Bit 0-3, it means if RF A-D is enabled.
for (i = 0; i < RF90_PATH_MAX; i++)
......@@ -3052,12 +3055,13 @@ static void dm_rxpath_sel_byrssi(struct net_device *dev)
if(!cck_Rx_Path_initialized)
{
DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf);
read_nic_byte(dev, 0xa07, &DM_RxPathSelTable.cck_Rx_path);
DM_RxPathSelTable.cck_Rx_path &= 0xf;
cck_Rx_Path_initialized = 1;
}
DM_RxPathSelTable.disabledRF = 0xf;
DM_RxPathSelTable.disabledRF &= ~(read_nic_byte(dev, 0xc04));
read_nic_byte(dev, 0xc04, &DM_RxPathSelTable.disabledRF);
DM_RxPathSelTable.disabledRF = ~DM_RxPathSelTable.disabledRF & 0xf;
if(priv->ieee80211->mode == WIRELESS_MODE_B)
{
......@@ -3731,17 +3735,17 @@ extern void dm_shadow_init(struct net_device *dev)
for (page = 0; page < 5; page++)
for (offset = 0; offset < 256; offset++)
{
dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
//DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);
}
for (page = 8; page < 11; page++)
for (offset = 0; offset < 256; offset++)
dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
for (page = 12; page < 15; page++)
for (offset = 0; offset < 256; offset++)
dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
} /* dm_shadow_init */
......@@ -3858,14 +3862,14 @@ static void dm_check_txrateandretrycount(struct net_device *dev)
struct ieee80211_device *ieee = priv->ieee80211;
//for 11n tx rate
// priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
read_nic_byte(dev, Current_Tx_Rate_Reg, &ieee->softmac_stats.CurrentShowTxate);
//printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);
//for initial tx rate
// priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);
ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg);
read_nic_byte(dev, Initial_Tx_Rate_Reg, &ieee->softmac_stats.last_packet_rate);
//for tx tx retry count
// priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
read_nic_dword(dev, Tx_Retry_Count_Reg, &ieee->softmac_stats.txretrycount);
}
static void dm_send_rssi_tofw(struct net_device *dev)
......
drivers/staging/rtl8192u/r8192U_hw.h
View file @ b3d42bf1
......@@ -388,10 +388,11 @@ enum _RTL8192Usb_HW {
#define EPROM_CMD_NORMAL 0
#define EPROM_CMD_LOAD 1
#define EPROM_CMD_PROGRAM 2
#define EPROM_CS_SHIFT 3
#define EPROM_CK_SHIFT 2
#define EPROM_W_SHIFT 1
#define EPROM_R_SHIFT 0
#define EPROM_CS_BIT BIT(3)
#define EPROM_CK_BIT BIT(2)
#define EPROM_W_BIT BIT(1)
#define EPROM_R_BIT BIT(0)
MAC0 = 0x000,
MAC1 = 0x001,
MAC2 = 0x002,
......
drivers/staging/rtl8192u/r8192U_wx.c
View file @ b3d42bf1
......@@ -235,7 +235,7 @@ static int r8192_wx_read_nicb(struct net_device *dev,
down(&priv->wx_sem);
get_user(addr,(u32 *)wrqu->data.pointer);
data1 = read_nic_byte(dev, addr);
read_nic_byte(dev, addr, &data1);
wrqu->data.length = data1;
up(&priv->wx_sem);
......
drivers/staging/rtl8192u/r819xU_firmware.c
View file @ b3d42bf1
......@@ -168,7 +168,7 @@ bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
/* Check whether put code OK */
do {
CPU_status = read_nic_dword(dev, CPU_GEN);
read_nic_dword(dev, CPU_GEN, &CPU_status);
if (CPU_status&CPU_GEN_PUT_CODE_OK)
break;
......@@ -183,13 +183,13 @@ bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
}
/* Turn On CPU */
CPU_status = read_nic_dword(dev, CPU_GEN);
read_nic_dword(dev, CPU_GEN, &CPU_status);
write_nic_byte(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff));
mdelay(1000);
/* Check whether CPU boot OK */
do {
CPU_status = read_nic_dword(dev, CPU_GEN);
read_nic_dword(dev, CPU_GEN, &CPU_status);
if (CPU_status&CPU_GEN_BOOT_RDY)
break;
......@@ -218,7 +218,7 @@ bool CPUcheck_firmware_ready(struct net_device *dev)
/* Check Firmware Ready */
do {
CPU_status = read_nic_dword(dev, CPU_GEN);
read_nic_dword(dev, CPU_GEN, &CPU_status);
if (CPU_status&CPU_GEN_FIRM_RDY)
break;
......
drivers/staging/rtl8192u/r819xU_phy.c
View file @ b3d42bf1
......@@ -90,7 +90,7 @@ void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, u32
if(dwBitMask!= bMaskDWord)
{//if not "double word" write
OriginalValue = read_nic_dword(dev, dwRegAddr);
read_nic_dword(dev, dwRegAddr, &OriginalValue);
BitShift = rtl8192_CalculateBitShift(dwBitMask);
NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
write_nic_dword(dev, dwRegAddr, NewValue);
......@@ -111,7 +111,7 @@ u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
{
u32 Ret = 0, OriginalValue, BitShift;
OriginalValue = read_nic_dword(dev, dwRegAddr);
read_nic_dword(dev, dwRegAddr, &OriginalValue);
BitShift = rtl8192_CalculateBitShift(dwBitMask);
Ret =(OriginalValue & dwBitMask) >> BitShift;
......@@ -379,6 +379,7 @@ phy_FwRFSerialRead(
u32 retValue = 0;
u32 Data = 0;
u8 time = 0;
u32 tmp;
//DbgPrint("FW RF CTRL\n\r");
/* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
not execute the scheme in the initial step. Otherwise, RF-R/W will waste
......@@ -394,13 +395,15 @@ phy_FwRFSerialRead(
// 5. Trigger Fw to operate the command. bit 31
Data |= 0x80000000;
// 6. We can not execute read operation if bit 31 is 1.
while (read_nic_dword(dev, QPNR)&0x80000000)
read_nic_dword(dev, QPNR, &tmp);
while (tmp & 0x80000000)
{
// If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100)
{
//DbgPrint("FW not finish RF-R Time=%d\n\r", time);
udelay(10);
read_nic_dword(dev, QPNR, &tmp);
}
else
break;
......@@ -408,18 +411,20 @@ phy_FwRFSerialRead(
// 7. Execute read operation.
write_nic_dword(dev, QPNR, Data);
// 8. Check if firmawre send back RF content.
while (read_nic_dword(dev, QPNR)&0x80000000)
read_nic_dword(dev, QPNR, &tmp);
while (tmp & 0x80000000)
{
// If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100)
{
//DbgPrint("FW not finish RF-W Time=%d\n\r", time);
udelay(10);
read_nic_dword(dev, QPNR, &tmp);
}
else
return (0);
}
retValue = read_nic_dword(dev, RF_DATA);
read_nic_dword(dev, RF_DATA, &retValue);
return (retValue);
......@@ -440,6 +445,7 @@ phy_FwRFSerialWrite(
u32 Data )
{
u8 time = 0;
u32 tmp;
//DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
/* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
......@@ -458,13 +464,15 @@ phy_FwRFSerialWrite(
Data |= 0x80000000;
// 6. Write operation. We can not write if bit 31 is 1.
while (read_nic_dword(dev, QPNR)&0x80000000)
read_nic_dword(dev, QPNR, &tmp);
while (tmp & 0x80000000)
{
// If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100)
{
//DbgPrint("FW not finish RF-W Time=%d\n\r", time);
udelay(10);
read_nic_dword(dev, QPNR, &tmp);
}
else
break;
......@@ -719,7 +727,7 @@ u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, RF9
case HW90_BLOCK_PHY0:
case HW90_BLOCK_PHY1:
write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
read_nic_dword(dev, WriteAddr[CheckBlock], &dwRegRead);
break;
case HW90_BLOCK_RF:
......@@ -770,11 +778,11 @@ void rtl8192_BB_Config_ParaFile(struct net_device *dev)
**************************************/
/*--set BB Global Reset--*/
bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
read_nic_byte(dev, BB_GLOBAL_RESET, &bRegValue);
write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
mdelay(50);
/*---set BB reset Active---*/
dwRegValue = read_nic_dword(dev, CPU_GEN);
read_nic_dword(dev, CPU_GEN, &dwRegValue);
write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
/*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
......@@ -795,7 +803,7 @@ void rtl8192_BB_Config_ParaFile(struct net_device *dev)
rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
/*----Set BB reset de-Active----*/
dwRegValue = read_nic_dword(dev, CPU_GEN);
read_nic_dword(dev, CPU_GEN, &dwRegValue);
write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
/*----BB AGC table Initialization----*/
......@@ -846,36 +854,32 @@ void rtl8192_BBConfig(struct net_device *dev)
void rtl8192_phy_getTxPower(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
priv->MCSTxPowerLevelOriginalOffset[0] =
read_nic_dword(dev, rTxAGC_Rate18_06);
priv->MCSTxPowerLevelOriginalOffset[1] =
read_nic_dword(dev, rTxAGC_Rate54_24);
priv->MCSTxPowerLevelOriginalOffset[2] =
read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
priv->MCSTxPowerLevelOriginalOffset[3] =
read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
priv->MCSTxPowerLevelOriginalOffset[4] =
read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
priv->MCSTxPowerLevelOriginalOffset[5] =
read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
u8 tmp;
read_nic_dword(dev, rTxAGC_Rate18_06, &priv->MCSTxPowerLevelOriginalOffset[0]);
read_nic_dword(dev, rTxAGC_Rate54_24, &priv->MCSTxPowerLevelOriginalOffset[1]);
read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, &priv->MCSTxPowerLevelOriginalOffset[2]);
read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, &priv->MCSTxPowerLevelOriginalOffset[3]);
read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, &priv->MCSTxPowerLevelOriginalOffset[4]);
read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, &priv->MCSTxPowerLevelOriginalOffset[5]);
// read rx initial gain
priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
// read framesync
priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
priv->framesyncC34 = read_nic_byte(dev, rOFDM0_RxDetector2);
read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
priv->framesyncC34 = tmp;
RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
rOFDM0_RxDetector3, priv->framesync);
// read SIFS (save the value read fome MACPHY_REG.txt)
priv->SifsTime = read_nic_word(dev, SIFS);
read_nic_word(dev, SIFS, &priv->SifsTime);
return;
}
......@@ -1525,7 +1529,7 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
}
//<1>Set MAC register
regBwOpMode = read_nic_byte(dev, BW_OPMODE);
read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
switch (priv->CurrentChannelBW)
{
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7