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Commit b4e1bce8 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "Core changes:

   - NONE whatsoever, we don't even touch the core files this time
     around.

  New drivers:

   - New driver for the Toshiba Visconti SoC.

   - New subdriver for the Qualcomm MSM8226 SoC.

   - New subdriver for the Actions Semiconductor S500 SoC.

   - New subdriver for the Mediatek MT8192 SoC.

   - New subdriver for the Microchip SAMA7G5 SoC.

  Driver enhancements:

   - Intel Cherryview and Baytrail cleanups and refactorings.

   - Enhanced support for the Renesas R8A7790, more pins and groups.

   - Some optimizations for the MCP23S08 MCP23x17 variant.

   - Some cleanups around the Actions Semiconductor subdrivers.

   - A bunch of cleanups around the SH-PFC and Emma Mobile drivers.

   - The "SH-PFC" (literally SuperH pin function controller, I think)
     subdirectory is now renamed to the more neutral "renesas", as these
     are not very much centered around SuperH anymore.

   - Non-critical fixes for the Aspeed driver.

   - Non-critical fixes for the Ingenic (MIPS!) driver.

   - Fix a bunch of missing pins on the AMD pinctrl driver"

* tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (78 commits)
  pinctrl: amd: Add missing pins to the pin group list
  dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks
  pinctrl: visconti: PINCTRL_TMPV7700 should depend on ARCH_VISCONTI
  pinctrl: mediatek: Free eint data on failure
  pinctrl: single: fix debug output when #pinctrl-cells = 2
  pinctrl: single: fix pinctrl_spec.args_count bounds check
  pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent
  pinctrl: cannonlake: Modify COMMUNITY macros to be consistent
  pinctrl: tigerlake: Fix register offsets for TGL-H variant
  pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2
  pinctrl: mediatek: use devm_platform_ioremap_resource_byname()
  pinctrl: nuvoton: npcm7xx: Constify static ops structs
  pinctrl: mediatek: mt7622: add antsel pins/groups
  pinctrl: ocelot: simplify the return expression of ocelot_gpiochip_register()
  pinctrl: at91-pio4: add support for sama7g5 SoC
  dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5
  pinctrl: spear: simplify the return expression of tvc_connect()
  pinctrl: spear: simplify the return expression of spear310_pinctrl_probe
  pinctrl: sprd: use module_platform_driver to simplify the code
  pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs.
  ...
parents 7fafb54c 55596c54
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Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml 0 → 100644
View file @ b4e1bce8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Actions Semi S500 SoC pinmux & GPIO controller
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
description: |
Pinmux & GPIO controller manages pin multiplexing & configuration including
GPIO function selection & GPIO attributes configuration. Please refer to
pinctrl-bindings.txt in this directory for common binding part and usage.
properties:
compatible:
const: actions,s500-pinctrl
reg:
items:
- description: GPIO Output + GPIO Input + GPIO Data
- description: Multiplexing Control
- description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control
- description: PAD Drive Capacity Select
minItems: 1
maxItems: 4
clocks:
maxItems: 1
gpio-controller: true
gpio-ranges:
maxItems: 1
'#gpio-cells':
description:
Specifies the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
interrupt-controller: true
'#interrupt-cells':
description:
Specifies the pin number and flags, as defined in
include/dt-bindings/interrupt-controller/irq.h
const: 2
interrupts:
description:
One interrupt per each of the 5 GPIO ports supported by the controller,
sorted by port number ascending order.
minItems: 5
maxItems: 5
patternProperties:
'-pins$':
type: object
patternProperties:
'^(.*-)?pinmux$':
type: object
description:
Pinctrl node's client devices specify pin muxes using subnodes,
which in turn use the standard properties below.
$ref: pinmux-node.yaml#
properties:
groups:
description:
List of gpio pin groups affected by the functions specified in
this subnode.
items:
oneOf:
- enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp,
rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp, rmii_rxd1_mfp,
rmii_rxd0_mfp, rmii_ref_clk_mfp, i2s_d0_mfp, i2s_pcm1_mfp,
i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp,
ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp,
ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
dsi_dp2_mfp, lcd0_d17_mfp, dsi_dp3_mfp, dsi_dn3_mfp,
dsi_dp0_mfp, lvds_ee_pn_mfp, spi0_i2c_pcm_mfp,
spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp, lvds_e_pn_mfp,
dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp,
uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp,
pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp,
dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp,
nand_ceb3_mfp]
minItems: 1
maxItems: 32
function:
description:
Specify the alternative function to be configured for the
given gpio pin groups.
enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0,
i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m,
mipi_csi, nand, spdif, ts, lcd0]
required:
- groups
- function
additionalProperties: false
'^(.*-)?pinconf$':
type: object
description:
Pinctrl node's client devices specify pin configurations using
subnodes, which in turn use the standard properties below.
$ref: pincfg-node.yaml#
properties:
groups:
description:
List of gpio pin groups affected by the drive-strength property
specified in this subnode.
items:
oneOf:
- enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv,
rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv,
smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv,
i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv,
lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv,
sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv,
spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv,
i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv,
sens0_ckout_drv, uart3_all_drv]
minItems: 1
maxItems: 32
pins:
description:
List of gpio pins affected by the bias-pull-* and
input-schmitt-* properties specified in this subnode.
items:
oneOf:
- enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen,
eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk,
eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1,
i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1,
ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep,
lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp,
lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3,
dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0,
dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0,
sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk,
sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1,
dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx, uart2_rtsb,
uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb,
pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, i2c1_sclk,
i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0,
csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2, dnand_d3,
dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_rb, dnand_rdb,
dnand_rdbn, dnand_wrb, porb, clko_25m, bsel, pkg0, pkg1,
pkg2, pkg3]
minItems: 1
maxItems: 64
bias-pull-up: true
bias-pull-down: true
drive-strength:
description:
Selects the drive strength for the specified pins, in mA.
enum: [2, 4, 8, 12]
input-schmitt-enable: true
input-schmitt-disable: true
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
- clocks
- gpio-controller
- gpio-ranges
- '#gpio-cells'
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl: pinctrl@b01b0000 {
compatible = "actions,s500-pinctrl";
reg = <0xb01b0000 0x40>, <0xb01b0040 0x10>,
<0xb01b0060 0x18>, <0xb01b0080 0xc>;
clocks = <&cmu 55>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 132>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
mmc0_pins: mmc0-pins {
pinmux {
groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
"sd0_cmd_mfp", "sd0_clk_mfp";
function = "sd0";
};
drv-pinconf {
groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
drive-strength = <8>;
};
bias-pinconf {
pins = "sd0_d0", "sd0_d1", "sd0_d2",
"sd0_d3", "sd0_cmd";
bias-pull-up;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
View file @ b4e1bce8
......@@ -48,6 +48,8 @@ properties:
- allwinner,sun9i-a80-r-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-a64-r-pinctrl
- allwinner,sun50i-a100-pinctrl
- allwinner,sun50i-a100-r-pinctrl
- allwinner,sun50i-h5-pinctrl
- allwinner,sun50i-h6-pinctrl
- allwinner,sun50i-h6-r-pinctrl
......@@ -59,7 +61,7 @@ properties:
interrupts:
minItems: 1
maxItems: 5
maxItems: 7
description:
One interrupt per external interrupt bank supported on the
controller, sorted by bank number ascending order.
......@@ -143,6 +145,18 @@ allOf:
# boards are defining it at the moment so it would generate a lot of
# warnings.
- if:
properties:
compatible:
enum:
- allwinner,sun50i-a100-pinctrl
then:
properties:
interrupts:
minItems: 7
maxItems: 7
- if:
properties:
compatible:
......@@ -155,8 +169,7 @@ allOf:
minItems: 5
maxItems: 5
else:
if:
- if:
properties:
compatible:
enum:
......@@ -170,8 +183,7 @@ allOf:
minItems: 4
maxItems: 4
else:
if:
- if:
properties:
compatible:
enum:
......@@ -187,8 +199,7 @@ allOf:
minItems: 3
maxItems: 3
else:
if:
- if:
properties:
compatible:
enum:
......@@ -206,7 +217,23 @@ allOf:
minItems: 2
maxItems: 2
else:
- if:
properties:
compatible:
enum:
- allwinner,sun4i-a10-pinctrl
- allwinner,sun5i-a10s-pinctrl
- allwinner,sun5i-a13-pinctrl
- allwinner,sun7i-a20-pinctrl
- allwinner,sun8i-a23-r-pinctrl
- allwinner,sun8i-a83t-r-pinctrl
- allwinner,sun8i-h3-r-pinctrl
- allwinner,sun8i-r40-pinctrl
- allwinner,sun50i-a64-r-pinctrl
- allwinner,sun50i-a100-r-pinctrl
- nextthing,gr8-pinctrl
then:
properties:
interrupts:
minItems: 1
......
Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
View file @ b4e1bce8
......@@ -4,7 +4,9 @@ The Atmel PIO4 controller is used to select the function of a pin and to
configure it.
Required properties:
- compatible: "atmel,sama5d2-pinctrl".
- compatible:
"atmel,sama5d2-pinctrl"
"microchip,sama7g5-pinctrl"
- reg: base address and length of the PIO controller.
- interrupts: interrupt outputs from the controller, one for each bank.
- interrupt-controller: mark the device node as an interrupt controller.
......
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
View file @ b4e1bce8
......@@ -10,6 +10,7 @@ Required properties:
"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
"mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
......
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml 0 → 100644
View file @ b4e1bce8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT8192 Pin Controller
maintainers:
- Sean Wang <sean.wang@mediatek.com>
description: |
The Mediatek's Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8192-pinctrl
gpio-controller: true
'#gpio-cells':
description: |
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
const: 2
gpio-ranges:
description: gpio valid number range.
maxItems: 1
reg:
description: |
Physical address base for gpio base registers. There are 11 GPIO
physical address base in mt8192.
maxItems: 11
reg-names:
description: |
Gpio base register names.
maxItems: 11
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
description: The interrupt outputs to sysirq.
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'^pins':
type: object
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and
input schmitt.
An example of using macro:
pincontroller {
/* GPIO0 set as multifunction GPIO0 */
state_0_node_a {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
};
/* GPIO1 set as multifunction PWM */
state_0_node_b {
pinmux = <PINMUX_GPIO1__FUNC_PWM_1>;
};
};
$ref: "pinmux-node.yaml"
properties:
pinmux:
description: |
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
drive-strength:
description: |
It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
enum: [2, 4, 6, 8, 10, 12, 14, 16]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pio: pinctrl@10005000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0x10005000 0x1000>,
<0x11c20000 0x1000>,
<0x11d10000 0x1000>,
<0x11d30000 0x1000>,
<0x11d40000 0x1000>,
<0x11e20000 0x1000>,
<0x11e70000 0x1000>,
<0x11ea0000 0x1000>,
<0x11f20000 0x1000>,
<0x11f30000 0x1000>,
<0x1000b000 0x1000>;
reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
"iocfg_bl", "iocfg_br", "iocfg_lm",
"iocfg_lb", "iocfg_rt", "iocfg_lt",
"iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 220>;
interrupt-controller;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
pins {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
output-low;
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
View file @ b4e1bce8
......@@ -94,16 +94,23 @@ pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.
The pin configuration nodes for pinctrl-single are specified as pinctrl
register offset and value pairs using pinctrl-single,pins. Only the bits
specified in pinctrl-single,function-mask are updated. For example, setting
a pin for a device could be done with:
register offset and values using pinctrl-single,pins. Only the bits specified
in pinctrl-single,function-mask are updated.
When #pinctrl-cells = 1, then setting a pin for a device could be done with:
pinctrl-single,pins = <0xdc 0x118>;
Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, and 0x118 contains the desired value of the
pinctrl register. See the device example and static board pins example
below for more information.
Where 0xdc is the offset from the pinctrl register base address for the device
pinctrl register, and 0x118 contains the desired value of the pinctrl register.
When #pinctrl-cells = 2, then setting a pin for a device could be done with:
pinctrl-single,pins = <0xdc 0x30 0x07>;
Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value.
These two values are OR'd together to produce the value stored at offset 0xdc.
See the device example and static board pins example below for more information.
In case when one register changes more than one pin's mux the
pinctrl-single,bits need to be used which takes three parameters:
......
Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml 0 → 100644
View file @ b4e1bce8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. MSM8226 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
MSM8226 platform.
properties:
compatible:
const: qcom,msm8226-pinctrl
reg:
description: Specifies the base address and size of the TLMM register space
maxItems: 1
interrupts:
description: Specifies the TLMM summary IRQ
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
description: Specifies the PIN numbers and Flags, as defined in
include/dt-bindings/interrupt-controller/irq.h
const: 2
gpio-controller: true
'#gpio-cells':
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
gpio-reserved-ranges:
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins. Functions are only valid for gpio pins.
enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1,
blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ]
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
msmgpio: pinctrl@fd510000 {
compatible = "qcom,msm8226-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&msmgpio 0 0 117>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
serial-pins {
pins = "gpio8", "gpio9";
function = "blsp_uart3";
drive-strength = <8>;
bias-disable;
};
};
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt deleted 100644 → 0
View file @ 7fafb54c
* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,
R8A73A4 and R8A7740 it also acts as a GPIO controller.
Pin Control
-----------
Required Properties:
- compatible: should be one of the following.
- "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller.
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
- "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
- "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller.
- "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
- "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
- "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller.
- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller.
- "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller.
- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
- "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
- "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible pin-controller.
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
controller hardware module.
Optional properties:
- #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden
otherwise. Should be 3.
- interrupts-extended: Specify the interrupts associated with external
IRQ pins. This property is mandatory when the PFC handles GPIOs and
forbidden otherwise. When specified, it must contain one interrupt per
external IRQ, sorted by external IRQ number.
The PFC node also acts as a container for pin configuration nodes. Please refer
to pinctrl-bindings.txt in this directory for the definition of the term "pin
configuration node" and for the common pinctrl bindings used by client devices.
Each pin configuration node represents a desired configuration for a pin, a
pin group, or a list of pins or pin groups. The configuration can include the
function to select on those pin(s) and pin configuration parameters (such as
pull-up and pull-down).
Pin configuration nodes contain pin configuration properties, either directly
or grouped in child subnodes. Both pin muxing and configuration parameters can
be grouped in that way and referenced as a single pin configuration node by
client devices.
A configuration node or subnode must reference at least one pin (through the
pins or pin groups properties) and contain at least a function or one
configuration parameter. When the function is present only pin groups can be
used to reference pins.
All pin configuration nodes and subnodes names are ignored. All of those nodes
are parsed through phandles and processed purely based on their content.
Pin Configuration Node Properties:
- pins : An array of strings, each string containing the name of a pin.
- groups : An array of strings, each string containing the name of a pin
group.
- function: A string containing the name of the function to mux to the pin
group(s) specified by the groups property.
Valid values for pin, group and function names can be found in the group and
function arrays of the PFC data file corresponding to the SoC
(drivers/pinctrl/sh-pfc/pfc-*.c)
The pin configuration parameters use the generic pinconf bindings defined in
pinctrl-bindings.txt in this directory. The supported parameters are
bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For
pins that have a configurable I/O voltage, the power-source value should be the
nominal I/O voltage in millivolts.
GPIO
----
On SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller node.
Required Properties:
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
The syntax of the gpio specifier used by client nodes should be the following
with values derived from the SoC user manual.
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[flags]>
On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.
Please refer to Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
for documentation of the GPIO device tree bindings on those platforms.
Examples
--------
Example 1: SH73A0 (SH-Mobile AG5) pin controller node
pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;
gpio-controller;
#gpio-cells = <2>;
interrupts-extended =
<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
};
Example 2: A GPIO LED node that references a GPIO
#include <dt-bindings/gpio/gpio.h>
leds {
compatible = "gpio-leds";
led1 {
gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
};
};
Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
for the MMCIF and SCIFA4 devices
&pfc {
pinctrl-0 = <&scifa4_pins>;
pinctrl-names = "default";
mmcif_pins: mmcif {
mux {
groups = "mmc0_data8_0", "mmc0_ctrl_0";
function = "mmc0";
};
cfg {
groups = "mmc0_data8_0";
pins = "PORT279";
bias-pull-up;
};
};
scifa4_pins: scifa4 {
groups = "scifa4_data", "scifa4_ctrl";
function = "scifa4";
};
};
Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
&mmcif {
pinctrl-0 = <&mmcif_pins>;
pinctrl-names = "default";
bus-width = <8>;
vmmc-supply = <&reg_1p8v>;
};
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml 0 → 100644
View file @ b4e1bce8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Pin Function Controller (GPIO and Pin Mux/Config)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The Pin Function Controller (PFC) is a Pin Mux/Config controller.
On SH/R-Mobile SoCs it also acts as a GPIO controller.
properties:
compatible:
enum:
- renesas,pfc-emev2 # EMMA Mobile EV2
- renesas,pfc-r8a73a4 # R-Mobile APE6
- renesas,pfc-r8a7740 # R-Mobile A1
- renesas,pfc-r8a7742 # RZ/G1H
- renesas,pfc-r8a7743 # RZ/G1M
- renesas,pfc-r8a7744 # RZ/G1N
- renesas,pfc-r8a7745 # RZ/G1E
- renesas,pfc-r8a77470 # RZ/G1C
- renesas,pfc-r8a774a1 # RZ/G2M
- renesas,pfc-r8a774b1 # RZ/G2N
- renesas,pfc-r8a774c0 # RZ/G2E
- renesas,pfc-r8a774e1 # RZ/G2H
- renesas,pfc-r8a7778 # R-Car M1
- renesas,pfc-r8a7779 # R-Car H1
- renesas,pfc-r8a7790 # R-Car H2
- renesas,pfc-r8a7791 # R-Car M2-W
- renesas,pfc-r8a7792 # R-Car V2H
- renesas,pfc-r8a7793 # R-Car M2-N
- renesas,pfc-r8a7794 # R-Car E2
- renesas,pfc-r8a7795 # R-Car H3
- renesas,pfc-r8a7796 # R-Car M3-W
- renesas,pfc-r8a77961 # R-Car M3-W+
- renesas,pfc-r8a77965 # R-Car M3-N
- renesas,pfc-r8a77970 # R-Car V3M
- renesas,pfc-r8a77980 # R-Car V3H
- renesas,pfc-r8a77990 # R-Car E3
- renesas,pfc-r8a77995 # R-Car D3
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:
minItems: 1
maxItems: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
minItems: 1
maxItems: 16
interrupts-extended:
minItems: 32
maxItems: 64
description:
Specify the interrupts associated with external IRQ pins on SoCs where
the PFC acts as a GPIO controller. It must contain one interrupt per
external IRQ, sorted by external IRQ number.
power-domains:
maxItems: 1
required:
- compatible
- reg
if:
properties:
compatible:
items:
enum:
- renesas,pfc-r8a73a4
- renesas,pfc-r8a7740
- renesas,pfc-sh73a0
then:
required:
- interrupts-extended
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- power-domains
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
Client device subnodes use below standard properties.
properties:
phandle: true
function: true
groups: true
pins: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength:
enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values
power-source:
enum: [ 1800, 3300 ]
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
additionalProperties: false
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
examples:
- |
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a7740";
reg = <0xe6050000 0x8000>,
<0xe605800c 0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 0 212>;
interrupts-extended =
<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
power-domains = <&pd_c5>;
lcd0-mux-hog {
/* DBGMD/LCDC0/FSIA MUX */
gpio-hog;
gpios = <176 0>;
output-high;
};
};
- |
pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7795";
reg = <0xe6060000 0x50c>;
avb_pins: avb {
mux {
groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb";
};
pins_mdio {
groups = "avb_mdio";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC",
"PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2",
"PIN_AVB_TD3";
drive-strength = <12>;
};
};
keys_pins: keys {
pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1";
bias-pull-up;
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
};
Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt deleted 100644 → 0
View file @ 7fafb54c
Renesas RZ/A1 combined Pin and GPIO controller
The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
named "Ports" in the hardware reference manual.
Pin multiplexing and GPIO configuration is performed on a per-pin basis
writing configuration values to per-port register sets.
Each "port" features up to 16 pins, each of them configurable for GPIO
function (port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
Pin controller node
-------------------
Required properties:
- compatible: should be:
- "renesas,r7s72100-ports": for RZ/A1H
- "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
- "renesas,r7s72102-ports": for RZ/A1L
- reg
address base and length of the memory area where the pin controller
hardware is mapped to.
Example:
Pin controller node for RZ/A1H SoC (r7s72100)
pinctrl: pin-controller@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
};
Sub-nodes
---------
The child nodes of the pin controller node describe a pin multiplexing
function or a GPIO controller alternatively.
- Pin multiplexing sub-nodes:
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
A few alternate function require special pin configuration flags to be
supplied along with the alternate function configuration number.
The hardware reference manual specifies when a pin function requires
"software IO driven" mode to be specified. To do so use the generic
properties from the <include/linux/pinctrl/pinconf_generic.h> header file
to instruct the pin controller to perform the desired pin configuration
operation.
Please refer to pinctrl-bindings.txt to get to know more on generic
pin properties usage.
The allowed generic formats for a pin multiplexing sub-node are the
following ones:
node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
node-2 {
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
sub-node-2 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
Use the second format when pins part of the same logical group need to have
different generic pin configuration flags applied.
Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
of the most external one.
Eg.
client-1 {
...
pinctrl-0 = <&node-1>;
...
};
client-2 {
...
pinctrl-0 = <&node-2>;
...
};
Required properties:
- pinmux:
integer array representing pin number and pin multiplexing configuration.
When a pin has to be configured in alternate function mode, use this
property to identify the pin by its global index, and provide its
alternate function configuration number along with it.
When multiple pins are required to be configured as part of the same
alternate function they shall be specified as members of the same
argument list of a single "pinmux" property.
Helper macros to ease assembling the pin index from its position
(port where it sits on and pin number) and alternate function identifier
are provided by the pin controller header file at:
<include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
Integers values in "pinmux" argument list are assembled as:
((PORT * 16 + PIN) | MUX_FUNC << 16)
Optional generic properties:
- input-enable:
enable input bufer for pins requiring software driven IO input
operations.
- output-high:
enable output buffer for pins requiring software driven IO output
operations. output-low can be used alternatively, as line value is
ignored by the driver.
The hardware reference manual specifies when a pin has to be configured to
work in bi-directional mode and when the IO direction has to be specified
by software. Bi-directional pins are managed by the pin controller driver
internally, while software driven IO direction has to be explicitly
selected when multiple options are available.
Example:
A serial communication interface with a TX output pin and an RX input pin.
&pinctrl {
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
};
Pin #0 on port #3 is configured as alternate function #6.
Pin #2 on port #3 is configured as alternate function #4.
Example 2:
I2c master: both SDA and SCL pins need bi-directional operations
&pinctrl {
i2c2_pins: i2c2 {
pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
};
};
Pin #4 on port #1 is configured as alternate function #1.
Pin #5 on port #1 is configured as alternate function #1.
Both need to work in bi-directional mode, the driver manages this internally.
Example 3:
Multi-function timer input and output compare pins.
Configure TIOC0A as software driven input and TIOC0B as software driven
output.
&pinctrl {
tioc0_pins: tioc0 {
tioc0_input_pins {
pinumx = <RZA1_PINMUX(4, 0, 2)>;
input-enable;
};
tioc0_output_pins {
pinmux = <RZA1_PINMUX(4, 1, 1)>;
output-enable;
};
};
};
&tioc0 {
...
pinctrl-0 = <&tioc0_pins>;
...
};
Pin #0 on port #4 is configured as alternate function #2 with IO direction
specified by software as input.
Pin #1 on port #4 is configured as alternate function #1 with IO direction
specified by software as output.
- GPIO controller sub-nodes:
Each port of the r7s72100 pin controller hardware is itself a GPIO controller.
Different SoCs have different numbers of available pins per port, but
generally speaking, each of them can be configured in GPIO ("port") mode
on this hardware.
Describe GPIO controllers using sub-nodes with the following properties.
Required properties:
- gpio-controller
empty property as defined by the GPIO bindings documentation.
- #gpio-cells
number of cells required to identify and configure a GPIO.
Shall be 2.
- gpio-ranges
Describes a GPIO controller specifying its specific pin base, the pin
base in the global pin numbering space, and the number of controlled
pins, as defined by the GPIO bindings documentation. Refer to
Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed
description.
Example:
A GPIO controller node, controlling 16 pins indexed from 0.
The GPIO controller base in the global pin indexing space is pin 48, thus
pins [0 - 15] on this controller map to pins [48 - 63] in the global pin
indexing space.
port3: gpio-3 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
};
A device node willing to use pins controlled by this GPIO controller, shall
refer to it as follows:
led1 {
gpios = <&port3 10 GPIO_ACTIVE_LOW>;
};
Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml 0 → 100644
View file @ b4e1bce8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/A1 combined Pin and GPIO controller
maintainers:
- Jacopo Mondi <jacopo+renesas@jmondi.org>
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
controller, named "Ports" in the hardware reference manual.
Pin multiplexing and GPIO configuration is performed on a per-pin basis
writing configuration values to per-port register sets.
Each "port" features up to 16 pins, each of them configurable for GPIO
function (port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
properties:
compatible:
oneOf:
- const: renesas,r7s72100-ports # RZ/A1H
- items:
- const: renesas,r7s72101-ports # RZ/A1M
- const: renesas,r7s72100-ports # fallback
- const: renesas,r7s72102-ports # RZ/A1L
reg:
maxItems: 1
required:
- compatible
- reg
patternProperties:
"^gpio-[0-9]*$":
type: object
description:
Each port of the r7s72100 pin controller hardware is itself a GPIO
controller.
Different SoCs have different numbers of available pins per port, but
generally speaking, each of them can be configured in GPIO ("port") mode
on this hardware.
Describe GPIO controllers using sub-nodes with the following properties.
properties:
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
maxItems: 1
required:
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
A pin multiplexing sub-node describes how to configure a set of (or a
single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
A few alternate function require special pin configuration flags to be
supplied along with the alternate function configuration number.
The hardware reference manual specifies when a pin function requires
"software IO driven" mode to be specified. To do so use the generic
properties from the <include/linux/pinctrl/pinconf_generic.h> header
file to instruct the pin controller to perform the desired pin
configuration operation.
The hardware reference manual specifies when a pin has to be configured
to work in bi-directional mode and when the IO direction has to be
specified by software. Bi-directional pins must be managed by the pin
controller driver internally, while software driven IO direction has to
be explicitly selected when multiple options are available.
properties:
pinmux:
description: |
Integer array representing pin number and pin multiplexing
configuration.
When a pin has to be configured in alternate function mode, use
this property to identify the pin by its global index, and provide
its alternate function configuration number along with it.
When multiple pins are required to be configured as part of the
same alternate function they shall be specified as members of the
same argument list of a single "pinmux" property.
Helper macros to ease assembling the pin index from its position
(port where it sits on and pin number) and alternate function
identifier are provided by the pin controller header file at:
<include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
Integers values in "pinmux" argument list are assembled as:
((PORT * 16 + PIN) | MUX_FUNC << 16)
phandle: true
input-enable: true
output-enable: true
required:
- pinmux
additionalProperties: false
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
examples:
- |
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
/*
* A GPIO controller node, controlling 16 pins indexed from 0.
* The GPIO controller base in the global pin indexing space is pin
* 48, thus pins [0 - 15] on this controller map to pins [48 - 63]
* in the global pin indexing space.
*/
port3: gpio-3 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
};
/*
* A serial communication interface with a TX output pin and an RX
* input pin.
* Pin #0 on port #3 is configured as alternate function #6.
* Pin #2 on port #3 is configured as alternate function #4.
*/
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
/*
* I2c master: both SDA and SCL pins need bi-directional operations
* Pin #4 on port #1 is configured as alternate function #1.
* Pin #5 on port #1 is configured as alternate function #1.
* Both need to work in bi-directional mode, the driver must manage
* this internally.
*/
i2c2_pins: i2c2 {
pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
};
/*
* Multi-function timer input and output compare pins.
*/
tioc0_pins: tioc0 {
/*
* Configure TIOC0A as software driven input
* Pin #0 on port #4 is configured as alternate function #2
* with IO direction specified by software as input.
*/
tioc0_input_pins {
pinmux = <RZA1_PINMUX(4, 0, 2)>;
input-enable;
};
/*
* Configure TIOC0B as software driven output
* Pin #1 on port #4 is configured as alternate function #1
* with IO direction specified by software as output.
*/
tioc0_output_pins {
pinmux = <RZA1_PINMUX(4, 1, 1)>;
output-enable;
};
};
};
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml
View file @ b4e1bce8
......@@ -84,7 +84,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
pinctrl: pin-controller@fcffe000 {
pinctrl: pinctrl@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;
......
Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt deleted 100644 → 0
View file @ 7fafb54c
Renesas RZ/N1 SoC Pinctrl node description.
Pin controller node
-------------------
Required properties:
- compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl"
followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible
strings must be one of:
"renesas,r9a06g032-pinctrl" for RZ/N1D
"renesas,r9a06g033-pinctrl" for RZ/N1S
- reg: Address base and length of the memory area where the pin controller
hardware is mapped to.
- clocks: phandle for the clock, see the description of clock-names below.
- clock-names: Contains the name of the clock:
"bus", the bus clock, sometimes described as pclk, for register accesses.
Example:
pinctrl: pin-controller@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
clock-names = "bus";
};
Sub-nodes
---------
The child nodes of the pin controller node describe a pin multiplexing
function.
- Pin multiplexing sub-nodes:
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
Please refer to pinctrl-bindings.txt to get to know more on generic
pin properties usage.
The allowed generic formats for a pin multiplexing sub-node are the
following ones:
node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
node-2 {
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
sub-node-2 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
node-3 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
Use the latter two formats when pins part of the same logical group need to
have different generic pin configuration flags applied. Note that the generic
pinconfig in node-3 does not apply to the sub-nodes.
Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
of the most external one.
Eg.
client-1 {
...
pinctrl-0 = <&node-1>;
...
};
client-2 {
...
pinctrl-0 = <&node-2>;
...
};
Required properties:
- pinmux:
integer array representing pin number and pin multiplexing configuration.
When a pin has to be configured in alternate function mode, use this
property to identify the pin by its global index, and provide its
alternate function configuration number along with it.
When multiple pins are required to be configured as part of the same
alternate function they shall be specified as members of the same
argument list of a single "pinmux" property.
Integers values in the "pinmux" argument list are assembled as:
(PIN | MUX_FUNC << 8)
where PIN directly corresponds to the pl_gpio pin number and MUX_FUNC is
one of the alternate function identifiers defined in:
<include/dt-bindings/pinctrl/rzn1-pinctrl.h>
These identifiers collapse the IO Multiplex Configuration Level 1 and
Level 2 numbers that are detailed in the hardware reference manual into a
single number. The identifiers for Level 2 are simply offset by 10.
Additional identifiers are provided to specify the MDIO source peripheral.
Optional generic pinconf properties:
- bias-disable - disable any pin bias
- bias-pull-up - pull up the pin with 50 KOhm
- bias-pull-down - pull down the pin with 50 KOhm
- bias-high-impedance - high impedance mode
- drive-strength - sink or source at most 4, 6, 8 or 12 mA
Example:
A serial communication interface with a TX output pin and an RX input pin.
&pinctrl {
pins_uart0: pins_uart0 {
pinmux = <
RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
>;
};
};
Example 2:
Here we set the pull up on the RXD pin of the UART.
&pinctrl {
pins_uart0: pins_uart0 {
pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>; /* TXD */
pins_uart6_rx {
pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>; /* RXD */
bias-pull-up;
};
};
};
Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml 0 → 100644
View file @ b4e1bce8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/N1 Pin Controller
maintainers:
- Gareth Williams <gareth.williams.jx@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
items:
- enum:
- renesas,r9a06g032-pinctrl # RZ/N1D
- renesas,r9a06g033-pinctrl # RZ/N1S
- const: renesas,rzn1-pinctrl # Generic RZ/N1
reg:
items:
- description: GPIO Multiplexing Level1 Register Block
- description: GPIO Multiplexing Level2 Register Block
clocks:
maxItems: 1
clock-names:
const: bus
description:
The bus clock, sometimes described as pclk, for register accesses.
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
A pin multiplexing sub-node describes how to configure a set of (or a
single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
properties:
pinmux:
description: |
Integer array representing pin number and pin multiplexing
configuration.
When a pin has to be configured in alternate function mode, use
this property to identify the pin by its global index, and provide
its alternate function configuration number along with it.
When multiple pins are required to be configured as part of the
same alternate function they shall be specified as members of the
same argument list of a single "pinmux" property.
Integers values in the "pinmux" argument list are assembled as:
(PIN | MUX_FUNC << 8)
where PIN directly corresponds to the pl_gpio pin number and
MUX_FUNC is one of the alternate function identifiers defined in:
<include/dt-bindings/pinctrl/rzn1-pinctrl.h>
These identifiers collapse the IO Multiplex Configuration Level 1
and Level 2 numbers that are detailed in the hardware reference
manual into a single number. The identifiers for Level 2 are simply
offset by 10. Additional identifiers are provided to specify the
MDIO source peripheral.
phandle: true
bias-disable: true
bias-pull-up:
description: Pull up the pin with 50 kOhm
bias-pull-down:
description: Pull down the pin with 50 kOhm
bias-high-impedance: true
drive-strength:
enum: [ 4, 6, 8, 12 ]
required:
- pinmux
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
examples:
- |
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
pinctrl: pinctrl@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
clock-names = "bus";
/*
* A serial communication interface with a TX output pin and an RX
* input pin.
*/
pins_uart0: pins_uart0 {
pinmux = <
RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
>;
};
/*
* Set the pull-up on the RXD pin of the UART.
*/
pins_uart0_alt: pins_uart0_alt {
pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
pins_uart6_rx {
pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
bias-pull-up;
};
};
};
Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml 0 → 100644
View file @ b4e1bce8
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Toshiba Visconti TMPV770x pin mux/config controller
maintainers:
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
description:
Toshiba's Visconti ARM SoC a pin mux/config controller.
properties:
compatible:
enum:
- toshiba,tmpv7708-pinctrl
reg:
maxItems: 1
required:
- compatible
- reg
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength.
$ref: "pinmux-node.yaml"
properties:
function:
description:
Function to mux.
$ref: "/schemas/types.yaml#/definitions/string"
enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8,
spi0, spi1, spi2, spi3, spi4, spi5, spi6,
uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in]
groups:
description:
Name of the pin group to use for the functions.
$ref: "/schemas/types.yaml#/definitions/string"
enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp,
i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp,
spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp,
spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp,
uart0_grp, uart1_grp, uart2_grp, uart3_grp,
pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp,
pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp,
pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp,
pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp,
pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp,
pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp]
drive-strength:
enum: [2, 4, 6, 8, 16, 24, 32]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
bias-pull-up: true
bias-pull-down: true
bias-disable: true
additionalProperties: false
examples:
# Pinmux controller node
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pmux: pmux@24190000 {
compatible = "toshiba,tmpv7708-pinctrl";
reg = <0 0x24190000 0 0x10000>;
spi0_pins: spi0-pins {
function = "spi0";
groups = "spi0_grp";
};
};
};
MAINTAINERS
View file @ b4e1bce8
......@@ -1538,7 +1538,7 @@ F: Documentation/devicetree/bindings/dma/owl-dma.txt
F: Documentation/devicetree/bindings/i2c/i2c-owl.txt
F: Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
F: Documentation/devicetree/bindings/mmc/owl-mmc.yaml
F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
F: Documentation/devicetree/bindings/pinctrl/actions,*
F: Documentation/devicetree/bindings/power/actions,owl-sps.txt
F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt
F: arch/arm/boot/dts/owl-*
......@@ -13738,10 +13738,9 @@ PIN CONTROLLER - RENESAS
M: Geert Uytterhoeven <geert+renesas@glider.be>
L: linux-renesas-soc@vger.kernel.org
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-pinctrl
F: Documentation/devicetree/bindings/pinctrl/renesas,*
F: drivers/pinctrl/pinctrl-rz*
F: drivers/pinctrl/sh-pfc/
F: drivers/pinctrl/renesas/
PIN CONTROLLER - SAMSUNG
M: Tomasz Figa <tomasz.figa@gmail.com>
......
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View file @ b4e1bce8
......@@ -316,7 +316,7 @@ sdio_pins: sdio-pins {
};
pcie_reset_pins: pcie-reset-pins {
groups = "pcie1";
groups = "pcie1"; /* this actually controls "pcie1_reset" */
function = "gpio";
};
......
drivers/pinctrl/Kconfig
View file @ b4e1bce8
......@@ -208,42 +208,12 @@ config PINCTRL_OXNAS
config PINCTRL_ROCKCHIP
bool
depends on OF
select PINMUX
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
select MFD_SYSCON
config PINCTRL_RZA1
bool "Renesas RZ/A1 gpio and pinctrl driver"
depends on OF
depends on ARCH_R7S72100 || COMPILE_TEST
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
config PINCTRL_RZA2
bool "Renesas RZ/A2 gpio and pinctrl driver"
depends on OF
depends on ARCH_R7S9210 || COMPILE_TEST
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_RZN1
bool "Renesas RZ/N1 pinctrl driver"
depends on OF
depends on ARCH_RZN1 || COMPILE_TEST
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects pinctrl driver for Renesas RZ/N1 devices.
select OF_GPIO
config PINCTRL_SINGLE
tristate "One-register-per-pin type device tree based pinctrl driver"
......@@ -415,8 +385,8 @@ source "drivers/pinctrl/nomadik/Kconfig"
source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/pxa/Kconfig"
source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sh-pfc/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
source "drivers/pinctrl/stm32/Kconfig"
......@@ -429,6 +399,7 @@ source "drivers/pinctrl/mediatek/Kconfig"
source "drivers/pinctrl/zte/Kconfig"
source "drivers/pinctrl/meson/Kconfig"
source "drivers/pinctrl/cirrus/Kconfig"
source "drivers/pinctrl/visconti/Kconfig"
config PINCTRL_XWAY
bool
......
drivers/pinctrl/Makefile
View file @ b4e1bce8
......@@ -30,9 +30,6 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
......@@ -62,8 +59,8 @@ obj-y += nomadik/
obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/
obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_PINCTRL_STM32) += stm32/
......@@ -74,3 +71,4 @@ obj-$(CONFIG_ARCH_VT8500) += vt8500/
obj-y += mediatek/
obj-$(CONFIG_PINCTRL_ZX) += zte/
obj-y += cirrus/
obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/
drivers/pinctrl/actions/Kconfig
View file @ b4e1bce8
......@@ -10,6 +10,12 @@ config PINCTRL_OWL
help
Say Y here to enable Actions Semi OWL pinctrl driver
config PINCTRL_S500
bool "Actions Semi S500 pinctrl driver"
depends on PINCTRL_OWL
help
Say Y here to enable Actions Semi S500 pinctrl driver
config PINCTRL_S700
bool "Actions Semi S700 pinctrl driver"
depends on PINCTRL_OWL
......
drivers/pinctrl/actions/Makefile
View file @ b4e1bce8
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PINCTRL_OWL) += pinctrl-owl.o
obj-$(CONFIG_PINCTRL_S500) += pinctrl-s500.o
obj-$(CONFIG_PINCTRL_S700) += pinctrl-s700.o
obj-$(CONFIG_PINCTRL_S900) += pinctrl-s900.o
drivers/pinctrl/actions/pinctrl-owl.c
View file @ b4e1bce8
......@@ -125,7 +125,7 @@ static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
seq_printf(s, "%s", dev_name(pctrl->dev));
}
static struct pinctrl_ops owl_pinctrl_ops = {
static const struct pinctrl_ops owl_pinctrl_ops = {
.get_groups_count = owl_get_groups_count,
.get_group_name = owl_get_group_name,
.get_group_pins = owl_get_group_pins,
......@@ -212,7 +212,7 @@ static int owl_set_mux(struct pinctrl_dev *pctrldev,
return 0;
}
static struct pinmux_ops owl_pinmux_ops = {
static const struct pinmux_ops owl_pinmux_ops = {
.get_functions_count = owl_get_funcs_count,
.get_function_name = owl_get_func_name,
.get_function_groups = owl_get_func_groups,
......
drivers/pinctrl/actions/pinctrl-s500.c 0 → 100644
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/actions/pinctrl-s700.c
View file @ b4e1bce8
......@@ -1685,7 +1685,7 @@ static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1);
static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1);
/* Pad info table for the pinmux subsystem */
static struct owl_padinfo s700_padinfo[NUM_PADS] = {
static const struct owl_padinfo s700_padinfo[NUM_PADS] = {
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
[ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
[ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
......
drivers/pinctrl/actions/pinctrl-s900.c
View file @ b4e1bce8
......@@ -1556,7 +1556,7 @@ static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
/* Pad info table */
static struct owl_padinfo s900_padinfo[NUM_PADS] = {
static const struct owl_padinfo s900_padinfo[NUM_PADS] = {
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
[ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
[ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
......
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
View file @ b4e1bce8
......@@ -19,6 +19,7 @@
#define SCU400 0x400 /* Multi-function Pin Control #1 */
#define SCU404 0x404 /* Multi-function Pin Control #2 */
#define SCU40C 0x40C /* Multi-function Pin Control #3 */
#define SCU410 0x410 /* Multi-function Pin Control #4 */
#define SCU414 0x414 /* Multi-function Pin Control #5 */
#define SCU418 0x418 /* Multi-function Pin Control #6 */
......@@ -2591,6 +2592,22 @@ static struct aspeed_pin_config aspeed_g6_configs[] = {
/* MAC4 */
{ PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)},
{ PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},
/* GPIO18E */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, Y4, SCU40C, 4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, Y4, SCU40C, 4),
/* GPIO18D */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AB4, AC5, SCU40C, 3),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AB4, AC5, SCU40C, 3),
/* GPIO18C */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E4, E1, SCU40C, 2),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E4, E1, SCU40C, 2),
/* GPIO18B */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D3, SCU40C, 1),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D3, SCU40C, 1),
/* GPIO18A */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C6, A2, SCU40C, 0),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C6, A2, SCU40C, 0),
};
/**
......
drivers/pinctrl/aspeed/pinctrl-aspeed.c
View file @ b4e1bce8
......@@ -534,14 +534,14 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
val = pmap->val << __ffs(pconf->mask);
rc = regmap_update_bits(pdata->scu, pconf->reg,
pmap->mask, val);
pconf->mask, val);
if (rc < 0)
return rc;
pr_debug("%s: Set SCU%02X[%lu]=%d for param %d(=%d) on pin %d\n",
__func__, pconf->reg, __ffs(pconf->mask),
pmap->val, param, arg, offset);
pr_debug("%s: Set SCU%02X[0x%08X]=0x%X for param %d(=%d) on pin %d\n",
__func__, pconf->reg, pconf->mask,
val, param, arg, offset);
}
return 0;
......
drivers/pinctrl/devicetree.c
View file @ b4e1bce8
......@@ -130,9 +130,8 @@ static int dt_to_map_one_config(struct pinctrl *p,
if (!np_pctldev || of_node_is_root(np_pctldev)) {
of_node_put(np_pctldev);
ret = driver_deferred_probe_check_state(p->dev);
/* keep deferring if modules are enabled unless we've timed out */
if (IS_ENABLED(CONFIG_MODULES) && !allow_default &&
(ret == -ENODEV))
/* keep deferring if modules are enabled */
if (IS_ENABLED(CONFIG_MODULES) && !allow_default && ret < 0)
ret = -EPROBE_DEFER;
return ret;
}
......
drivers/pinctrl/freescale/Kconfig
View file @ b4e1bce8
# SPDX-License-Identifier: GPL-2.0-only
config PINCTRL_IMX
bool
tristate
depends on OF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select REGMAP
config PINCTRL_IMX_SCU
bool
tristate
depends on IMX_SCU
select PINCTRL_IMX
......
drivers/pinctrl/freescale/pinctrl-imx.c
View file @ b4e1bce8
......@@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
......@@ -373,7 +374,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
const struct imx_pinctrl_soc_info *info = ipctl->info;
if (info->flags & IMX_USE_SCU)
return imx_pinconf_get_scu(pctldev, pin_id, config);
return info->imx_pinconf_get(pctldev, pin_id, config);
else
return imx_pinconf_get_mmio(pctldev, pin_id, config);
}
......@@ -423,7 +424,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
const struct imx_pinctrl_soc_info *info = ipctl->info;
if (info->flags & IMX_USE_SCU)
return imx_pinconf_set_scu(pctldev, pin_id,
return info->imx_pinconf_set(pctldev, pin_id,
configs, num_configs);
else
return imx_pinconf_set_mmio(pctldev, pin_id,
......@@ -440,7 +441,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
int ret;
if (info->flags & IMX_USE_SCU) {
ret = imx_pinconf_get_scu(pctldev, pin_id, &config);
ret = info->imx_pinconf_get(pctldev, pin_id, &config);
if (ret) {
dev_err(ipctl->dev, "failed to get %s pinconf\n",
pin_get_name(pctldev, pin_id));
......@@ -629,7 +630,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
for (i = 0; i < grp->num_pins; i++) {
pin = &((struct imx_pin *)(grp->data))[i];
if (info->flags & IMX_USE_SCU)
imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i],
info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i],
pin, &list);
else
imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
......@@ -898,3 +899,7 @@ const struct dev_pm_ops imx_pinctrl_pm_ops = {
imx_pinctrl_resume)
};
EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
MODULE_DESCRIPTION("NXP i.MX common pinctrl driver");
MODULE_LICENSE("GPL v2");
drivers/pinctrl/freescale/pinctrl-imx.h
View file @ b4e1bce8
......@@ -75,6 +75,21 @@ struct imx_cfg_params_decode {
bool invert;
};
/**
* @dev: a pointer back to containing device
* @base: the offset to the controller in virtual memory
*/
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
struct imx_pin_reg *pin_regs;
unsigned int group_index;
struct mutex mutex;
};
struct imx_pinctrl_soc_info {
const struct pinctrl_pin_desc *pins;
unsigned int npins;
......@@ -98,21 +113,13 @@ struct imx_pinctrl_soc_info {
struct pinctrl_gpio_range *range,
unsigned offset,
bool input);
};
/**
* @dev: a pointer back to containing device
* @base: the offset to the controller in virtual memory
*/
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
struct imx_pin_reg *pin_regs;
unsigned int group_index;
struct mutex mutex;
int (*imx_pinconf_get)(struct pinctrl_dev *pctldev, unsigned int pin_id,
unsigned long *config);
int (*imx_pinconf_set)(struct pinctrl_dev *pctldev, unsigned int pin_id,
unsigned long *configs, unsigned int num_configs);
void (*imx_pinctrl_parse_pin)(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p);
};
#define IMX_CFG_PARAMS_DECODE(p, m, o) \
......@@ -137,7 +144,6 @@ struct imx_pinctrl {
int imx_pinctrl_probe(struct platform_device *pdev,
const struct imx_pinctrl_soc_info *info);
#ifdef CONFIG_PINCTRL_IMX_SCU
#define BM_PAD_CTL_GP_ENABLE BIT(30)
#define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
#define BP_PAD_CTL_IFMUX 27
......@@ -150,23 +156,4 @@ int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p);
#else
static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
return -EINVAL;
}
static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
return -EINVAL;
}
static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id,
struct imx_pin *pin,
const __be32 **list_p)
{
}
#endif
#endif /* __DRIVERS_PINCTRL_IMX_H */
drivers/pinctrl/freescale/pinctrl-imx8dxl.c
View file @ b4e1bce8
......@@ -159,6 +159,9 @@ static struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = {
.pins = imx8dxl_pinctrl_pads,
.npins = ARRAY_SIZE(imx8dxl_pinctrl_pads),
.flags = IMX_USE_SCU,
.imx_pinconf_get = imx_pinconf_get_scu,
.imx_pinconf_set = imx_pinconf_set_scu,
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
};
static const struct of_device_id imx8dxl_pinctrl_of_match[] = {
......
drivers/pinctrl/freescale/pinctrl-imx8qm.c
View file @ b4e1bce8
......@@ -292,6 +292,9 @@ static const struct imx_pinctrl_soc_info imx8qm_pinctrl_info = {
.pins = imx8qm_pinctrl_pads,
.npins = ARRAY_SIZE(imx8qm_pinctrl_pads),
.flags = IMX_USE_SCU,
.imx_pinconf_get = imx_pinconf_get_scu,
.imx_pinconf_set = imx_pinconf_set_scu,
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
};
static const struct of_device_id imx8qm_pinctrl_of_match[] = {
......
drivers/pinctrl/freescale/pinctrl-imx8qxp.c
View file @ b4e1bce8
......@@ -198,6 +198,9 @@ static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
.pins = imx8qxp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
.flags = IMX_USE_SCU,
.imx_pinconf_get = imx_pinconf_get_scu,
.imx_pinconf_set = imx_pinconf_set_scu,
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
};
static const struct of_device_id imx8qxp_pinctrl_of_match[] = {
......
drivers/pinctrl/freescale/pinctrl-scu.c
View file @ b4e1bce8
......@@ -7,6 +7,7 @@
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
......@@ -123,3 +124,7 @@ void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
pin_scu->mux_mode, pin_scu->config);
}
EXPORT_SYMBOL_GPL(imx_pinctrl_parse_pin_scu);
MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
MODULE_DESCRIPTION("NXP i.MX SCU common pinctrl driver");
MODULE_LICENSE("GPL v2");
drivers/pinctrl/intel/Kconfig
View file @ b4e1bce8
......@@ -6,11 +6,7 @@ if (X86 || COMPILE_TEST)
config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control"
depends on ACPI
select GPIOLIB
select GPIOLIB_IRQCHIP
select PINMUX
select PINCONF
select GENERIC_PINCONF
select PINCTRL_INTEL
help
driver for memory mapped GPIO functionality on Intel Baytrail
platforms. Supports 3 banks with 102, 28 and 44 gpios.
......@@ -22,11 +18,7 @@ config PINCTRL_BAYTRAIL
config PINCTRL_CHERRYVIEW
tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
depends on ACPI
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB_IRQCHIP
select PINCTRL_INTEL
help
Cherryview/Braswell pinctrl driver provides an interface that
allows configuring of SoC pins and using them as GPIOs.
......
drivers/pinctrl/intel/pinctrl-baytrail.c
View file @ b4e1bce8
......@@ -1635,28 +1635,14 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = {
static int byt_pinctrl_probe(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *soc_data = NULL;
const struct intel_pinctrl_soc_data **soc_table;
const struct intel_pinctrl_soc_data *soc_data;
struct device *dev = &pdev->dev;
struct acpi_device *acpi_dev;
struct intel_pinctrl *vg;
int i, ret;
acpi_dev = ACPI_COMPANION(dev);
if (!acpi_dev)
return -ENODEV;
soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
for (i = 0; soc_table[i]; i++) {
if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
soc_data = soc_table[i];
break;
}
}
int ret;
if (!soc_data)
return -ENODEV;
soc_data = intel_pinctrl_get_soc_data(pdev);
if (IS_ERR(soc_data))
return PTR_ERR(soc_data);
vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
if (!vg)
......
drivers/pinctrl/intel/pinctrl-cannonlake.c
View file @ b4e1bce8
......@@ -30,12 +30,12 @@
.gpio_base = (g), \
}
#define CNL_COMMUNITY(b, s, e, o, g) \
#define CNL_COMMUNITY(b, s, e, ho, g) \
{ \
.barno = (b), \
.padown_offset = CNL_PAD_OWN, \
.padcfglock_offset = CNL_PADCFGLOCK, \
.hostown_offset = (o), \
.hostown_offset = (ho), \
.is_offset = CNL_GPI_IS, \
.ie_offset = CNL_GPI_IE, \
.pin_base = (s), \
......@@ -44,10 +44,10 @@
.ngpps = ARRAY_SIZE(g), \
}
#define CNLLP_COMMUNITY(b, s, e, g) \
#define CNL_LP_COMMUNITY(b, s, e, g) \
CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)
#define CNLH_COMMUNITY(b, s, e, g) \
#define CNL_H_COMMUNITY(b, s, e, g) \
CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)
/* Cannon Lake-H */
......@@ -449,10 +449,10 @@ static const struct intel_function cnlh_functions[] = {
};
static const struct intel_community cnlh_communities[] = {
CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
CNL_H_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
CNL_H_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
CNL_H_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
CNL_H_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
};
static const struct intel_pinctrl_soc_data cnlh_soc_data = {
......@@ -810,9 +810,9 @@ static const struct intel_padgroup cnllp_community4_gpps[] = {
};
static const struct intel_community cnllp_communities[] = {
CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
CNL_LP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
CNL_LP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
CNL_LP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
};
static const struct intel_pinctrl_soc_data cnllp_soc_data = {
......
drivers/pinctrl/intel/pinctrl-cherryview.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/intel/pinctrl-intel.c
View file @ b4e1bce8
......@@ -1414,9 +1414,6 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
struct intel_pinctrl *pctrl;
int i, ret, irq;
if (!soc_data)
return -EINVAL;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
......@@ -1505,11 +1502,26 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
const struct intel_pinctrl_soc_data *data;
data = device_get_match_data(&pdev->dev);
if (!data)
return -ENODATA;
return intel_pinctrl_probe(pdev, data);
}
EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *data;
data = intel_pinctrl_get_soc_data(pdev);
if (IS_ERR(data))
return PTR_ERR(data);
return intel_pinctrl_probe(pdev, data);
}
EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *data = NULL;
const struct intel_pinctrl_soc_data **table;
......@@ -1532,15 +1544,15 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
id = platform_get_device_id(pdev);
if (!id)
return -ENODEV;
return ERR_PTR(-ENODEV);
table = (const struct intel_pinctrl_soc_data **)id->driver_data;
data = table[pdev->id];
}
return intel_pinctrl_probe(pdev, data);
return data ?: ERR_PTR(-ENODATA);
}
EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
#ifdef CONFIG_PM_SLEEP
static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
......
drivers/pinctrl/intel/pinctrl-intel.h
View file @ b4e1bce8
......@@ -10,12 +10,15 @@
#ifndef PINCTRL_INTEL_H
#define PINCTRL_INTEL_H
#include <linux/bits.h>
#include <linux/compiler_types.h>
#include <linux/gpio/driver.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/spinlock_types.h>
struct pinctrl_pin_desc;
struct platform_device;
struct device;
......@@ -194,6 +197,8 @@ struct intel_pinctrl_soc_data {
size_t ncommunities;
};
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
struct intel_pad_context;
struct intel_community_context;
......
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View file @ b4e1bce8
......@@ -22,21 +22,26 @@
#define SPT_GPI_IS 0x100
#define SPT_GPI_IE 0x120
#define SPT_COMMUNITY(b, s, e) \
#define SPT_COMMUNITY(b, s, e, pl, gs, gn, g, n) \
{ \
.barno = (b), \
.padown_offset = SPT_PAD_OWN, \
.padcfglock_offset = SPT_LP_PADCFGLOCK, \
.padcfglock_offset = (pl), \
.hostown_offset = SPT_HOSTSW_OWN, \
.is_offset = SPT_GPI_IS, \
.ie_offset = SPT_GPI_IE, \
.gpp_size = 24, \
.gpp_num_padown_regs = 4, \
.gpp_size = (gs), \
.gpp_num_padown_regs = (gn), \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = (n), \
}
#define SPTH_GPP(r, s, e, g) \
#define SPT_LP_COMMUNITY(b, s, e) \
SPT_COMMUNITY(b, s, e, SPT_LP_PADCFGLOCK, 24, 4, NULL, 0)
#define SPT_H_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
......@@ -44,19 +49,8 @@
.gpio_base = (g), \
}
#define SPTH_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = SPT_PAD_OWN, \
.padcfglock_offset = SPT_H_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \
.is_offset = SPT_GPI_IS, \
.ie_offset = SPT_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
#define SPT_H_COMMUNITY(b, s, e, g) \
SPT_COMMUNITY(b, s, e, SPT_H_PADCFGLOCK, 0, 0, g, ARRAY_SIZE(g))
/* Sunrisepoint-LP */
static const struct pinctrl_pin_desc sptlp_pins[] = {
......@@ -292,9 +286,9 @@ static const struct intel_function sptlp_functions[] = {
};
static const struct intel_community sptlp_communities[] = {
SPT_COMMUNITY(0, 0, 47),
SPT_COMMUNITY(1, 48, 119),
SPT_COMMUNITY(2, 120, 151),
SPT_LP_COMMUNITY(0, 0, 47),
SPT_LP_COMMUNITY(1, 48, 119),
SPT_LP_COMMUNITY(2, 120, 151),
};
static const struct intel_pinctrl_soc_data sptlp_soc_data = {
......@@ -554,27 +548,27 @@ static const struct intel_function spth_functions[] = {
};
static const struct intel_padgroup spth_community0_gpps[] = {
SPTH_GPP(0, 0, 23, 0), /* GPP_A */
SPTH_GPP(1, 24, 47, 24), /* GPP_B */
SPT_H_GPP(0, 0, 23, 0), /* GPP_A */
SPT_H_GPP(1, 24, 47, 24), /* GPP_B */
};
static const struct intel_padgroup spth_community1_gpps[] = {
SPTH_GPP(0, 48, 71, 48), /* GPP_C */
SPTH_GPP(1, 72, 95, 72), /* GPP_D */
SPTH_GPP(2, 96, 108, 96), /* GPP_E */
SPTH_GPP(3, 109, 132, 120), /* GPP_F */
SPTH_GPP(4, 133, 156, 144), /* GPP_G */
SPTH_GPP(5, 157, 180, 168), /* GPP_H */
SPT_H_GPP(0, 48, 71, 48), /* GPP_C */
SPT_H_GPP(1, 72, 95, 72), /* GPP_D */
SPT_H_GPP(2, 96, 108, 96), /* GPP_E */
SPT_H_GPP(3, 109, 132, 120), /* GPP_F */
SPT_H_GPP(4, 133, 156, 144), /* GPP_G */
SPT_H_GPP(5, 157, 180, 168), /* GPP_H */
};
static const struct intel_padgroup spth_community3_gpps[] = {
SPTH_GPP(0, 181, 191, 192), /* GPP_I */
SPT_H_GPP(0, 181, 191, 192), /* GPP_I */
};
static const struct intel_community spth_communities[] = {
SPTH_COMMUNITY(0, 0, 47, spth_community0_gpps),
SPTH_COMMUNITY(1, 48, 180, spth_community1_gpps),
SPTH_COMMUNITY(2, 181, 191, spth_community3_gpps),
SPT_H_COMMUNITY(0, 0, 47, spth_community0_gpps),
SPT_H_COMMUNITY(1, 48, 180, spth_community1_gpps),
SPT_H_COMMUNITY(2, 181, 191, spth_community3_gpps),
};
static const struct intel_pinctrl_soc_data spth_soc_data = {
......
drivers/pinctrl/intel/pinctrl-tigerlake.c
View file @ b4e1bce8
......@@ -16,8 +16,10 @@
#include "pinctrl-intel.h"
#define TGL_PAD_OWN 0x020
#define TGL_PADCFGLOCK 0x080
#define TGL_HOSTSW_OWN 0x0b0
#define TGL_LP_PADCFGLOCK 0x080
#define TGL_H_PADCFGLOCK 0x090
#define TGL_LP_HOSTSW_OWN 0x0b0
#define TGL_H_HOSTSW_OWN 0x0c0
#define TGL_GPI_IS 0x100
#define TGL_GPI_IE 0x120
......@@ -29,12 +31,12 @@
.gpio_base = (g), \
}
#define TGL_COMMUNITY(b, s, e, g) \
#define TGL_COMMUNITY(b, s, e, pl, ho, g) \
{ \
.barno = (b), \
.padown_offset = TGL_PAD_OWN, \
.padcfglock_offset = TGL_PADCFGLOCK, \
.hostown_offset = TGL_HOSTSW_OWN, \
.padcfglock_offset = (pl), \
.hostown_offset = (ho), \
.is_offset = TGL_GPI_IS, \
.ie_offset = TGL_GPI_IE, \
.pin_base = (s), \
......@@ -43,6 +45,12 @@
.ngpps = ARRAY_SIZE(g), \
}
#define TGL_LP_COMMUNITY(b, s, e, g) \
TGL_COMMUNITY(b, s, e, TGL_LP_PADCFGLOCK, TGL_LP_HOSTSW_OWN, g)
#define TGL_H_COMMUNITY(b, s, e, g) \
TGL_COMMUNITY(b, s, e, TGL_H_PADCFGLOCK, TGL_H_HOSTSW_OWN, g)
/* Tiger Lake-LP */
static const struct pinctrl_pin_desc tgllp_pins[] = {
/* GPP_B */
......@@ -367,10 +375,10 @@ static const struct intel_padgroup tgllp_community5_gpps[] = {
};
static const struct intel_community tgllp_communities[] = {
TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps),
TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps),
TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps),
TGL_LP_COMMUNITY(0, 0, 66, tgllp_community0_gpps),
TGL_LP_COMMUNITY(1, 67, 170, tgllp_community1_gpps),
TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
TGL_LP_COMMUNITY(3, 260, 276, tgllp_community5_gpps),
};
static const struct intel_pinctrl_soc_data tgllp_soc_data = {
......@@ -723,11 +731,11 @@ static const struct intel_padgroup tglh_community5_gpps[] = {
};
static const struct intel_community tglh_communities[] = {
TGL_COMMUNITY(0, 0, 78, tglh_community0_gpps),
TGL_COMMUNITY(1, 79, 180, tglh_community1_gpps),
TGL_COMMUNITY(2, 181, 217, tglh_community3_gpps),
TGL_COMMUNITY(3, 218, 266, tglh_community4_gpps),
TGL_COMMUNITY(4, 267, 290, tglh_community5_gpps),
TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps),
TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps),
TGL_H_COMMUNITY(2, 181, 217, tglh_community3_gpps),
TGL_H_COMMUNITY(3, 218, 266, tglh_community4_gpps),
TGL_H_COMMUNITY(4, 267, 290, tglh_community5_gpps),
};
static const struct intel_pinctrl_soc_data tglh_soc_data = {
......
drivers/pinctrl/mediatek/Kconfig
View file @ b4e1bce8
......@@ -119,6 +119,13 @@ config PINCTRL_MT7622
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
config PINCTRL_MT8167
bool "Mediatek MT8167 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK
config PINCTRL_MT8173
bool "Mediatek MT8173 pin control"
depends on OF
......@@ -133,6 +140,13 @@ config PINCTRL_MT8183
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8192
bool "Mediatek MT8192 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8516
bool "Mediatek MT8516 pin control"
depends on OF
......
drivers/pinctrl/mediatek/Makefile
View file @ b4e1bce8
......@@ -17,7 +17,9 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
drivers/pinctrl/mediatek/pinctrl-moore.c
View file @ b4e1bce8
......@@ -589,7 +589,6 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc)
{
struct pinctrl_pin_desc *pins;
struct resource *res;
struct mtk_pinctrl *hw;
int err, i;
......@@ -612,14 +611,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
return -ENOMEM;
for (i = 0; i < hw->soc->nbase_names; i++) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
hw->soc->base_names[i]);
if (!res) {
dev_err(&pdev->dev, "missing IO resource\n");
return -ENXIO;
}
hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(hw->base[i]))
return PTR_ERR(hw->base[i]);
}
......
drivers/pinctrl/mediatek/pinctrl-mt7622.c
View file @ b4e1bce8
......@@ -263,6 +263,68 @@ static const struct mtk_pin_desc mt7622_pins[] = {
* hardware probably has multiple combinations of these pinouts.
*/
/* ANTSEL */
static int mt7622_antsel0_pins[] = { 91, };
static int mt7622_antsel0_funcs[] = { 5, };
static int mt7622_antsel1_pins[] = { 92, };
static int mt7622_antsel1_funcs[] = { 5, };
static int mt7622_antsel2_pins[] = { 93, };
static int mt7622_antsel2_funcs[] = { 5, };
static int mt7622_antsel3_pins[] = { 94, };
static int mt7622_antsel3_funcs[] = { 5, };
static int mt7622_antsel4_pins[] = { 95, };
static int mt7622_antsel4_funcs[] = { 5, };
static int mt7622_antsel5_pins[] = { 96, };
static int mt7622_antsel5_funcs[] = { 5, };
static int mt7622_antsel6_pins[] = { 97, };
static int mt7622_antsel6_funcs[] = { 5, };
static int mt7622_antsel7_pins[] = { 98, };
static int mt7622_antsel7_funcs[] = { 5, };
static int mt7622_antsel8_pins[] = { 99, };
static int mt7622_antsel8_funcs[] = { 5, };
static int mt7622_antsel9_pins[] = { 100, };
static int mt7622_antsel9_funcs[] = { 5, };
static int mt7622_antsel10_pins[] = { 101, };
static int mt7622_antsel10_funcs[] = { 5, };
static int mt7622_antsel11_pins[] = { 102, };
static int mt7622_antsel11_funcs[] = { 5, };
static int mt7622_antsel12_pins[] = { 73, };
static int mt7622_antsel12_funcs[] = { 5, };
static int mt7622_antsel13_pins[] = { 74, };
static int mt7622_antsel13_funcs[] = { 5, };
static int mt7622_antsel14_pins[] = { 75, };
static int mt7622_antsel14_funcs[] = { 5, };
static int mt7622_antsel15_pins[] = { 76, };
static int mt7622_antsel15_funcs[] = { 5, };
static int mt7622_antsel16_pins[] = { 77, };
static int mt7622_antsel16_funcs[] = { 5, };
static int mt7622_antsel17_pins[] = { 22, };
static int mt7622_antsel17_funcs[] = { 5, };
static int mt7622_antsel18_pins[] = { 79, };
static int mt7622_antsel18_funcs[] = { 5, };
static int mt7622_antsel19_pins[] = { 80, };
static int mt7622_antsel19_funcs[] = { 5, };
static int mt7622_antsel20_pins[] = { 81, };
static int mt7622_antsel20_funcs[] = { 5, };
static int mt7622_antsel21_pins[] = { 82, };
static int mt7622_antsel21_funcs[] = { 5, };
static int mt7622_antsel22_pins[] = { 14, };
static int mt7622_antsel22_funcs[] = { 5, };
static int mt7622_antsel23_pins[] = { 15, };
static int mt7622_antsel23_funcs[] = { 5, };
static int mt7622_antsel24_pins[] = { 16, };
static int mt7622_antsel24_funcs[] = { 5, };
static int mt7622_antsel25_pins[] = { 17, };
static int mt7622_antsel25_funcs[] = { 5, };
static int mt7622_antsel26_pins[] = { 18, };
static int mt7622_antsel26_funcs[] = { 5, };
static int mt7622_antsel27_pins[] = { 19, };
static int mt7622_antsel27_funcs[] = { 5, };
static int mt7622_antsel28_pins[] = { 20, };
static int mt7622_antsel28_funcs[] = { 5, };
static int mt7622_antsel29_pins[] = { 21, };
static int mt7622_antsel29_funcs[] = { 5, };
/* EMMC */
static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
......@@ -543,6 +605,36 @@ static int mt7622_wled_pins[] = { 85, };
static int mt7622_wled_funcs[] = { 0, };
static const struct group_desc mt7622_groups[] = {
PINCTRL_PIN_GROUP("antsel0", mt7622_antsel0),
PINCTRL_PIN_GROUP("antsel1", mt7622_antsel1),
PINCTRL_PIN_GROUP("antsel2", mt7622_antsel2),
PINCTRL_PIN_GROUP("antsel3", mt7622_antsel3),
PINCTRL_PIN_GROUP("antsel4", mt7622_antsel4),
PINCTRL_PIN_GROUP("antsel5", mt7622_antsel5),
PINCTRL_PIN_GROUP("antsel6", mt7622_antsel6),
PINCTRL_PIN_GROUP("antsel7", mt7622_antsel7),
PINCTRL_PIN_GROUP("antsel8", mt7622_antsel8),
PINCTRL_PIN_GROUP("antsel9", mt7622_antsel9),
PINCTRL_PIN_GROUP("antsel10", mt7622_antsel10),
PINCTRL_PIN_GROUP("antsel11", mt7622_antsel11),
PINCTRL_PIN_GROUP("antsel12", mt7622_antsel12),
PINCTRL_PIN_GROUP("antsel13", mt7622_antsel13),
PINCTRL_PIN_GROUP("antsel14", mt7622_antsel14),
PINCTRL_PIN_GROUP("antsel15", mt7622_antsel15),
PINCTRL_PIN_GROUP("antsel16", mt7622_antsel16),
PINCTRL_PIN_GROUP("antsel17", mt7622_antsel17),
PINCTRL_PIN_GROUP("antsel18", mt7622_antsel18),
PINCTRL_PIN_GROUP("antsel19", mt7622_antsel19),
PINCTRL_PIN_GROUP("antsel20", mt7622_antsel20),
PINCTRL_PIN_GROUP("antsel21", mt7622_antsel21),
PINCTRL_PIN_GROUP("antsel22", mt7622_antsel22),
PINCTRL_PIN_GROUP("antsel23", mt7622_antsel23),
PINCTRL_PIN_GROUP("antsel24", mt7622_antsel24),
PINCTRL_PIN_GROUP("antsel25", mt7622_antsel25),
PINCTRL_PIN_GROUP("antsel26", mt7622_antsel26),
PINCTRL_PIN_GROUP("antsel27", mt7622_antsel27),
PINCTRL_PIN_GROUP("antsel28", mt7622_antsel28),
PINCTRL_PIN_GROUP("antsel29", mt7622_antsel29),
PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
......@@ -663,6 +755,16 @@ static const struct group_desc mt7622_groups[] = {
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
*/
static const char *mt7622_antsel_groups[] = { "antsel0", "antsel1", "antsel2",
"antsel3", "antsel4", "antsel5",
"antsel6", "antsel7", "antsel8",
"antsel9", "antsel10", "antsel11",
"antsel12", "antsel13", "antsel14",
"antsel15", "antsel16", "antsel17",
"antsel18", "antsel19", "antsel20",
"antsel21", "antsel22", "antsel23",
"antsel24", "antsel25", "antsel26",
"antsel27", "antsel28", "antsel29",};
static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
"esw_p2_p3_p4", "mdc_mdio",
......@@ -732,6 +834,7 @@ static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx",
static const char *mt7622_wdt_groups[] = { "watchdog", };
static const struct function_desc mt7622_functions[] = {
{"antsel", mt7622_antsel_groups, ARRAY_SIZE(mt7622_antsel_groups)},
{"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
{"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
{"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
......
drivers/pinctrl/mediatek/pinctrl-mt8167.c 0 → 100644
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/mediatek/pinctrl-mt8192.c 0 → 100644
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h 0 → 100644
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/mediatek/pinctrl-mtk-mt8192.h 0 → 100644
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/mediatek/pinctrl-paris.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View file @ b4e1bce8
......@@ -197,7 +197,7 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
......
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/pinctrl-amd.h
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/pinctrl-at91-pio4.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/pinctrl-ingenic.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/pinctrl-mcp23s08.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/pinctrl-ocelot.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/pinctrl-single.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/pinctrl-sx150x.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/qcom/Kconfig
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/qcom/Makefile
View file @ b4e1bce8
......@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
......
drivers/pinctrl/qcom/pinctrl-msm8226.c 0 → 100644
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/spear/pinctrl-spear310.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/spear/pinctrl-spear320.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/sunxi/Kconfig
View file @ b4e1bce8
This diff is collapsed.
drivers/pinctrl/sunxi/Makefile
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drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c 0 → 100644
View file @ b4e1bce8
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drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c 0 → 100644
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drivers/pinctrl/visconti/Kconfig 0 → 100644
View file @ b4e1bce8
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drivers/pinctrl/visconti/Makefile 0 → 100644
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drivers/pinctrl/visconti/pinctrl-common.c 0 → 100644
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drivers/pinctrl/visconti/pinctrl-common.h 0 → 100644
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drivers/pinctrl/visconti/pinctrl-tmpv7700.c 0 → 100644
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This diff is collapsed.
include/dt-bindings/pinctrl/mt8192-pinfunc.h 0 → 100644
View file @ b4e1bce8
This diff is collapsed.
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