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Commit b5948fc6 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events: Update Sandybridge 

Events are still at version 16:
    https://download.01.org/perfmon/SNB
Json files generated by the latest code at:
    https://github.com/intel/event-converter-for-linux-perf

Tested:

Not tested on a Sandybridge, on a SkylakeX:

  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-22-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
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tools/perf/pmu-events/arch/x86/sandybridge/cache.json
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tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json
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[
{
"EventCode": "0x10",
"BriefDescription": "Cycles with any input/output SSE or FP assist.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
"SampleAfterValue": "100003",
"UMask": "0x1e"
},
{
"EventCode": "0x10",
"BriefDescription": "Number of SIMD FP assists due to input values.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"EventCode": "0x10",
"BriefDescription": "Number of SIMD FP assists due to Output values.",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"EventCode": "0x10",
"BriefDescription": "Number of X87 assists due to input value.",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"EventCode": "0x10",
"BriefDescription": "Number of X87 assists due to output value.",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"EventCode": "0x11",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x10"
},
{
"EventCode": "0x11",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x40"
},
{
"EventCode": "0xC1",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"SampleAfterValue": "100003",
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"EventCode": "0xC1",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"EventCode": "0xC1",
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"EventCode": "0xCA",
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_ASSIST.X87_OUTPUT",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"SampleAfterValue": "100003",
"BriefDescription": "Number of X87 assists due to output value.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x8"
},
{
"EventCode": "0xCA",
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "FP_ASSIST.X87_INPUT",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
"BriefDescription": "Number of X87 assists due to input value.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x10"
},
{
"EventCode": "0xCA",
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
"BriefDescription": "Number of SIMD FP assists due to Output values.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x20"
},
{
"EventCode": "0xCA",
"BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "FP_ASSIST.SIMD_INPUT",
"SampleAfterValue": "100003",
"BriefDescription": "Number of SIMD FP assists due to input values.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0xCA",
"BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
"Counter": "0,1,2,3",
"UMask": "0x1e",
"EventName": "FP_ASSIST.ANY",
"SampleAfterValue": "100003",
"BriefDescription": "Cycles with any input/output SSE or FP assist.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/sandybridge/frontend.json
View file @ b5948fc6
[
{
"EventCode": "0x79",
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "IDQ.EMPTY",
"SampleAfterValue": "2000003",
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
"CounterHTOff": "0,1,2,3"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
"UMask": "0x1f"
},
{
"EventCode": "0x79",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "IDQ.MITE_UOPS",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0x79",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "IDQ.MITE_CYCLES",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"EventCode": "0x79",
"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "IDQ.DSB_UOPS",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.ALL_CANCEL",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0xa"
},
{
"EventCode": "0x79",
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "IDQ.DSB_CYCLES",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x8"
},
{
"EventCode": "0x79",
"BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "IDQ.MS_DSB_UOPS",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.OTHER_CANCEL",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"EventCode": "0x79",
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "IDQ.MS_DSB_CYCLES",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0x79",
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EdgeDetect": "1",
"EventName": "IDQ.MS_DSB_OCCUR",
"SampleAfterValue": "2000003",
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"EventCode": "0x79",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
"Counter": "0,1,2,3",
"UMask": "0x18",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x18"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x18",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "IDQ.MS_MITE_UOPS",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x18"
},
{
"EventCode": "0x79",
"BriefDescription": "Cycles MITE is delivering 4 Uops.",
"Counter": "0,1,2,3",
"UMask": "0x24",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles MITE is delivering 4 Uops.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x24"
},
{
"EventCode": "0x79",
"BriefDescription": "Cycles MITE is delivering any Uop.",
"Counter": "0,1,2,3",
"UMask": "0x24",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles MITE is delivering any Uop.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x24"
},
{
"EventCode": "0x79",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "IDQ.MS_UOPS",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x8"
},
{
"PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual for more information.",
"EventCode": "0x79",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "IDQ.MS_CYCLES",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x8"
},
{
"EventCode": "0x79",
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EdgeDetect": "1",
"EventName": "IDQ.MS_SWITCHES",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"EventCode": "0x79",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
"Counter": "0,1,2,3",
"UMask": "0x3c",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x3c"
},
{
"EventCode": "0x80",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ICACHE.HIT",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x4"
},
{
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
"EventCode": "0x80",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200003",
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
"EventCode": "0x9C",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
"PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel 64 and IA-32 Architectures Optimization Reference Manual for more information.",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
"CounterHTOff": "0,1,2,3"
"UMask": "0x30"
},
{
"EventCode": "0x9C",
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3"
"UMask": "0x10"
},
{
"EventCode": "0x9C",
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_OCCUR",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"CounterMask": "3",
"CounterHTOff": "0,1,2,3"
"UMask": "0x10"
},
{
"EventCode": "0x9C",
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"CounterMask": "2",
"CounterHTOff": "0,1,2,3"
"UMask": "0x10"
},
{
"EventCode": "0x9C",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"UMask": "0x20"
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"EventCode": "0x9C",
"Invert": "1",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3"
"UMask": "0x30"
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"Invert": "1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xAB",
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
"SampleAfterValue": "2000003",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
"EventCode": "0xAB",
"BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
"Invert": "1",
"SampleAfterValue": "2000003",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0xAC",
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DSB_FILL.OTHER_CANCEL",
"CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0xAC",
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
"CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0xAC",
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3",
"UMask": "0xa",
"EventName": "DSB_FILL.ALL_CANCEL",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/sandybridge/memory.json
View file @ b5948fc6
[
{
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "MISALIGN_MEM_REF.LOADS",
"SampleAfterValue": "2000003",
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "MISALIGN_MEM_REF.STORES",
"SampleAfterValue": "2000003",
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xBE",
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "PAGE_WALKS.LLC_MISS",
"SampleAfterValue": "100003",
"BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.",
"SampleAfterValue": "100003",
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x4",
"BriefDescription": "Loads with latency value being above 128.",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"SampleAfterValue": "100003",
"BriefDescription": "Loads with latency value being above 4 .",
"MSRValue": "0x80",
"PEBS": "2",
"SampleAfterValue": "1009",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x8",
"BriefDescription": "Loads with latency value being above 16.",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"SampleAfterValue": "50021",
"BriefDescription": "Loads with latency value being above 8.",
"MSRValue": "0x10",
"PEBS": "2",
"SampleAfterValue": "20011",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x10",
"BriefDescription": "Loads with latency value being above 256.",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"SampleAfterValue": "20011",
"BriefDescription": "Loads with latency value being above 16.",
"MSRValue": "0x100",
"PEBS": "2",
"SampleAfterValue": "503",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x20",
"BriefDescription": "Loads with latency value being above 32.",
"Counter": "3",
"UMask": "0x1",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"SampleAfterValue": "100007",
"BriefDescription": "Loads with latency value being above 32.",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x40",
"BriefDescription": "Loads with latency value being above 4 .",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"SampleAfterValue": "2003",
"BriefDescription": "Loads with latency value being above 64.",
"MSRValue": "0x4",
"PEBS": "2",
"SampleAfterValue": "100003",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x80",
"BriefDescription": "Loads with latency value being above 512.",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"SampleAfterValue": "1009",
"BriefDescription": "Loads with latency value being above 128.",
"MSRValue": "0x200",
"PEBS": "2",
"SampleAfterValue": "101",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x100",
"BriefDescription": "Loads with latency value being above 64.",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"SampleAfterValue": "503",
"BriefDescription": "Loads with latency value being above 256.",
"MSRValue": "0x40",
"PEBS": "2",
"SampleAfterValue": "2003",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x200",
"BriefDescription": "Loads with latency value being above 8.",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"SampleAfterValue": "101",
"BriefDescription": "Loads with latency value being above 512.",
"MSRValue": "0x8",
"PEBS": "2",
"SampleAfterValue": "50021",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
"Counter": "3",
"UMask": "0x2",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
"PEBS": "2",
"PRECISE_STORE": "1",
"SampleAfterValue": "2000003",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x2"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400244",
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400244",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400091",
"BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400091",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400240",
"BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400240",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400090",
"BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400090",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400120",
"BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400120",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x3004003f7",
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3004003f7",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400122",
"BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400122",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400004",
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80408fff",
"Offcore": "1",
"PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400001",
"BriefDescription": "Counts LLC replacements.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6004001b3",
"Offcore": "1",
"PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400002",
"BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x17004001b3",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400040",
"BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400004",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400010",
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400001",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400020",
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80400004",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400200",
"BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400002",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400080",
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80400010",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x300400100",
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80400040",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM",
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6004001b3",
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400040",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "Counts LLC replacements.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM",
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x1f80408fff",
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400010",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x17004001b3",
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400020",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x1f80400004",
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400200",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x1f80400010",
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400080",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x1f80400040",
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400100",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x1f80400080",
"BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80400080",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x1f80400200",
"BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80400200",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBE",
"EventName": "PAGE_WALKS.LLC_MISS",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/sandybridge/other.json
View file @ b5948fc6
[
{
"EventCode": "0x17",
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"SampleAfterValue": "2000003",
"BriefDescription": "Valid instructions written to IQ per cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0x4E",
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "HW_PRE_REQ.DL1_MISS",
"SampleAfterValue": "2000003",
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0_TRANS",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"EventCode": "0x5C",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CPL_CYCLES.RING0",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"EventCode": "0x5C",
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EdgeDetect": "1",
"EventName": "CPL_CYCLES.RING0_TRANS",
"SampleAfterValue": "100007",
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4E",
"EventName": "HW_PRE_REQ.DL1_MISS",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0x5C",
"BriefDescription": "Valid instructions written to IQ per cycle.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "CPL_CYCLES.RING123",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x17",
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0x63",
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
View file @ b5948fc6
[
{
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"Counter": "Fixed counter 2",
"UMask": "0x3",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the core is not in halt state.",
"CounterHTOff": "Fixed counter 2"
},
{
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
"Counter": "Fixed counter 0",
"UMask": "0x1",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Instructions retired from execution.",
"CounterHTOff": "Fixed counter 0"
"BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB6",
"EventName": "AGU_BYPASS_CANCEL.COUNT",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"Counter": "Fixed counter 1",
"UMask": "0x2",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when the thread is not in halt state.",
"CounterHTOff": "Fixed counter 1"
"BriefDescription": "Divide operations executed.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV",
"PublicDescription": "This event counts the number of the divide operations executed.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"Counter": "Fixed counter 1",
"UMask": "0x2",
"AnyThread": "1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"BriefDescription": "Cycles when divider is busy executing divide operations.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"CounterHTOff": "Fixed counter 1"
"UMask": "0x1"
},
{
"EventCode": "0x03",
"BriefDescription": "Speculative and retired branches.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"SampleAfterValue": "100003",
"BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"SampleAfterValue": "200003",
"UMask": "0xff"
},
{
"PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
"EventCode": "0x03",
"BriefDescription": "Speculative and retired macro-conditional branches.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"SampleAfterValue": "100003",
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
"UMask": "0xc1"
},
{
"EventCode": "0x03",
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "LD_BLOCKS.NO_SR",
"SampleAfterValue": "100003",
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"SampleAfterValue": "200003",
"UMask": "0xc2"
},
{
"EventCode": "0x03",
"BriefDescription": "Speculative and retired direct near calls.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"SampleAfterValue": "100003",
"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"UMask": "0xd0"
},
{
"PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.",
"EventCode": "0x07",
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"SampleAfterValue": "100003",
"BriefDescription": "False dependencies in MOB due to partial compare.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
"UMask": "0xc4"
},
{
"EventCode": "0x07",
"BriefDescription": "Speculative and retired indirect return branches.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",
"SampleAfterValue": "100003",
"BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
"UMask": "0xc8"
},
{
"EventCode": "0x0D",
"BriefDescription": "Not taken macro-conditional branches.",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "INT_MISC.RECOVERY_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"EventCode": "0x0D",
"BriefDescription": "Taken speculative and retired macro-conditional branches.",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EdgeDetect": "1",
"EventName": "INT_MISC.RECOVERY_STALLS_COUNT",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
"UMask": "0x81"
},
{
"EventCode": "0x0D",
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
"Counter": "0,1,2,3",
"UMask": "0x3",
"AnyThread": "1",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"SampleAfterValue": "200003",
"UMask": "0x82"
},
{
"EventCode": "0x0D",
"BriefDescription": "Taken speculative and retired direct near calls.",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "INT_MISC.RAT_STALL_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"UMask": "0x90"
},
{
"PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
"EventCode": "0x0E",
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
"UMask": "0x84"
},
{
"EventCode": "0x0E",
"Invert": "1",
"BriefDescription": "Taken speculative and retired indirect calls.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"UMask": "0xa0"
},
{
"EventCode": "0x0E",
"Invert": "1",
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"AnyThread": "1",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
"UMask": "0x88"
},
{
"EventCode": "0x14",
"BriefDescription": "All (macro) branch instructions retired.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when divider is busy executing divide operations.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009"
},
{
"PublicDescription": "This event counts the number of the divide operations executed.",
"EventCode": "0x14",
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EdgeDetect": "1",
"EventName": "ARITH.FPU_DIV",
"SampleAfterValue": "100003",
"BriefDescription": "Divide operations executed.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
"SampleAfterValue": "400009",
"UMask": "0x4"
},
{
"EventCode": "0x3C",
"BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Thread cycles when thread is not in halt state.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
"SampleAfterValue": "400009",
"UMask": "0x1"
},
{
"EventCode": "0x3C",
"BriefDescription": "Far branch instructions retired.",
"Counter": "0,1,2,3",
"UMask": "0x0",
"AnyThread": "1",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"EventCode": "0x3C",
"BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
"SampleAfterValue": "100007",
"UMask": "0x2"
},
{
"EventCode": "0x3C",
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x1",
"AnyThread": "1",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
"SampleAfterValue": "100007",
"UMask": "0x2"
},
{
"PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
"EventCode": "0x3C",
"BriefDescription": "Return instructions retired. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
"SampleAfterValue": "100007",
"UMask": "0x8"
},
{
"EventCode": "0x3C",
"BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x1",
"AnyThread": "1",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
"SampleAfterValue": "400009",
"UMask": "0x20"
},
{
"EventCode": "0x3C",
"BriefDescription": "Not taken branch instructions retired.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
"CounterHTOff": "0,1,2,3"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"SampleAfterValue": "400009",
"UMask": "0x10"
},
{
"EventCode": "0x3C",
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"SampleAfterValue": "200003",
"UMask": "0xff"
},
{
"EventCode": "0x4C",
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LOAD_HIT_PRE.SW_PF",
"SampleAfterValue": "100003",
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
"UMask": "0xc1"
},
{
"EventCode": "0x4C",
"BriefDescription": "Speculative and retired mispredicted direct near calls.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "LOAD_HIT_PRE.HW_PF",
"SampleAfterValue": "100003",
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"UMask": "0xd0"
},
{
"EventCode": "0x59",
"BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP",
"SampleAfterValue": "2000003",
"BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
"UMask": "0xc4"
},
{
"PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual.",
"EventCode": "0x59",
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",
"EventCode": "0x59",
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles with at least one slow LEA uop being allocated.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
"UMask": "0x81"
},
{
"EventCode": "0x59",
"BriefDescription": "Taken speculative and retired mispredicted direct near calls.",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",
"SampleAfterValue": "2000003",
"BriefDescription": "Multiply packed/scalar single precision uops allocated.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"UMask": "0x90"
},
{
"EventCode": "0x5B",
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
"Counter": "0,1,2,3",
"UMask": "0xc",
"EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles with either free list is empty.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
"UMask": "0x84"
},
{
"EventCode": "0x5B",
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
"Counter": "0,1,2,3",
"UMask": "0xf",
"EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL",
"SampleAfterValue": "2000003",
"BriefDescription": "Resource stalls2 control structures full for physical registers.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"UMask": "0xa0"
},
{
"EventCode": "0x5B",
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "RESOURCE_STALLS2.BOB_FULL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"SampleAfterValue": "200003",
"UMask": "0x88"
},
{
"EventCode": "0x5B",
"BriefDescription": "All mispredicted macro branch instructions retired.",
"Counter": "0,1,2,3",
"UMask": "0x4f",
"EventName": "RESOURCE_STALLS2.OOO_RSRC",
"SampleAfterValue": "2000003",
"BriefDescription": "Resource stalls out of order resources full.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009"
},
{
"EventCode": "0x5E",
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
"PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
"SampleAfterValue": "400009",
"UMask": "0x4"
},
{
"EventCode": "0x5E",
"Invert": "1",
"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EdgeDetect": "1",
"EventName": "RS_EVENTS.EMPTY_END",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
"SampleAfterValue": "400009",
"UMask": "0x1"
},
{
"EventCode": "0x87",
"BriefDescription": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000003",
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
"SampleAfterValue": "100007",
"UMask": "0x2"
},
{
"EventCode": "0x87",
"BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000003",
"BriefDescription": "Stall cycles because IQ is full.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NOT_TAKEN",
"PEBS": "1",
"SampleAfterValue": "400009",
"UMask": "0x10"
},
{
"EventCode": "0x88",
"BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x41",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
"BriefDescription": "Not taken macro-conditional branches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.TAKEN",
"PEBS": "1",
"SampleAfterValue": "400009",
"UMask": "0x20"
},
{
"EventCode": "0x88",
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
"Counter": "0,1,2,3",
"UMask": "0x81",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired macro-conditional branches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0x88",
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
"Counter": "0,1,2,3",
"UMask": "0x82",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"EventCode": "0x88",
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"Counter": "0,1,2,3",
"UMask": "0x84",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"EventCode": "0x88",
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
"Counter": "0,1,2,3",
"UMask": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x90",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired direct near calls.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"BriefDescription": "Reference cycles when the core is not in halt state.",
"Counter": "Fixed counter 2",
"CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"EventCode": "0x88",
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
"Counter": "0,1,2,3",
"UMask": "0xa0",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired indirect calls.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"EventCode": "0x88",
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"Counter": "0,1,2,3",
"UMask": "0xc1",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
"BriefDescription": "Speculative and retired macro-conditional branches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0xc2",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"SampleAfterValue": "200003",
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"BriefDescription": "Core cycles when the thread is not in halt state.",
"Counter": "Fixed counter 1",
"CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0xc4",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"Counter": "Fixed counter 1",
"CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0x88",
"BriefDescription": "Thread cycles when thread is not in halt state.",
"Counter": "0,1,2,3",
"UMask": "0xc8",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "Speculative and retired indirect return branches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000003"
},
{
"EventCode": "0x88",
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"Counter": "0,1,2,3",
"UMask": "0xd0",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Speculative and retired direct near calls.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0xff",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Speculative and retired branches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0x89",
"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",
"Counter": "0,1,2,3",
"UMask": "0x41",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"EventCode": "0x89",
"BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",
"Counter": "0,1,2,3",
"UMask": "0x81",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x84",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
"SampleAfterValue": "2000003",
"UMask": "0x6"
},
{
"EventCode": "0x89",
"BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",
"Counter": "0,1,2,3",
"UMask": "0x88",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
"SampleAfterValue": "2000003",
"UMask": "0x5"
},
{
"EventCode": "0x89",
"BriefDescription": "Stall cycles because IQ is full.",
"Counter": "0,1,2,3",
"UMask": "0x90",
"EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired mispredicted direct near calls.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"EventCode": "0x89",
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
"Counter": "0,1,2,3",
"UMask": "0xa0",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0xc1",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"BriefDescription": "Instructions retired from execution.",
"Counter": "Fixed counter 0",
"CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"EventCode": "0x89",
"BriefDescription": "Number of instructions retired. General Counter - architectural event.",
"Counter": "0,1,2,3",
"UMask": "0xc4",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
"BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0xd0",
"EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Speculative and retired mispredicted direct near calls.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"BriefDescription": "Instructions retired. (Precise Event - PEBS).",
"Counter": "1",
"CounterHTOff": "1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "2",
"SampleAfterValue": "2000003",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"EventCode": "0x89",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.",
"Counter": "0,1,2,3",
"UMask": "0xff",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RAT_STALL_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x40"
},
{
"EventCode": "0xA1",
"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x3"
},
{
"EventCode": "0xA1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"AnyThread": "1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are dispatched to port 0.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x3"
},
{
"EventCode": "0xA1",
"BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_STALLS_COUNT",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are dispatched to port 1.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x3"
},
{
"EventCode": "0xA1",
"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).",
"Counter": "0,1,2,3",
"UMask": "0x2",
"AnyThread": "1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are dispatched to port 1.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"EventCode": "0xA1",
"BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.",
"Counter": "0,1,2,3",
"UMask": "0xc",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"EventCode": "0xA1",
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"Counter": "0,1,2,3",
"UMask": "0xc",
"AnyThread": "1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"EventCode": "0xA1",
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"EventCode": "0xA1",
"BriefDescription": "False dependencies in MOB due to partial compare.",
"Counter": "0,1,2,3",
"UMask": "0x30",
"AnyThread": "1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"EventCode": "0xA1",
"BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are dispatched to port 4.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"EventCode": "0xA1",
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.",
"Counter": "0,1,2,3",
"UMask": "0x40",
"AnyThread": "1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are dispatched to port 4.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"EventCode": "0xA1",
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when uops are dispatched to port 5.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"EventCode": "0xA1",
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
"Counter": "0,1,2,3",
"UMask": "0x80",
"AnyThread": "1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per core when uops are dispatched to port 5.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0xA2",
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "RESOURCE_STALLS.ANY",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
"SampleAfterValue": "2000003",
"BriefDescription": "Resource-related stall cycles.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0xA2",
"BriefDescription": "Number of Uops delivered by the LSD.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "RESOURCE_STALLS.LB",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the cycles of stall due to lack of load buffers.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0xA2",
"BriefDescription": "Number of machine clears (nukes) of any type.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.COUNT",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"EventCode": "0xA2",
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "RESOURCE_STALLS.SB",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"EventCode": "0xA2",
"BriefDescription": "Self-modifying code (SMC) detected.",
"Counter": "0,1,2,3",
"UMask": "0xa",
"EventName": "RESOURCE_STALLS.LB_SB",
"SampleAfterValue": "2000003",
"BriefDescription": "Resource stalls due to load or store buffers all being in use.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"EventCode": "0xA2",
"BriefDescription": "Retired instructions experiencing ITLB misses.",
"Counter": "0,1,2,3",
"UMask": "0xe",
"EventName": "RESOURCE_STALLS.MEM_RS",
"SampleAfterValue": "2000003",
"BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"EventCode": "0xA2",
"BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "RESOURCE_STALLS.ROB",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles stalled due to re-order buffer full.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x20"
},
{
"EventCode": "0xA2",
"BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
"Counter": "0,1,2,3",
"UMask": "0xf0",
"EventName": "RESOURCE_STALLS.OOO_RSRC",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES",
"PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel 64 and IA-32 Architectures Optimization Reference Manual.",
"SampleAfterValue": "2000003",
"BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x20"
},
{
"EventCode": "0xA3",
"BriefDescription": "Multiply packed/scalar single precision uops allocated.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",
"SampleAfterValue": "2000003",
"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x80"
},
{
"EventCode": "0xA3",
"Counter": "2",
"UMask": "0x2",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
"BriefDescription": "Cycles with at least one slow LEA uop being allocated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",
"PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",
"SampleAfterValue": "2000003",
"BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
"CounterMask": "2",
"CounterHTOff": "2"
"UMask": "0x40"
},
{
"EventCode": "0xA3",
"BriefDescription": "Resource-related stall cycles.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xA3",
"BriefDescription": "Counts the cycles of stall due to lack of load buffers.",
"Counter": "0,1,2,3",
"UMask": "0x5",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LB",
"SampleAfterValue": "2000003",
"BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",
"CounterMask": "5",
"CounterHTOff": "0,1,2,3"
"UMask": "0x2"
},
{
"EventCode": "0xA3",
"Counter": "2",
"UMask": "0x6",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
"BriefDescription": "Resource stalls due to load or store buffers all being in use.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LB_SB",
"SampleAfterValue": "2000003",
"BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
"CounterMask": "6",
"CounterHTOff": "2"
"UMask": "0xa"
},
{
"EventCode": "0xA8",
"BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LSD.UOPS",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MEM_RS",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of Uops delivered by the LSD.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0xe"
},
{
"EventCode": "0xA8",
"BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LSD.CYCLES_ACTIVE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OOO_RSRC",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0xf0"
},
{
"EventCode": "0xA8",
"BriefDescription": "Cycles stalled due to re-order buffer full.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LSD.CYCLES_4_UOPS",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x10"
},
{
"EventCode": "0xB1",
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_DISPATCHED.THREAD",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops dispatched per thread.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x4"
},
{
"EventCode": "0xB1",
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_DISPATCHED.CORE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops dispatched from any thread.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x8"
},
{
"EventCode": "0xB1",
"BriefDescription": "Cycles with either free list is empty.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0xc"
},
{
"EventCode": "0xB1",
"BriefDescription": "Resource stalls2 control structures full for physical registers.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
"CounterMask": "2",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0xf"
},
{
"EventCode": "0xB1",
"BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.BOB_FULL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
"CounterMask": "3",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x40"
},
{
"EventCode": "0xB1",
"BriefDescription": "Resource stalls out of order resources full.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.OOO_RSRC",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x4f"
},
{
"EventCode": "0xB1",
"Invert": "1",
"BriefDescription": "Count cases of saving new LBR.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x20"
},
{
"EventCode": "0xB6",
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "AGU_BYPASS_CANCEL.COUNT",
"SampleAfterValue": "100003",
"BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"EventCode": "0xC0",
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "INST_RETIRED.ANY_P",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_END",
"Invert": "1",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of instructions retired. General Counter - architectural event.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xC0",
"Counter": "1",
"UMask": "0x1",
"EventName": "INST_RETIRED.PREC_DIST",
"BriefDescription": "Uops dispatched from any thread.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_DISPATCHED.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Instructions retired. (Precise Event - PEBS).",
"TakenAlone": "1",
"CounterHTOff": "1"
"UMask": "0x2"
},
{
"EventCode": "0xC1",
"BriefDescription": "Uops dispatched per thread.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED",
"SampleAfterValue": "100003",
"BriefDescription": "Retired instructions experiencing ITLB misses.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_DISPATCHED.THREAD",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"PEBS": "1",
"PublicDescription": "This event counts the number of micro-ops retired. (Precise Event)",
"EventCode": "0xC2",
"BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_RETIRED.ALL",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"SampleAfterValue": "2000003",
"BriefDescription": "Actually retired uops. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0xC2",
"Invert": "1",
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 0.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles without actually retired uops.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xC2",
"Invert": "1",
"BriefDescription": "Cycles per thread when uops are dispatched to port 1.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles with less than 10 actually retired uops.",
"CounterMask": "10",
"CounterHTOff": "0,1,2,3"
"UMask": "0x2"
},
{
"EventCode": "0xC2",
"Invert": "1",
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 1.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles without actually retired uops.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
"UMask": "0x2"
},
{
"PEBS": "1",
"PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS)",
"EventCode": "0xC2",
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"SampleAfterValue": "2000003",
"BriefDescription": "Retirement slots used. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0xc"
},
{
"EventCode": "0xc3",
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EdgeDetect": "1",
"EventName": "MACHINE_CLEARS.COUNT",
"SampleAfterValue": "100003",
"BriefDescription": "Number of machine clears (nukes) of any type.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
"UMask": "0xc"
},
{
"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.",
"EventCode": "0xC3",
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "100003",
"BriefDescription": "Self-modifying code (SMC) detected.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
"EventCode": "0xC3",
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "MACHINE_CLEARS.MASKMOV",
"SampleAfterValue": "100003",
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"EventCode": "0xC4",
"BriefDescription": "Cycles per thread when uops are dispatched to port 4.",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009",
"BriefDescription": "All (macro) branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"SampleAfterValue": "2000003",
"UMask": "0x40"
},
{
"PEBS": "1",
"EventCode": "0xC4",
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 4.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"SampleAfterValue": "400009",
"BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
"UMask": "0x40"
},
{
"PEBS": "1",
"EventCode": "0xC4",
"BriefDescription": "Cycles per thread when uops are dispatched to port 5.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"SampleAfterValue": "100007",
"BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"PEBS": "1",
"EventCode": "0xC4",
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 5.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"SampleAfterValue": "100007",
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"PEBS": "2",
"EventCode": "0xC4",
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"SampleAfterValue": "400009",
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"PEBS": "1",
"EventCode": "0xC4",
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"SampleAfterValue": "100007",
"BriefDescription": "Return instructions retired. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0xC4",
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"SampleAfterValue": "400009",
"BriefDescription": "Not taken branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"PEBS": "1",
"EventCode": "0xC4",
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"SampleAfterValue": "400009",
"BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0xC4",
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"SampleAfterValue": "100007",
"BriefDescription": "Far branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0xC5",
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009",
"BriefDescription": "All mispredicted macro branch instructions retired.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"PEBS": "1",
"EventCode": "0xC5",
"AnyThread": "1",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"SampleAfterValue": "400009",
"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"PEBS": "1",
"EventCode": "0xC5",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"SampleAfterValue": "100007",
"BriefDescription": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"PEBS": "2",
"PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
"EventCode": "0xC5",
"BriefDescription": "Actually retired uops. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"SampleAfterValue": "400009",
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
"PublicDescription": "This event counts the number of micro-ops retired. (Precise Event)",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"PEBS": "1",
"EventCode": "0xC5",
"BriefDescription": "Cycles without actually retired uops.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "BR_MISP_RETIRED.NOT_TAKEN",
"SampleAfterValue": "400009",
"BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"PEBS": "1",
"EventCode": "0xC5",
"BriefDescription": "Retirement slots used. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "BR_MISP_RETIRED.TAKEN",
"SampleAfterValue": "400009",
"BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
"PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS)",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"EventCode": "0xCC",
"BriefDescription": "Cycles without actually retired uops.",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
"Invert": "1",
"SampleAfterValue": "2000003",
"BriefDescription": "Count cases of saving new LBR.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0xE6",
"BriefDescription": "Cycles with less than 10 actually retired uops.",
"Counter": "0,1,2,3",
"UMask": "0x1f",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3",
"CounterMask": "10",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json
View file @ b5948fc6
[
{
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Frontend_Bound",
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
},
{
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Frontend_Bound_SMT",
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Bad_Speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example."
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Bad_Speculation_SMT",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )",
"MetricConstraint": "NO_NMI_WATCHDOG",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )",
"MetricGroup": "TopdownL1",
"MetricName": "Backend_Bound",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound."
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Backend_Bound_SMT",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Retiring",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. "
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. "
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Retiring_SMT",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "TopDownL1",
"MetricGroup": "Ret;Summary",
"MetricName": "IPC"
},
{
"BriefDescription": "Uops Per Instruction",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Retire",
"MetricGroup": "Pipeline;Ret;Retire",
"MetricName": "UPI"
},
{
"BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions",
"MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )",
"MetricGroup": "PGO;IcMiss",
"MetricName": "IFetch_Line_Utilization"
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
"MetricGroup": "DSB;Fetch_BW",
"MetricName": "DSB_Coverage"
},
{
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
"MetricExpr": "1 / (INST_RETIRED.ANY / cycles)",
"MetricGroup": "Pipeline;Summary",
"MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "Pipeline;Mem",
"MetricName": "CPI"
},
{
"BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary",
"MetricGroup": "Pipeline",
"MetricName": "CLKS"
},
{
"BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
"MetricExpr": "4 * cycles",
"MetricGroup": "TopDownL1",
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
"MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "TmaL1",
"MetricName": "SLOTS"
},
{
"BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
"MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopDownL1_SMT",
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
"MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "TmaL1_SMT",
"MetricName": "SLOTS_SMT"
},
{
"BriefDescription": "Total number of retired Instructions",
"MetricExpr": "INST_RETIRED.ANY",
"MetricGroup": "Summary",
"MetricName": "Instructions"
"BriefDescription": "The ratio of Executed- by Issued-Uops",
"MetricExpr": "UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY",
"MetricGroup": "Cor;Pipeline",
"MetricName": "Execute_per_Issue",
"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
},
{
"BriefDescription": "Instructions Per Cycle (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / cycles",
"MetricGroup": "SMT",
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Ret;SMT;TmaL1",
"MetricName": "CoreIPC"
},
{
"BriefDescription": "Instructions Per Cycle (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "SMT",
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "Ret;SMT;TmaL1_SMT",
"MetricName": "CoreIPC_SMT"
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
"MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / cycles",
"MetricGroup": "FLOPS",
"MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Ret;Flops",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
"MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "FLOPS_SMT",
"MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "Ret;Flops_SMT",
"MetricName": "FLOPc_SMT"
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
"MetricExpr": "UOPS_DISPATCHED.THREAD / (( cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)",
"MetricGroup": "Pipeline",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
......@@ -145,16 +135,34 @@
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
{
"BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST",
"MetricExpr": "INST_RETIRED.ANY",
"MetricGroup": "Summary;TmaL1",
"MetricName": "Instructions"
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
{
"BriefDescription": "Average CPU Utilization",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
"MetricGroup": "Summary",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
"MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time",
"MetricGroup": "Summary;Power",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
"MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time",
"MetricGroup": "FLOPS;Summary",
"MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs"
},
{
......@@ -165,22 +173,46 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
"MetricGroup": "SMT;Summary",
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
{
"BriefDescription": "Fraction of cycles spent in Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary",
"BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "OS",
"MetricName": "Kernel_Utilization"
},
{
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
"MetricGroup": "OS",
"MetricName": "Kernel_CPI"
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
"MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000",
"MetricGroup": "Memory_BW",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Request_Latency"
},
{
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Parallel_Requests"
},
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
{
"BriefDescription": "C3 residency percent per core",
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
......
tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json 0 → 100644
View file @ b5948fc6
[
{
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"UMask": "0x86",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
"UMask": "0x88",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"UMask": "0x8f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
"PerPkg": "1",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
"UMask": "0x46",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
"PerPkg": "1",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
"PerPkg": "1",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
"UMask": "0x41",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
"PerPkg": "1",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
"UMask": "0x4f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"UMask": "0x16",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
"UMask": "0x18",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
"UMask": "0x11",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"UMask": "0x1f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"UMask": "0x26",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
"UMask": "0x28",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
"UMask": "0x21",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"UMask": "0x2f",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
"UMask": "0x88",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
"PerPkg": "1",
"PublicDescription": "An external snoop hits a modified line in some processor core.",
"UMask": "0x28",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
"UMask": "0x84",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
"PerPkg": "1",
"PublicDescription": "An external snoop hits a non-modified line in some processor core.",
"UMask": "0x24",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"UMask": "0x44",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
"PerPkg": "1",
"PublicDescription": "An external snoop misses in some processor core.",
"UMask": "0x21",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"UMask": "0x41",
"Unit": "CBO"
}
]
tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json 0 → 100644
View file @ b5948fc6
[
{
"BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
"EventCode": "0x83",
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
"PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
"Counter": "0,1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
"PublicDescription": "Number of requests allocated in Coherency Tracker.",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
"PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"Counter": "0,1",
"CounterMask": "10",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
"PerPkg": "1",
"PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"Counter": "0,1",
"CounterMask": "1",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1",
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of LLC evictions allocated.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
"PerPkg": "1",
"PublicDescription": "Counts the number of LLC evictions allocated.",
"UMask": "0x80",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1",
"PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
"UMask": "0x20",
"Unit": "ARB"
},
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Counter": "Fixed",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"UMask": "0x01",
"Unit": "ARB"
}
]
tools/perf/pmu-events/arch/x86/sandybridge/uncore.json deleted 100644 → 0
View file @ 3f5f0df7
[
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x01",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS",
"BriefDescription": "A snoop misses in some processor core.",
"PublicDescription": "A snoop misses in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x02",
"EventName": "UNC_CBO_XSNP_RESPONSE.INVAL",
"BriefDescription": "A snoop invalidates a non-modified line in some processor core.",
"PublicDescription": "A snoop invalidates a non-modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x04",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT",
"BriefDescription": "A snoop hits a non-modified line in some processor core.",
"PublicDescription": "A snoop hits a non-modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x08",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM",
"BriefDescription": "A snoop hits a modified line in some processor core.",
"PublicDescription": "A snoop hits a modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x10",
"EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M",
"BriefDescription": "A snoop invalidates a modified line in some processor core.",
"PublicDescription": "A snoop invalidates a modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x20",
"EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER",
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x40",
"EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER",
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x80",
"EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER",
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x01",
"EventName": "UNC_CBO_CACHE_LOOKUP.M",
"BriefDescription": "LLC lookup request that access cache and found line in M-state.",
"PublicDescription": "LLC lookup request that access cache and found line in M-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x02",
"EventName": "UNC_CBO_CACHE_LOOKUP.E",
"BriefDescription": "LLC lookup request that access cache and found line in E-state.",
"PublicDescription": "LLC lookup request that access cache and found line in E-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x04",
"EventName": "UNC_CBO_CACHE_LOOKUP.S",
"BriefDescription": "LLC lookup request that access cache and found line in S-state.",
"PublicDescription": "LLC lookup request that access cache and found line in S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x08",
"EventName": "UNC_CBO_CACHE_LOOKUP.I",
"BriefDescription": "LLC lookup request that access cache and found line in I-state.",
"PublicDescription": "LLC lookup request that access cache and found line in I-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x10",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER",
"BriefDescription": "Filter on processor core initiated cacheable read requests.",
"PublicDescription": "Filter on processor core initiated cacheable read requests.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x20",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER",
"BriefDescription": "Filter on processor core initiated cacheable write requests.",
"PublicDescription": "Filter on processor core initiated cacheable write requests.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x40",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER",
"BriefDescription": "Filter on external snoop requests.",
"PublicDescription": "Filter on external snoop requests.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x80",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER",
"BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",
"PublicDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x80",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"Counter": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x81",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x81",
"UMask": "0x20",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
"PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x81",
"UMask": "0x80",
"EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
"BriefDescription": "Counts the number of LLC evictions allocated.",
"PublicDescription": "Counts the number of LLC evictions allocated.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x83",
"UMask": "0x01",
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
"BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
"PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
"Counter": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x84",
"UMask": "0x01",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
"PublicDescription": "Number of requests allocated in Coherency Tracker.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x80",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"Counter": "0,1",
"CounterMask": "1",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x80",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
"BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"Counter": "0,1",
"CounterMask": "10",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x0",
"UMask": "0x01",
"EventName": "UNC_CLOCK.SOCKET",
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Counter": "Fixed",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x06",
"EventName": "UNC_CBO_CACHE_LOOKUP.ES",
"BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.",
"PublicDescription": "LLC lookup request that access cache and found line in E-state or S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
View file @ b5948fc6
[
{
"EventCode": "0x08",
"BriefDescription": "Load misses in all DTLB levels that cause page walks.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Load misses in all DTLB levels that cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
"EventCode": "0x08",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x4"
},
{
"PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
"EventCode": "0x08",
"BriefDescription": "Store misses in all DTLB levels that cause page walks.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0x49",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x10"
},
{
"EventCode": "0x49",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"EventCode": "0x49",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x4"
},
{
"EventCode": "0x49",
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x10"
},
{
"EventCode": "0x85",
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Misses at all ITLB levels that cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"EventCode": "0x85",
"BriefDescription": "Misses at all ITLB levels that cause page walks.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
"EventCode": "0x85",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ITLB_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"EventCode": "0x85",
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "ITLB_MISSES.STLB_HIT",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"EventCode": "0xAE",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB.ITLB_FLUSH",
"SampleAfterValue": "100007",
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"EventCode": "0xBD",
"BriefDescription": "DTLB flush attempts of the thread-specific entries.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"SampleAfterValue": "100007",
"BriefDescription": "DTLB flush attempts of the thread-specific entries.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0xBD",
"BriefDescription": "STLB flush attempts.",
"Counter": "0,1,2,3",
"UMask": "0x20",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"SampleAfterValue": "100007",
"BriefDescription": "STLB flush attempts.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x20"
}
]
\ No newline at end of file
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