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Commit b69337d3 authored by Kevin Hilman's avatar Kevin Hilman
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Merge tag 'clk-meson-v5.4-1' of git://github.com/BayLibre/clk-meson into v5.4/dt64 

Amlogic clock changes for v5.4

* Migrate to new clock description method
* Add DVFS support to g12

# gpg: Signature made Mon 12 Aug 2019 02:11:32 AM PDT
# gpg:                using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85
# gpg: Good signature from "Jerome Brunet <jbrunet@baylibre.com>" [full]
# gpg:                 aka "Jerome Brunet <jerome@liltaz.com>" [full]
# gpg:                 aka "Jerome Brunet <jerome.brunet@gmail.com>" [full]

* tag 'clk-meson-v5.4-1' of git://github.com/BayLibre/clk-meson:
  clk: meson: g12a: expose CPUB clock ID for G12B
  clk: meson: g12a: add notifiers to handle cpu clock change
  clk: meson: add g12a cpu dynamic divider driver
  clk: core: introduce clk_hw_set_parent()
  clk: meson: remove clk input helper
  clk: meson: remove ee input bypass clocks
  clk: meson: clk-regmap: migrate to new parent description method
  clk: meson: meson8b: migrate to the new parent description method
  clk: meson: axg: migrate to the new parent description method
  clk: meson: gxbb: migrate to the new parent description method
  clk: meson: g12a: migrate to the new parent description method
  clk: meson: remove ao input bypass clocks
  clk: meson: axg-aoclk: migrate to the new parent description method
  clk: meson: gxbb-aoclk: migrate to the new parent description method
  clk: meson: g12a-aoclk: migrate to the new parent description method
  clk: meson: axg-audio: migrate to the new parent description method
  clk: meson: g12a: fix hifi typo in mali parent_names
parents e2fb6f7c 1d97657a
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drivers/clk/clk.c
View file @ b69337d3
...@@ -2487,6 +2487,12 @@ static int clk_core_set_parent_nolock(struct clk_core *core, ...@@ -2487,6 +2487,12 @@ static int clk_core_set_parent_nolock(struct clk_core *core,
return ret; return ret;
} }
int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *parent)
{
return clk_core_set_parent_nolock(hw->core, parent->core);
}
EXPORT_SYMBOL_GPL(clk_hw_set_parent);
/** /**
* clk_set_parent - switch the parent of a mux clk * clk_set_parent - switch the parent of a mux clk
* @clk: the mux clk whose input we are switching * @clk: the mux clk whose input we are switching
......
drivers/clk/meson/Kconfig
View file @ b69337d3
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
config COMMON_CLK_MESON_INPUT
tristate
config COMMON_CLK_MESON_REGMAP config COMMON_CLK_MESON_REGMAP
tristate tristate
select REGMAP select REGMAP
...@@ -33,13 +30,15 @@ config COMMON_CLK_MESON_VID_PLL_DIV ...@@ -33,13 +30,15 @@ config COMMON_CLK_MESON_VID_PLL_DIV
config COMMON_CLK_MESON_AO_CLKC config COMMON_CLK_MESON_AO_CLKC
tristate tristate
select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_INPUT
select RESET_CONTROLLER select RESET_CONTROLLER
config COMMON_CLK_MESON_EE_CLKC config COMMON_CLK_MESON_EE_CLKC
tristate tristate
select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_INPUT
config COMMON_CLK_MESON_CPU_DYNDIV
tristate
select COMMON_CLK_MESON_REGMAP
config COMMON_CLK_MESON8B config COMMON_CLK_MESON8B
bool bool
...@@ -86,7 +85,6 @@ config COMMON_CLK_AXG ...@@ -86,7 +85,6 @@ config COMMON_CLK_AXG
config COMMON_CLK_AXG_AUDIO config COMMON_CLK_AXG_AUDIO
tristate "Meson AXG Audio Clock Controller Driver" tristate "Meson AXG Audio Clock Controller Driver"
depends on ARCH_MESON depends on ARCH_MESON
select COMMON_CLK_MESON_INPUT
select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_PHASE select COMMON_CLK_MESON_PHASE
select COMMON_CLK_MESON_SCLK_DIV select COMMON_CLK_MESON_SCLK_DIV
...@@ -104,6 +102,7 @@ config COMMON_CLK_G12A ...@@ -104,6 +102,7 @@ config COMMON_CLK_G12A
select COMMON_CLK_MESON_PLL select COMMON_CLK_MESON_PLL
select COMMON_CLK_MESON_AO_CLKC select COMMON_CLK_MESON_AO_CLKC
select COMMON_CLK_MESON_EE_CLKC select COMMON_CLK_MESON_EE_CLKC
select COMMON_CLK_MESON_CPU_DYNDIV
select MFD_SYSCON select MFD_SYSCON
help help
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2 Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
......
drivers/clk/meson/Makefile
View file @ b69337d3
...@@ -2,9 +2,9 @@ ...@@ -2,9 +2,9 @@
# Amlogic clock drivers # Amlogic clock drivers
obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
obj-$(CONFIG_COMMON_CLK_MESON_INPUT) += clk-input.o
obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
......
drivers/clk/meson/axg-aoclk.c
View file @ b69337d3
...@@ -18,8 +18,6 @@ ...@@ -18,8 +18,6 @@
#include "clk-regmap.h" #include "clk-regmap.h"
#include "clk-dualdiv.h" #include "clk-dualdiv.h"
#define IN_PREFIX "ao-in-"
/* /*
* AO Configuration Clock registers offsets * AO Configuration Clock registers offsets
* Register offsets from the data sheet must be multiplied by 4. * Register offsets from the data sheet must be multiplied by 4.
...@@ -42,7 +40,9 @@ static struct clk_regmap axg_aoclk_##_name = { \ ...@@ -42,7 +40,9 @@ static struct clk_regmap axg_aoclk_##_name = { \
.hw.init = &(struct clk_init_data) { \ .hw.init = &(struct clk_init_data) { \
.name = "axg_ao_" #_name, \ .name = "axg_ao_" #_name, \
.ops = &clk_regmap_gate_ops, \ .ops = &clk_regmap_gate_ops, \
.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \ .parent_data = &(const struct clk_parent_data) { \
.fw_name = "mpeg-clk", \
}, \
.num_parents = 1, \ .num_parents = 1, \
.flags = CLK_IGNORE_UNUSED, \ .flags = CLK_IGNORE_UNUSED, \
}, \ }, \
...@@ -64,7 +64,9 @@ static struct clk_regmap axg_aoclk_cts_oscin = { ...@@ -64,7 +64,9 @@ static struct clk_regmap axg_aoclk_cts_oscin = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_oscin", .name = "cts_oscin",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -77,7 +79,9 @@ static struct clk_regmap axg_aoclk_32k_pre = { ...@@ -77,7 +79,9 @@ static struct clk_regmap axg_aoclk_32k_pre = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axg_ao_32k_pre", .name = "axg_ao_32k_pre",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_oscin" }, .parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_cts_oscin.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -124,7 +128,9 @@ static struct clk_regmap axg_aoclk_32k_div = { ...@@ -124,7 +128,9 @@ static struct clk_regmap axg_aoclk_32k_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axg_ao_32k_div", .name = "axg_ao_32k_div",
.ops = &meson_clk_dualdiv_ops, .ops = &meson_clk_dualdiv_ops,
.parent_names = (const char *[]){ "axg_ao_32k_pre" }, .parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_32k_pre.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -139,8 +145,10 @@ static struct clk_regmap axg_aoclk_32k_sel = { ...@@ -139,8 +145,10 @@ static struct clk_regmap axg_aoclk_32k_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axg_ao_32k_sel", .name = "axg_ao_32k_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "axg_ao_32k_div", .parent_hws = (const struct clk_hw *[]) {
"axg_ao_32k_pre" }, &axg_aoclk_32k_div.hw,
&axg_aoclk_32k_pre.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -154,7 +162,9 @@ static struct clk_regmap axg_aoclk_32k = { ...@@ -154,7 +162,9 @@ static struct clk_regmap axg_aoclk_32k = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axg_ao_32k", .name = "axg_ao_32k",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "axg_ao_32k_sel" }, .parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_32k_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -170,8 +180,10 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin = { ...@@ -170,8 +180,10 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axg_ao_cts_rtc_oscin", .name = "axg_ao_cts_rtc_oscin",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "axg_ao_32k", .parent_data = (const struct clk_parent_data []) {
IN_PREFIX "ext_32k-0" }, { .hw = &axg_aoclk_32k.hw },
{ .fw_name = "ext_32k-0", },
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -187,8 +199,10 @@ static struct clk_regmap axg_aoclk_clk81 = { ...@@ -187,8 +199,10 @@ static struct clk_regmap axg_aoclk_clk81 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axg_ao_clk81", .name = "axg_ao_clk81",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk", .parent_data = (const struct clk_parent_data []) {
"axg_ao_cts_rtc_oscin"}, { .fw_name = "mpeg-clk", },
{ .hw = &axg_aoclk_cts_rtc_oscin.hw },
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -203,8 +217,10 @@ static struct clk_regmap axg_aoclk_saradc_mux = { ...@@ -203,8 +217,10 @@ static struct clk_regmap axg_aoclk_saradc_mux = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axg_ao_saradc_mux", .name = "axg_ao_saradc_mux",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal", .parent_data = (const struct clk_parent_data []) {
"axg_ao_clk81" }, { .fw_name = "xtal", },
{ .hw = &axg_aoclk_clk81.hw },
},
.num_parents = 2, .num_parents = 2,
}, },
}; };
...@@ -218,7 +234,9 @@ static struct clk_regmap axg_aoclk_saradc_div = { ...@@ -218,7 +234,9 @@ static struct clk_regmap axg_aoclk_saradc_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axg_ao_saradc_div", .name = "axg_ao_saradc_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "axg_ao_saradc_mux" }, .parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_saradc_mux.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -232,7 +250,9 @@ static struct clk_regmap axg_aoclk_saradc_gate = { ...@@ -232,7 +250,9 @@ static struct clk_regmap axg_aoclk_saradc_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axg_ao_saradc_gate", .name = "axg_ao_saradc_gate",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "axg_ao_saradc_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_saradc_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -290,12 +310,6 @@ static const struct clk_hw_onecell_data axg_aoclk_onecell_data = { ...@@ -290,12 +310,6 @@ static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
.num = NR_CLKS, .num = NR_CLKS,
}; };
static const struct meson_aoclk_input axg_aoclk_inputs[] = {
{ .name = "xtal", .required = true },
{ .name = "mpeg-clk", .required = true },
{ .name = "ext-32k-0", .required = false },
};
static const struct meson_aoclk_data axg_aoclkc_data = { static const struct meson_aoclk_data axg_aoclkc_data = {
.reset_reg = AO_RTI_GEN_CNTL_REG0, .reset_reg = AO_RTI_GEN_CNTL_REG0,
.num_reset = ARRAY_SIZE(axg_aoclk_reset), .num_reset = ARRAY_SIZE(axg_aoclk_reset),
...@@ -303,9 +317,6 @@ static const struct meson_aoclk_data axg_aoclkc_data = { ...@@ -303,9 +317,6 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
.num_clks = ARRAY_SIZE(axg_aoclk_regmap), .num_clks = ARRAY_SIZE(axg_aoclk_regmap),
.clks = axg_aoclk_regmap, .clks = axg_aoclk_regmap,
.hw_data = &axg_aoclk_onecell_data, .hw_data = &axg_aoclk_onecell_data,
.inputs = axg_aoclk_inputs,
.num_inputs = ARRAY_SIZE(axg_aoclk_inputs),
.input_prefix = IN_PREFIX,
}; };
static const struct of_device_id axg_aoclkc_match_table[] = { static const struct of_device_id axg_aoclkc_match_table[] = {
......
drivers/clk/meson/axg-audio.c
View file @ b69337d3
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
#include <linux/slab.h> #include <linux/slab.h>
#include "axg-audio.h" #include "axg-audio.h"
#include "clk-input.h"
#include "clk-regmap.h" #include "clk-regmap.h"
#include "clk-phase.h" #include "clk-phase.h"
#include "sclk-div.h" #include "sclk-div.h"
...@@ -24,7 +23,7 @@ ...@@ -24,7 +23,7 @@
#define AUD_SLV_SCLK_COUNT 10 #define AUD_SLV_SCLK_COUNT 10
#define AUD_SLV_LRCLK_COUNT 10 #define AUD_SLV_LRCLK_COUNT 10
#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) \ #define AUD_GATE(_name, _reg, _bit, _phws, _iflags) \
struct clk_regmap aud_##_name = { \ struct clk_regmap aud_##_name = { \
.data = &(struct clk_regmap_gate_data){ \ .data = &(struct clk_regmap_gate_data){ \
.offset = (_reg), \ .offset = (_reg), \
...@@ -33,13 +32,13 @@ struct clk_regmap aud_##_name = { \ ...@@ -33,13 +32,13 @@ struct clk_regmap aud_##_name = { \
.hw.init = &(struct clk_init_data) { \ .hw.init = &(struct clk_init_data) { \
.name = "aud_"#_name, \ .name = "aud_"#_name, \
.ops = &clk_regmap_gate_ops, \ .ops = &clk_regmap_gate_ops, \
.parent_names = (const char *[]){ _pname }, \ .parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
.num_parents = 1, \ .num_parents = 1, \
.flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
}, \ }, \
} }
#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \ #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) \
struct clk_regmap aud_##_name = { \ struct clk_regmap aud_##_name = { \
.data = &(struct clk_regmap_mux_data){ \ .data = &(struct clk_regmap_mux_data){ \
.offset = (_reg), \ .offset = (_reg), \
...@@ -50,13 +49,13 @@ struct clk_regmap aud_##_name = { \ ...@@ -50,13 +49,13 @@ struct clk_regmap aud_##_name = { \
.hw.init = &(struct clk_init_data){ \ .hw.init = &(struct clk_init_data){ \
.name = "aud_"#_name, \ .name = "aud_"#_name, \
.ops = &clk_regmap_mux_ops, \ .ops = &clk_regmap_mux_ops, \
.parent_names = (_pnames), \ .parent_data = _pdata, \
.num_parents = ARRAY_SIZE(_pnames), \ .num_parents = ARRAY_SIZE(_pdata), \
.flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
}, \ }, \
} }
#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \ #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags) \
struct clk_regmap aud_##_name = { \ struct clk_regmap aud_##_name = { \
.data = &(struct clk_regmap_div_data){ \ .data = &(struct clk_regmap_div_data){ \
.offset = (_reg), \ .offset = (_reg), \
...@@ -67,15 +66,27 @@ struct clk_regmap aud_##_name = { \ ...@@ -67,15 +66,27 @@ struct clk_regmap aud_##_name = { \
.hw.init = &(struct clk_init_data){ \ .hw.init = &(struct clk_init_data){ \
.name = "aud_"#_name, \ .name = "aud_"#_name, \
.ops = &clk_regmap_divider_ops, \ .ops = &clk_regmap_divider_ops, \
.parent_names = (const char *[]) { _pname }, \ .parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
.num_parents = 1, \ .num_parents = 1, \
.flags = (_iflags), \ .flags = (_iflags), \
}, \ }, \
} }
#define AUD_PCLK_GATE(_name, _bit) \ #define AUD_PCLK_GATE(_name, _bit) \
AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "audio_pclk", 0) struct clk_regmap aud_##_name = { \
.data = &(struct clk_regmap_gate_data){ \
.offset = (AUDIO_CLK_GATE_EN), \
.bit_idx = (_bit), \
}, \
.hw.init = &(struct clk_init_data) { \
.name = "aud_"#_name, \
.ops = &clk_regmap_gate_ops, \
.parent_data = &(const struct clk_parent_data) { \
.fw_name = "pclk", \
}, \
.num_parents = 1, \
}, \
}
/* Audio peripheral clocks */ /* Audio peripheral clocks */
static AUD_PCLK_GATE(ddr_arb, 0); static AUD_PCLK_GATE(ddr_arb, 0);
static AUD_PCLK_GATE(pdm, 1); static AUD_PCLK_GATE(pdm, 1);
...@@ -100,14 +111,20 @@ static AUD_PCLK_GATE(power_detect, 19); ...@@ -100,14 +111,20 @@ static AUD_PCLK_GATE(power_detect, 19);
static AUD_PCLK_GATE(spdifout_b, 21); static AUD_PCLK_GATE(spdifout_b, 21);
/* Audio Master Clocks */ /* Audio Master Clocks */
static const char * const mst_mux_parent_names[] = { static const struct clk_parent_data mst_mux_parent_data[] = {
"aud_mst_in0", "aud_mst_in1", "aud_mst_in2", "aud_mst_in3", { .fw_name = "mst_in0", },
"aud_mst_in4", "aud_mst_in5", "aud_mst_in6", "aud_mst_in7", { .fw_name = "mst_in1", },
{ .fw_name = "mst_in2", },
{ .fw_name = "mst_in3", },
{ .fw_name = "mst_in4", },
{ .fw_name = "mst_in5", },
{ .fw_name = "mst_in6", },
{ .fw_name = "mst_in7", },
}; };
#define AUD_MST_MUX(_name, _reg, _flag) \ #define AUD_MST_MUX(_name, _reg, _flag) \
AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \ AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
mst_mux_parent_names, CLK_SET_RATE_PARENT) mst_mux_parent_data, 0)
#define AUD_MST_MCLK_MUX(_name, _reg) \ #define AUD_MST_MCLK_MUX(_name, _reg) \
AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST) AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
...@@ -129,7 +146,7 @@ static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); ...@@ -129,7 +146,7 @@ static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
#define AUD_MST_DIV(_name, _reg, _flag) \ #define AUD_MST_DIV(_name, _reg, _flag) \
AUD_DIV(_name##_div, _reg, 0, 16, _flag, \ AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
"aud_"#_name"_sel", CLK_SET_RATE_PARENT) \ aud_##_name##_sel, CLK_SET_RATE_PARENT) \
#define AUD_MST_MCLK_DIV(_name, _reg) \ #define AUD_MST_MCLK_DIV(_name, _reg) \
AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST) AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
...@@ -150,7 +167,7 @@ static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); ...@@ -150,7 +167,7 @@ static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
#define AUD_MST_MCLK_GATE(_name, _reg) \ #define AUD_MST_MCLK_GATE(_name, _reg) \
AUD_GATE(_name, _reg, 31, "aud_"#_name"_div", \ AUD_GATE(_name, _reg, 31, aud_##_name##_div, \
CLK_SET_RATE_PARENT) CLK_SET_RATE_PARENT)
static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL); static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
...@@ -168,7 +185,7 @@ static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); ...@@ -168,7 +185,7 @@ static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
/* Sample Clocks */ /* Sample Clocks */
#define AUD_MST_SCLK_PRE_EN(_name, _reg) \ #define AUD_MST_SCLK_PRE_EN(_name, _reg) \
AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \ AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
"aud_mst_"#_name"_mclk", 0) aud_mst_##_name##_mclk, 0)
static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0); static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0); static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
...@@ -178,7 +195,7 @@ static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0); ...@@ -178,7 +195,7 @@ static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0); static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
_hi_shift, _hi_width, _pname, _iflags) \ _hi_shift, _hi_width, _phws, _iflags) \
struct clk_regmap aud_##_name = { \ struct clk_regmap aud_##_name = { \
.data = &(struct meson_sclk_div_data) { \ .data = &(struct meson_sclk_div_data) { \
.div = { \ .div = { \
...@@ -195,7 +212,7 @@ struct clk_regmap aud_##_name = { \ ...@@ -195,7 +212,7 @@ struct clk_regmap aud_##_name = { \
.hw.init = &(struct clk_init_data) { \ .hw.init = &(struct clk_init_data) { \
.name = "aud_"#_name, \ .name = "aud_"#_name, \
.ops = &meson_sclk_div_ops, \ .ops = &meson_sclk_div_ops, \
.parent_names = (const char *[]) { _pname }, \ .parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
.num_parents = 1, \ .num_parents = 1, \
.flags = (_iflags), \ .flags = (_iflags), \
}, \ }, \
...@@ -203,7 +220,7 @@ struct clk_regmap aud_##_name = { \ ...@@ -203,7 +220,7 @@ struct clk_regmap aud_##_name = { \
#define AUD_MST_SCLK_DIV(_name, _reg) \ #define AUD_MST_SCLK_DIV(_name, _reg) \
AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \ AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
"aud_mst_"#_name"_sclk_pre_en", \ aud_mst_##_name##_sclk_pre_en, \
CLK_SET_RATE_PARENT) CLK_SET_RATE_PARENT)
static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
...@@ -214,8 +231,8 @@ static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); ...@@ -214,8 +231,8 @@ static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
#define AUD_MST_SCLK_POST_EN(_name, _reg) \ #define AUD_MST_SCLK_POST_EN(_name, _reg) \
AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \ AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
"aud_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT) aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0); static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0); static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
...@@ -224,8 +241,8 @@ static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0); ...@@ -224,8 +241,8 @@ static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0); static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0); static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
_pname, _iflags) \ _phws, _iflags) \
struct clk_regmap aud_##_name = { \ struct clk_regmap aud_##_name = { \
.data = &(struct meson_clk_triphase_data) { \ .data = &(struct meson_clk_triphase_data) { \
.ph0 = { \ .ph0 = { \
...@@ -247,7 +264,7 @@ struct clk_regmap aud_##_name = { \ ...@@ -247,7 +264,7 @@ struct clk_regmap aud_##_name = { \
.hw.init = &(struct clk_init_data) { \ .hw.init = &(struct clk_init_data) { \
.name = "aud_"#_name, \ .name = "aud_"#_name, \
.ops = &meson_clk_triphase_ops, \ .ops = &meson_clk_triphase_ops, \
.parent_names = (const char *[]) { _pname }, \ .parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
.num_parents = 1, \ .num_parents = 1, \
.flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
}, \ }, \
...@@ -255,7 +272,7 @@ struct clk_regmap aud_##_name = { \ ...@@ -255,7 +272,7 @@ struct clk_regmap aud_##_name = { \
#define AUD_MST_SCLK(_name, _reg) \ #define AUD_MST_SCLK(_name, _reg) \
AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \ AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
"aud_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT) aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1); static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1); static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
...@@ -266,7 +283,7 @@ static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1); ...@@ -266,7 +283,7 @@ static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
#define AUD_MST_LRCLK_DIV(_name, _reg) \ #define AUD_MST_LRCLK_DIV(_name, _reg) \
AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \ AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
"aud_mst_"#_name"_sclk_post_en", 0) \ aud_mst_##_name##_sclk_post_en, 0) \
static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
...@@ -277,7 +294,7 @@ static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); ...@@ -277,7 +294,7 @@ static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
#define AUD_MST_LRCLK(_name, _reg) \ #define AUD_MST_LRCLK(_name, _reg) \
AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \ AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
"aud_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT) aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1); static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1); static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
...@@ -286,19 +303,29 @@ static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1); ...@@ -286,19 +303,29 @@ static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1); static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1); static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
static const char * const tdm_sclk_parent_names[] = { static const struct clk_parent_data tdm_sclk_parent_data[] = {
"aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk", { .hw = &aud_mst_a_sclk.hw, },
"aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk", { .hw = &aud_mst_b_sclk.hw, },
"aud_slv_sclk0", "aud_slv_sclk1", "aud_slv_sclk2", { .hw = &aud_mst_c_sclk.hw, },
"aud_slv_sclk3", "aud_slv_sclk4", "aud_slv_sclk5", { .hw = &aud_mst_d_sclk.hw, },
"aud_slv_sclk6", "aud_slv_sclk7", "aud_slv_sclk8", { .hw = &aud_mst_e_sclk.hw, },
"aud_slv_sclk9" { .hw = &aud_mst_f_sclk.hw, },
{ .fw_name = "slv_sclk0", },
{ .fw_name = "slv_sclk1", },
{ .fw_name = "slv_sclk2", },
{ .fw_name = "slv_sclk3", },
{ .fw_name = "slv_sclk4", },
{ .fw_name = "slv_sclk5", },
{ .fw_name = "slv_sclk6", },
{ .fw_name = "slv_sclk7", },
{ .fw_name = "slv_sclk8", },
{ .fw_name = "slv_sclk9", },
}; };
#define AUD_TDM_SCLK_MUX(_name, _reg) \ #define AUD_TDM_SCLK_MUX(_name, _reg) \
AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \ AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
CLK_MUX_ROUND_CLOSEST, \ CLK_MUX_ROUND_CLOSEST, \
tdm_sclk_parent_names, 0) tdm_sclk_parent_data, 0)
static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL); static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL); static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
...@@ -310,7 +337,7 @@ static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL); ...@@ -310,7 +337,7 @@ static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \ #define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \ AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
"aud_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT) aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
...@@ -322,7 +349,7 @@ static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); ...@@ -322,7 +349,7 @@ static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
#define AUD_TDM_SCLK_POST_EN(_name, _reg) \ #define AUD_TDM_SCLK_POST_EN(_name, _reg) \
AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \ AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
"aud_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT) aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
...@@ -344,8 +371,9 @@ static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); ...@@ -344,8 +371,9 @@ static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
.hw.init = &(struct clk_init_data) { \ .hw.init = &(struct clk_init_data) { \
.name = "aud_tdm"#_name"_sclk", \ .name = "aud_tdm"#_name"_sclk", \
.ops = &meson_clk_phase_ops, \ .ops = &meson_clk_phase_ops, \
.parent_names = (const char *[]) \ .parent_hws = (const struct clk_hw *[]) { \
{ "aud_tdm"#_name"_sclk_post_en" }, \ &aud_tdm##_name##_sclk_post_en.hw \
}, \
.num_parents = 1, \ .num_parents = 1, \
.flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \ .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \
}, \ }, \
...@@ -359,19 +387,29 @@ static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); ...@@ -359,19 +387,29 @@ static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
static const char * const tdm_lrclk_parent_names[] = { static const struct clk_parent_data tdm_lrclk_parent_data[] = {
"aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk", { .hw = &aud_mst_a_lrclk.hw, },
"aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk", { .hw = &aud_mst_b_lrclk.hw, },
"aud_slv_lrclk0", "aud_slv_lrclk1", "aud_slv_lrclk2", { .hw = &aud_mst_c_lrclk.hw, },
"aud_slv_lrclk3", "aud_slv_lrclk4", "aud_slv_lrclk5", { .hw = &aud_mst_d_lrclk.hw, },
"aud_slv_lrclk6", "aud_slv_lrclk7", "aud_slv_lrclk8", { .hw = &aud_mst_e_lrclk.hw, },
"aud_slv_lrclk9" { .hw = &aud_mst_f_lrclk.hw, },
{ .fw_name = "slv_lrclk0", },
{ .fw_name = "slv_lrclk1", },
{ .fw_name = "slv_lrclk2", },
{ .fw_name = "slv_lrclk3", },
{ .fw_name = "slv_lrclk4", },
{ .fw_name = "slv_lrclk5", },
{ .fw_name = "slv_lrclk6", },
{ .fw_name = "slv_lrclk7", },
{ .fw_name = "slv_lrclk8", },
{ .fw_name = "slv_lrclk9", },
}; };
#define AUD_TDM_LRLCK(_name, _reg) \ #define AUD_TDM_LRLCK(_name, _reg) \
AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \ AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
CLK_MUX_ROUND_CLOSEST, \ CLK_MUX_ROUND_CLOSEST, \
tdm_lrclk_parent_names, 0) tdm_lrclk_parent_data, 0)
static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL); static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL); static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
...@@ -386,39 +424,51 @@ static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); ...@@ -386,39 +424,51 @@ static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \ AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \
CLK_SET_RATE_NO_REPARENT) CLK_SET_RATE_NO_REPARENT)
static const char * const mclk_pad_ctrl_parent_names[] = { static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
"aud_mst_a_mclk", "aud_mst_b_mclk", "aud_mst_c_mclk", { .hw = &aud_mst_a_mclk.hw },
"aud_mst_d_mclk", "aud_mst_e_mclk", "aud_mst_f_mclk", { .hw = &aud_mst_b_mclk.hw },
{ .hw = &aud_mst_c_mclk.hw },
{ .hw = &aud_mst_d_mclk.hw },
{ .hw = &aud_mst_e_mclk.hw },
{ .hw = &aud_mst_f_mclk.hw },
}; };
static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,
mclk_pad_ctrl_parent_names); mclk_pad_ctrl_parent_data);
static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,
mclk_pad_ctrl_parent_names); mclk_pad_ctrl_parent_data);
static const char * const lrclk_pad_ctrl_parent_names[] = { static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
"aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk", { .hw = &aud_mst_a_lrclk.hw },
"aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk", { .hw = &aud_mst_b_lrclk.hw },
{ .hw = &aud_mst_c_lrclk.hw },
{ .hw = &aud_mst_d_lrclk.hw },
{ .hw = &aud_mst_e_lrclk.hw },
{ .hw = &aud_mst_f_lrclk.hw },
}; };
static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,
lrclk_pad_ctrl_parent_names); lrclk_pad_ctrl_parent_data);
static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,
lrclk_pad_ctrl_parent_names); lrclk_pad_ctrl_parent_data);
static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,
lrclk_pad_ctrl_parent_names); lrclk_pad_ctrl_parent_data);
static const char * const sclk_pad_ctrl_parent_names[] = { static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
"aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk", { .hw = &aud_mst_a_sclk.hw },
"aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk", { .hw = &aud_mst_b_sclk.hw },
{ .hw = &aud_mst_c_sclk.hw },
{ .hw = &aud_mst_d_sclk.hw },
{ .hw = &aud_mst_e_sclk.hw },
{ .hw = &aud_mst_f_sclk.hw },
}; };
static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,
sclk_pad_ctrl_parent_names); sclk_pad_ctrl_parent_data);
static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,
sclk_pad_ctrl_parent_names); sclk_pad_ctrl_parent_data);
static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
sclk_pad_ctrl_parent_names); sclk_pad_ctrl_parent_data);
/* /*
* Array of all clocks provided by this provider * Array of all clocks provided by this provider
...@@ -868,54 +918,6 @@ static int devm_clk_get_enable(struct device *dev, char *id) ...@@ -868,54 +918,6 @@ static int devm_clk_get_enable(struct device *dev, char *id)
return 0; return 0;
} }
static int axg_register_clk_hw_input(struct device *dev,
const char *name)
{
char *clk_name;
struct clk_hw *hw;
int err = 0;
clk_name = kasprintf(GFP_KERNEL, "aud_%s", name);
if (!clk_name)
return -ENOMEM;
hw = meson_clk_hw_register_input(dev, name, clk_name, 0);
if (IS_ERR(hw)) {
/* It is ok if an input clock is missing */
if (PTR_ERR(hw) == -ENOENT) {
dev_dbg(dev, "%s not provided", name);
} else {
err = PTR_ERR(hw);
if (err != -EPROBE_DEFER)
dev_err(dev, "failed to get %s clock", name);
}
}
kfree(clk_name);
return err;
}
static int axg_register_clk_hw_inputs(struct device *dev,
const char *basename,
unsigned int count)
{
char *name;
int i, ret;
for (i = 0; i < count; i++) {
name = kasprintf(GFP_KERNEL, "%s%d", basename, i);
if (!name)
return -ENOMEM;
ret = axg_register_clk_hw_input(dev, name);
kfree(name);
if (ret)
return ret;
}
return 0;
}
static const struct regmap_config axg_audio_regmap_cfg = { static const struct regmap_config axg_audio_regmap_cfg = {
.reg_bits = 32, .reg_bits = 32,
.val_bits = 32, .val_bits = 32,
...@@ -963,29 +965,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) ...@@ -963,29 +965,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
return ret; return ret;
} }
/* Register the peripheral input clock */
hw = meson_clk_hw_register_input(dev, "pclk", "audio_pclk", 0);
if (IS_ERR(hw))
return PTR_ERR(hw);
/* Register optional input master clocks */
ret = axg_register_clk_hw_inputs(dev, "mst_in",
AUD_MST_IN_COUNT);
if (ret)
return ret;
/* Register optional input slave sclks */
ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
AUD_SLV_SCLK_COUNT);
if (ret)
return ret;
/* Register optional input slave lrclks */
ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
AUD_SLV_LRCLK_COUNT);
if (ret)
return ret;
/* Populate regmap for the regmap backed clocks */ /* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++) for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
aud_clk_regmaps[i]->map = map; aud_clk_regmaps[i]->map = map;
......
drivers/clk/meson/axg.c
View file @ b69337d3
...@@ -14,7 +14,6 @@ ...@@ -14,7 +14,6 @@
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include "clk-input.h"
#include "clk-regmap.h" #include "clk-regmap.h"
#include "clk-pll.h" #include "clk-pll.h"
#include "clk-mpll.h" #include "clk-mpll.h"
...@@ -59,7 +58,9 @@ static struct clk_regmap axg_fixed_pll_dco = { ...@@ -59,7 +58,9 @@ static struct clk_regmap axg_fixed_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fixed_pll_dco", .name = "fixed_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -74,7 +75,9 @@ static struct clk_regmap axg_fixed_pll = { ...@@ -74,7 +75,9 @@ static struct clk_regmap axg_fixed_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fixed_pll", .name = "fixed_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "fixed_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&axg_fixed_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock won't ever change at runtime so * This clock won't ever change at runtime so
...@@ -114,7 +117,9 @@ static struct clk_regmap axg_sys_pll_dco = { ...@@ -114,7 +117,9 @@ static struct clk_regmap axg_sys_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys_pll_dco", .name = "sys_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -129,7 +134,9 @@ static struct clk_regmap axg_sys_pll = { ...@@ -129,7 +134,9 @@ static struct clk_regmap axg_sys_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys_pll", .name = "sys_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "sys_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&axg_sys_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -215,7 +222,9 @@ static struct clk_regmap axg_gp0_pll_dco = { ...@@ -215,7 +222,9 @@ static struct clk_regmap axg_gp0_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp0_pll_dco", .name = "gp0_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -230,7 +239,9 @@ static struct clk_regmap axg_gp0_pll = { ...@@ -230,7 +239,9 @@ static struct clk_regmap axg_gp0_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp0_pll", .name = "gp0_pll",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "gp0_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&axg_gp0_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -284,7 +295,9 @@ static struct clk_regmap axg_hifi_pll_dco = { ...@@ -284,7 +295,9 @@ static struct clk_regmap axg_hifi_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hifi_pll_dco", .name = "hifi_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -299,7 +312,9 @@ static struct clk_regmap axg_hifi_pll = { ...@@ -299,7 +312,9 @@ static struct clk_regmap axg_hifi_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hifi_pll", .name = "hifi_pll",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "hifi_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&axg_hifi_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -311,7 +326,7 @@ static struct clk_fixed_factor axg_fclk_div2_div = { ...@@ -311,7 +326,7 @@ static struct clk_fixed_factor axg_fclk_div2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div2_div", .name = "fclk_div2_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -324,7 +339,9 @@ static struct clk_regmap axg_fclk_div2 = { ...@@ -324,7 +339,9 @@ static struct clk_regmap axg_fclk_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div2", .name = "fclk_div2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div2_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_fclk_div2_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_IS_CRITICAL, .flags = CLK_IS_CRITICAL,
}, },
...@@ -336,7 +353,7 @@ static struct clk_fixed_factor axg_fclk_div3_div = { ...@@ -336,7 +353,7 @@ static struct clk_fixed_factor axg_fclk_div3_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div3_div", .name = "fclk_div3_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -349,7 +366,9 @@ static struct clk_regmap axg_fclk_div3 = { ...@@ -349,7 +366,9 @@ static struct clk_regmap axg_fclk_div3 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div3", .name = "fclk_div3",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div3_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_fclk_div3_div.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* FIXME: * FIXME:
...@@ -372,7 +391,7 @@ static struct clk_fixed_factor axg_fclk_div4_div = { ...@@ -372,7 +391,7 @@ static struct clk_fixed_factor axg_fclk_div4_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div4_div", .name = "fclk_div4_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -385,7 +404,9 @@ static struct clk_regmap axg_fclk_div4 = { ...@@ -385,7 +404,9 @@ static struct clk_regmap axg_fclk_div4 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div4", .name = "fclk_div4",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div4_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_fclk_div4_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -396,7 +417,7 @@ static struct clk_fixed_factor axg_fclk_div5_div = { ...@@ -396,7 +417,7 @@ static struct clk_fixed_factor axg_fclk_div5_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div5_div", .name = "fclk_div5_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -409,7 +430,9 @@ static struct clk_regmap axg_fclk_div5 = { ...@@ -409,7 +430,9 @@ static struct clk_regmap axg_fclk_div5 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div5", .name = "fclk_div5",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div5_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_fclk_div5_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -420,7 +443,9 @@ static struct clk_fixed_factor axg_fclk_div7_div = { ...@@ -420,7 +443,9 @@ static struct clk_fixed_factor axg_fclk_div7_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div7_div", .name = "fclk_div7_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) {
&axg_fixed_pll.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -433,7 +458,9 @@ static struct clk_regmap axg_fclk_div7 = { ...@@ -433,7 +458,9 @@ static struct clk_regmap axg_fclk_div7 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div7", .name = "fclk_div7",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div7_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_fclk_div7_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -447,7 +474,9 @@ static struct clk_regmap axg_mpll_prediv = { ...@@ -447,7 +474,9 @@ static struct clk_regmap axg_mpll_prediv = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll_prediv", .name = "mpll_prediv",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) {
&axg_fixed_pll.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -480,7 +509,9 @@ static struct clk_regmap axg_mpll0_div = { ...@@ -480,7 +509,9 @@ static struct clk_regmap axg_mpll0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0_div", .name = "mpll0_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&axg_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -493,7 +524,9 @@ static struct clk_regmap axg_mpll0 = { ...@@ -493,7 +524,9 @@ static struct clk_regmap axg_mpll0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0", .name = "mpll0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll0_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_mpll0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -527,7 +560,9 @@ static struct clk_regmap axg_mpll1_div = { ...@@ -527,7 +560,9 @@ static struct clk_regmap axg_mpll1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1_div", .name = "mpll1_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&axg_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -540,7 +575,9 @@ static struct clk_regmap axg_mpll1 = { ...@@ -540,7 +575,9 @@ static struct clk_regmap axg_mpll1 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1", .name = "mpll1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll1_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_mpll1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -579,7 +616,9 @@ static struct clk_regmap axg_mpll2_div = { ...@@ -579,7 +616,9 @@ static struct clk_regmap axg_mpll2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2_div", .name = "mpll2_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&axg_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -592,7 +631,9 @@ static struct clk_regmap axg_mpll2 = { ...@@ -592,7 +631,9 @@ static struct clk_regmap axg_mpll2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2", .name = "mpll2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll2_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_mpll2_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -626,7 +667,9 @@ static struct clk_regmap axg_mpll3_div = { ...@@ -626,7 +667,9 @@ static struct clk_regmap axg_mpll3_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll3_div", .name = "mpll3_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&axg_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -639,7 +682,9 @@ static struct clk_regmap axg_mpll3 = { ...@@ -639,7 +682,9 @@ static struct clk_regmap axg_mpll3 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll3", .name = "mpll3",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll3_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_mpll3_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -702,7 +747,9 @@ static struct clk_regmap axg_pcie_pll_dco = { ...@@ -702,7 +747,9 @@ static struct clk_regmap axg_pcie_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcie_pll_dco", .name = "pcie_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -717,7 +764,9 @@ static struct clk_regmap axg_pcie_pll_od = { ...@@ -717,7 +764,9 @@ static struct clk_regmap axg_pcie_pll_od = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcie_pll_od", .name = "pcie_pll_od",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "pcie_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&axg_pcie_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -733,7 +782,9 @@ static struct clk_regmap axg_pcie_pll = { ...@@ -733,7 +782,9 @@ static struct clk_regmap axg_pcie_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcie_pll", .name = "pcie_pll",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "pcie_pll_od" }, .parent_hws = (const struct clk_hw *[]) {
&axg_pcie_pll_od.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -750,7 +801,7 @@ static struct clk_regmap axg_pcie_mux = { ...@@ -750,7 +801,7 @@ static struct clk_regmap axg_pcie_mux = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcie_mux", .name = "pcie_mux",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "pcie_pll" }, .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -767,7 +818,7 @@ static struct clk_regmap axg_pcie_ref = { ...@@ -767,7 +818,7 @@ static struct clk_regmap axg_pcie_ref = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcie_ref", .name = "pcie_ref",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "pcie_mux" }, .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -781,7 +832,7 @@ static struct clk_regmap axg_pcie_cml_en0 = { ...@@ -781,7 +832,7 @@ static struct clk_regmap axg_pcie_cml_en0 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "pcie_cml_en0", .name = "pcie_cml_en0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "pcie_ref" }, .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -796,16 +847,21 @@ static struct clk_regmap axg_pcie_cml_en1 = { ...@@ -796,16 +847,21 @@ static struct clk_regmap axg_pcie_cml_en1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "pcie_cml_en1", .name = "pcie_cml_en1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "pcie_ref" }, .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
static const char * const clk81_parent_names[] = { static const struct clk_parent_data clk81_parent_data[] = {
IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", { .fw_name = "xtal", },
"fclk_div3", "fclk_div5" { .hw = &axg_fclk_div7.hw },
{ .hw = &axg_mpll1.hw },
{ .hw = &axg_mpll2.hw },
{ .hw = &axg_fclk_div4.hw },
{ .hw = &axg_fclk_div3.hw },
{ .hw = &axg_fclk_div5.hw },
}; };
static struct clk_regmap axg_mpeg_clk_sel = { static struct clk_regmap axg_mpeg_clk_sel = {
...@@ -818,8 +874,8 @@ static struct clk_regmap axg_mpeg_clk_sel = { ...@@ -818,8 +874,8 @@ static struct clk_regmap axg_mpeg_clk_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpeg_clk_sel", .name = "mpeg_clk_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = clk81_parent_names, .parent_data = clk81_parent_data,
.num_parents = ARRAY_SIZE(clk81_parent_names), .num_parents = ARRAY_SIZE(clk81_parent_data),
}, },
}; };
...@@ -832,7 +888,9 @@ static struct clk_regmap axg_mpeg_clk_div = { ...@@ -832,7 +888,9 @@ static struct clk_regmap axg_mpeg_clk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div", .name = "mpeg_clk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "mpeg_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&axg_mpeg_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -846,15 +904,20 @@ static struct clk_regmap axg_clk81 = { ...@@ -846,15 +904,20 @@ static struct clk_regmap axg_clk81 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "clk81", .name = "clk81",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpeg_clk_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_mpeg_clk_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
}, },
}; };
static const char * const axg_sd_emmc_clk0_parent_names[] = { static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", { .fw_name = "xtal", },
{ .hw = &axg_fclk_div2.hw },
{ .hw = &axg_fclk_div3.hw },
{ .hw = &axg_fclk_div5.hw },
{ .hw = &axg_fclk_div7.hw },
/* /*
* Following these parent clocks, we should also have had mpll2, mpll3 * Following these parent clocks, we should also have had mpll2, mpll3
* and gp0_pll but these clocks are too precious to be used here. All * and gp0_pll but these clocks are too precious to be used here. All
...@@ -873,8 +936,8 @@ static struct clk_regmap axg_sd_emmc_b_clk0_sel = { ...@@ -873,8 +936,8 @@ static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_sel", .name = "sd_emmc_b_clk0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = axg_sd_emmc_clk0_parent_names, .parent_data = axg_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -889,7 +952,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0_div = { ...@@ -889,7 +952,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_div", .name = "sd_emmc_b_clk0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&axg_sd_emmc_b_clk0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -903,7 +968,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0 = { ...@@ -903,7 +968,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sd_emmc_b_clk0", .name = "sd_emmc_b_clk0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_sd_emmc_b_clk0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -919,8 +986,8 @@ static struct clk_regmap axg_sd_emmc_c_clk0_sel = { ...@@ -919,8 +986,8 @@ static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_sel", .name = "sd_emmc_c_clk0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = axg_sd_emmc_clk0_parent_names, .parent_data = axg_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -935,7 +1002,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0_div = { ...@@ -935,7 +1002,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_div", .name = "sd_emmc_c_clk0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&axg_sd_emmc_c_clk0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -949,7 +1018,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = { ...@@ -949,7 +1018,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sd_emmc_c_clk0", .name = "sd_emmc_c_clk0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_sd_emmc_c_clk0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -957,9 +1028,18 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = { ...@@ -957,9 +1028,18 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
9, 10, 11, 13, 14, }; 9, 10, 11, 13, 14, };
static const char * const gen_clk_parent_names[] = { static const struct clk_parent_data gen_clk_parent_data[] = {
IN_PREFIX "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3", { .fw_name = "xtal", },
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll", { .hw = &axg_hifi_pll.hw },
{ .hw = &axg_mpll0.hw },
{ .hw = &axg_mpll1.hw },
{ .hw = &axg_mpll2.hw },
{ .hw = &axg_mpll3.hw },
{ .hw = &axg_fclk_div4.hw },
{ .hw = &axg_fclk_div3.hw },
{ .hw = &axg_fclk_div5.hw },
{ .hw = &axg_fclk_div7.hw },
{ .hw = &axg_gp0_pll.hw },
}; };
static struct clk_regmap axg_gen_clk_sel = { static struct clk_regmap axg_gen_clk_sel = {
...@@ -978,8 +1058,8 @@ static struct clk_regmap axg_gen_clk_sel = { ...@@ -978,8 +1058,8 @@ static struct clk_regmap axg_gen_clk_sel = {
* hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4, * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
*/ */
.parent_names = gen_clk_parent_names, .parent_data = gen_clk_parent_data,
.num_parents = ARRAY_SIZE(gen_clk_parent_names), .num_parents = ARRAY_SIZE(gen_clk_parent_data),
}, },
}; };
...@@ -992,7 +1072,9 @@ static struct clk_regmap axg_gen_clk_div = { ...@@ -992,7 +1072,9 @@ static struct clk_regmap axg_gen_clk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gen_clk_div", .name = "gen_clk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "gen_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&axg_gen_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1006,12 +1088,17 @@ static struct clk_regmap axg_gen_clk = { ...@@ -1006,12 +1088,17 @@ static struct clk_regmap axg_gen_clk = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gen_clk", .name = "gen_clk",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "gen_clk_div" }, .parent_hws = (const struct clk_hw *[]) {
&axg_gen_clk_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
#define MESON_GATE(_name, _reg, _bit) \
MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
/* Everything Else (EE) domain gates */ /* Everything Else (EE) domain gates */
static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2); static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
......
drivers/clk/meson/clk-cpu-dyndiv.c 0 → 100644
View file @ b69337d3
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include "clk-regmap.h"
#include "clk-cpu-dyndiv.h"
static inline struct meson_clk_cpu_dyndiv_data *
meson_clk_cpu_dyndiv_data(struct clk_regmap *clk)
{
return (struct meson_clk_cpu_dyndiv_data *)clk->data;
}
static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw,
unsigned long prate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
return divider_recalc_rate(hw, prate,
meson_parm_read(clk->map, &data->div),
NULL, 0, data->div.width);
}
static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long *prate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);
}
static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
unsigned int val;
int ret;
ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0);
if (ret < 0)
return ret;
val = (unsigned int)ret << data->div.shift;
/* Write the SYS_CPU_DYN_ENABLE bit before changing the divider */
meson_parm_write(clk->map, &data->dyn, 1);
/* Update the divider while removing the SYS_CPU_DYN_ENABLE bit */
return regmap_update_bits(clk->map, data->div.reg_off,
SETPMASK(data->div.width, data->div.shift) |
SETPMASK(data->dyn.width, data->dyn.shift),
val);
};
const struct clk_ops meson_clk_cpu_dyndiv_ops = {
.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,
.round_rate = meson_clk_cpu_dyndiv_round_rate,
.set_rate = meson_clk_cpu_dyndiv_set_rate,
};
EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);
MODULE_DESCRIPTION("Amlogic CPU Dynamic Clock divider");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_LICENSE("GPL v2");
drivers/clk/meson/clk-cpu-dyndiv.h 0 → 100644
View file @ b69337d3
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef __MESON_CLK_CPU_DYNDIV_H
#define __MESON_CLK_CPU_DYNDIV_H
#include <linux/clk-provider.h>
#include "parm.h"
struct meson_clk_cpu_dyndiv_data {
struct parm div;
struct parm dyn;
};
extern const struct clk_ops meson_clk_cpu_dyndiv_ops;
#endif /* __MESON_CLK_CPU_DYNDIV_H */
drivers/clk/meson/clk-input.c deleted 100644 → 0
View file @ e2fb6f7c
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2018 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/module.h>
#include "clk-input.h"
static const struct clk_ops meson_clk_no_ops = {};
struct clk_hw *meson_clk_hw_register_input(struct device *dev,
const char *of_name,
const char *clk_name,
unsigned long flags)
{
struct clk *parent_clk = devm_clk_get(dev, of_name);
struct clk_init_data init;
const char *parent_name;
struct clk_hw *hw;
int ret;
if (IS_ERR(parent_clk))
return (struct clk_hw *)parent_clk;
hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
if (!hw)
return ERR_PTR(-ENOMEM);
parent_name = __clk_get_name(parent_clk);
init.name = clk_name;
init.ops = &meson_clk_no_ops;
init.flags = flags;
init.parent_names = &parent_name;
init.num_parents = 1;
hw->init = &init;
ret = devm_clk_hw_register(dev, hw);
return ret ? ERR_PTR(ret) : hw;
}
EXPORT_SYMBOL_GPL(meson_clk_hw_register_input);
MODULE_DESCRIPTION("Amlogic clock input helper");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("GPL v2");
drivers/clk/meson/clk-input.h deleted 100644 → 0
View file @ e2fb6f7c
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#ifndef __MESON_CLK_INPUT_H
#define __MESON_CLK_INPUT_H
#include <linux/clk-provider.h>
struct device;
struct clk_hw *meson_clk_hw_register_input(struct device *dev,
const char *of_name,
const char *clk_name,
unsigned long flags);
#endif /* __MESON_CLK_INPUT_H */
drivers/clk/meson/clk-regmap.h
View file @ b69337d3
...@@ -111,7 +111,7 @@ clk_get_regmap_mux_data(struct clk_regmap *clk) ...@@ -111,7 +111,7 @@ clk_get_regmap_mux_data(struct clk_regmap *clk)
extern const struct clk_ops clk_regmap_mux_ops; extern const struct clk_ops clk_regmap_mux_ops;
extern const struct clk_ops clk_regmap_mux_ro_ops; extern const struct clk_ops clk_regmap_mux_ro_ops;
#define __MESON_GATE(_name, _reg, _bit, _ops) \ #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \
struct clk_regmap _name = { \ struct clk_regmap _name = { \
.data = &(struct clk_regmap_gate_data){ \ .data = &(struct clk_regmap_gate_data){ \
.offset = (_reg), \ .offset = (_reg), \
...@@ -120,15 +120,15 @@ struct clk_regmap _name = { \ ...@@ -120,15 +120,15 @@ struct clk_regmap _name = { \
.hw.init = &(struct clk_init_data) { \ .hw.init = &(struct clk_init_data) { \
.name = #_name, \ .name = #_name, \
.ops = _ops, \ .ops = _ops, \
.parent_names = (const char *[]){ "clk81" }, \ .parent_hws = (const struct clk_hw *[]) { _pname }, \
.num_parents = 1, \ .num_parents = 1, \
.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
}, \ }, \
} }
#define MESON_GATE(_name, _reg, _bit) \ #define MESON_PCLK(_name, _reg, _bit, _pname) \
__MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ops) __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
#define MESON_GATE_RO(_name, _reg, _bit) \ #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \
__MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ro_ops) __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
#endif /* __CLK_REGMAP_H */ #endif /* __CLK_REGMAP_H */
drivers/clk/meson/g12a-aoclk.c
View file @ b69337d3
...@@ -18,8 +18,6 @@ ...@@ -18,8 +18,6 @@
#include "clk-regmap.h" #include "clk-regmap.h"
#include "clk-dualdiv.h" #include "clk-dualdiv.h"
#define IN_PREFIX "ao-in-"
/* /*
* AO Configuration Clock registers offsets * AO Configuration Clock registers offsets
* Register offsets from the data sheet must be multiplied by 4. * Register offsets from the data sheet must be multiplied by 4.
...@@ -51,7 +49,9 @@ static struct clk_regmap g12a_aoclk_##_name = { \ ...@@ -51,7 +49,9 @@ static struct clk_regmap g12a_aoclk_##_name = { \
.hw.init = &(struct clk_init_data) { \ .hw.init = &(struct clk_init_data) { \
.name = "g12a_ao_" #_name, \ .name = "g12a_ao_" #_name, \
.ops = &clk_regmap_gate_ops, \ .ops = &clk_regmap_gate_ops, \
.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \ .parent_data = &(const struct clk_parent_data) { \
.fw_name = "mpeg-clk", \
}, \
.num_parents = 1, \ .num_parents = 1, \
.flags = CLK_IGNORE_UNUSED, \ .flags = CLK_IGNORE_UNUSED, \
}, \ }, \
...@@ -81,7 +81,9 @@ static struct clk_regmap g12a_aoclk_cts_oscin = { ...@@ -81,7 +81,9 @@ static struct clk_regmap g12a_aoclk_cts_oscin = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_oscin", .name = "cts_oscin",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -106,7 +108,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = { ...@@ -106,7 +108,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin_pre", .name = "g12a_ao_32k_by_oscin_pre",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_oscin" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cts_oscin.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -143,7 +147,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_div = { ...@@ -143,7 +147,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin_div", .name = "g12a_ao_32k_by_oscin_div",
.ops = &meson_clk_dualdiv_ops, .ops = &meson_clk_dualdiv_ops,
.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_pre" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_32k_by_oscin_pre.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -158,8 +164,10 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = { ...@@ -158,8 +164,10 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin_sel", .name = "g12a_ao_32k_by_oscin_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_div", .parent_hws = (const struct clk_hw *[]) {
"g12a_ao_32k_by_oscin_pre" }, &g12a_aoclk_32k_by_oscin_div.hw,
&g12a_aoclk_32k_by_oscin_pre.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -173,7 +181,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin = { ...@@ -173,7 +181,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin", .name = "g12a_ao_32k_by_oscin",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_32k_by_oscin_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -189,7 +199,9 @@ static struct clk_regmap g12a_aoclk_cec_pre = { ...@@ -189,7 +199,9 @@ static struct clk_regmap g12a_aoclk_cec_pre = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec_pre", .name = "g12a_ao_cec_pre",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_oscin" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cts_oscin.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -226,7 +238,9 @@ static struct clk_regmap g12a_aoclk_cec_div = { ...@@ -226,7 +238,9 @@ static struct clk_regmap g12a_aoclk_cec_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec_div", .name = "g12a_ao_cec_div",
.ops = &meson_clk_dualdiv_ops, .ops = &meson_clk_dualdiv_ops,
.parent_names = (const char *[]){ "g12a_ao_cec_pre" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cec_pre.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -241,8 +255,10 @@ static struct clk_regmap g12a_aoclk_cec_sel = { ...@@ -241,8 +255,10 @@ static struct clk_regmap g12a_aoclk_cec_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec_sel", .name = "g12a_ao_cec_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "g12a_ao_cec_div", .parent_hws = (const struct clk_hw *[]) {
"g12a_ao_cec_pre" }, &g12a_aoclk_cec_div.hw,
&g12a_aoclk_cec_pre.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -256,7 +272,9 @@ static struct clk_regmap g12a_aoclk_cec = { ...@@ -256,7 +272,9 @@ static struct clk_regmap g12a_aoclk_cec = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec", .name = "g12a_ao_cec",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "g12a_ao_cec_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cec_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -272,8 +290,10 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin = { ...@@ -272,8 +290,10 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_cts_rtc_oscin", .name = "g12a_ao_cts_rtc_oscin",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin", .parent_data = (const struct clk_parent_data []) {
IN_PREFIX "ext_32k-0" }, { .hw = &g12a_aoclk_32k_by_oscin.hw },
{ .fw_name = "ext-32k-0", },
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -289,8 +309,10 @@ static struct clk_regmap g12a_aoclk_clk81 = { ...@@ -289,8 +309,10 @@ static struct clk_regmap g12a_aoclk_clk81 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_clk81", .name = "g12a_ao_clk81",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk", .parent_data = (const struct clk_parent_data []) {
"g12a_ao_cts_rtc_oscin"}, { .fw_name = "mpeg-clk", },
{ .hw = &g12a_aoclk_cts_rtc_oscin.hw },
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -305,8 +327,10 @@ static struct clk_regmap g12a_aoclk_saradc_mux = { ...@@ -305,8 +327,10 @@ static struct clk_regmap g12a_aoclk_saradc_mux = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_saradc_mux", .name = "g12a_ao_saradc_mux",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal", .parent_data = (const struct clk_parent_data []) {
"g12a_ao_clk81" }, { .fw_name = "xtal", },
{ .hw = &g12a_aoclk_clk81.hw },
},
.num_parents = 2, .num_parents = 2,
}, },
}; };
...@@ -320,7 +344,9 @@ static struct clk_regmap g12a_aoclk_saradc_div = { ...@@ -320,7 +344,9 @@ static struct clk_regmap g12a_aoclk_saradc_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_saradc_div", .name = "g12a_ao_saradc_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "g12a_ao_saradc_mux" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_saradc_mux.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -334,7 +360,9 @@ static struct clk_regmap g12a_aoclk_saradc_gate = { ...@@ -334,7 +360,9 @@ static struct clk_regmap g12a_aoclk_saradc_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "g12a_ao_saradc_gate", .name = "g12a_ao_saradc_gate",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "g12a_ao_saradc_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_saradc_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -417,12 +445,6 @@ static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = { ...@@ -417,12 +445,6 @@ static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
.num = NR_CLKS, .num = NR_CLKS,
}; };
static const struct meson_aoclk_input g12a_aoclk_inputs[] = {
{ .name = "xtal", .required = true },
{ .name = "mpeg-clk", .required = true },
{ .name = "ext-32k-0", .required = false },
};
static const struct meson_aoclk_data g12a_aoclkc_data = { static const struct meson_aoclk_data g12a_aoclkc_data = {
.reset_reg = AO_RTI_GEN_CNTL_REG0, .reset_reg = AO_RTI_GEN_CNTL_REG0,
.num_reset = ARRAY_SIZE(g12a_aoclk_reset), .num_reset = ARRAY_SIZE(g12a_aoclk_reset),
...@@ -430,9 +452,6 @@ static const struct meson_aoclk_data g12a_aoclkc_data = { ...@@ -430,9 +452,6 @@ static const struct meson_aoclk_data g12a_aoclkc_data = {
.num_clks = ARRAY_SIZE(g12a_aoclk_regmap), .num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
.clks = g12a_aoclk_regmap, .clks = g12a_aoclk_regmap,
.hw_data = &g12a_aoclk_onecell_data, .hw_data = &g12a_aoclk_onecell_data,
.inputs = g12a_aoclk_inputs,
.num_inputs = ARRAY_SIZE(g12a_aoclk_inputs),
.input_prefix = IN_PREFIX,
}; };
static const struct of_device_id g12a_aoclkc_match_table[] = { static const struct of_device_id g12a_aoclkc_match_table[] = {
......
drivers/clk/meson/g12a.c
View file @ b69337d3
...@@ -14,11 +14,12 @@ ...@@ -14,11 +14,12 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/clk.h>
#include "clk-input.h"
#include "clk-mpll.h" #include "clk-mpll.h"
#include "clk-pll.h" #include "clk-pll.h"
#include "clk-regmap.h" #include "clk-regmap.h"
#include "clk-cpu-dyndiv.h"
#include "vid-pll-div.h" #include "vid-pll-div.h"
#include "meson-eeclk.h" #include "meson-eeclk.h"
#include "g12a.h" #include "g12a.h"
...@@ -61,7 +62,9 @@ static struct clk_regmap g12a_fixed_pll_dco = { ...@@ -61,7 +62,9 @@ static struct clk_regmap g12a_fixed_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fixed_pll_dco", .name = "fixed_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -76,7 +79,9 @@ static struct clk_regmap g12a_fixed_pll = { ...@@ -76,7 +79,9 @@ static struct clk_regmap g12a_fixed_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fixed_pll", .name = "fixed_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "fixed_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_fixed_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock won't ever change at runtime so * This clock won't ever change at runtime so
...@@ -85,16 +90,9 @@ static struct clk_regmap g12a_fixed_pll = { ...@@ -85,16 +90,9 @@ static struct clk_regmap g12a_fixed_pll = {
}, },
}; };
/* static const struct pll_mult_range g12a_sys_pll_mult_range = {
* Internal sys pll emulation configuration parameters .min = 128,
*/ .max = 250,
static const struct reg_sequence g12a_sys_init_regs[] = {
{ .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 },
{ .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 },
{ .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
{ .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
{ .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
{ .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000 },
}; };
static struct clk_regmap g12a_sys_pll_dco = { static struct clk_regmap g12a_sys_pll_dco = {
...@@ -124,14 +122,17 @@ static struct clk_regmap g12a_sys_pll_dco = { ...@@ -124,14 +122,17 @@ static struct clk_regmap g12a_sys_pll_dco = {
.shift = 29, .shift = 29,
.width = 1, .width = 1,
}, },
.init_regs = g12a_sys_init_regs, .range = &g12a_sys_pll_mult_range,
.init_count = ARRAY_SIZE(g12a_sys_init_regs),
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys_pll_dco", .name = "sys_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
/* This clock feeds the CPU, avoid disabling it */
.flags = CLK_IS_CRITICAL,
}, },
}; };
...@@ -144,9 +145,12 @@ static struct clk_regmap g12a_sys_pll = { ...@@ -144,9 +145,12 @@ static struct clk_regmap g12a_sys_pll = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys_pll", .name = "sys_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sys_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_sys_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -177,12 +181,17 @@ static struct clk_regmap g12b_sys1_pll_dco = { ...@@ -177,12 +181,17 @@ static struct clk_regmap g12b_sys1_pll_dco = {
.shift = 29, .shift = 29,
.width = 1, .width = 1,
}, },
.range = &g12a_sys_pll_mult_range,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys1_pll_dco", .name = "sys1_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
/* This clock feeds the CPU, avoid disabling it */
.flags = CLK_IS_CRITICAL,
}, },
}; };
...@@ -195,9 +204,12 @@ static struct clk_regmap g12b_sys1_pll = { ...@@ -195,9 +204,12 @@ static struct clk_regmap g12b_sys1_pll = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys1_pll", .name = "sys1_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sys1_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_sys1_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -209,7 +221,7 @@ static struct clk_regmap g12a_sys_pll_div16_en = { ...@@ -209,7 +221,7 @@ static struct clk_regmap g12a_sys_pll_div16_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sys_pll_div16_en", .name = "sys_pll_div16_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "sys_pll" }, .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is used to debug the sys_pll range * This clock is used to debug the sys_pll range
...@@ -226,7 +238,9 @@ static struct clk_regmap g12b_sys1_pll_div16_en = { ...@@ -226,7 +238,9 @@ static struct clk_regmap g12b_sys1_pll_div16_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sys1_pll_div16_en", .name = "sys1_pll_div16_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "sys1_pll" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_sys1_pll.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is used to debug the sys_pll range * This clock is used to debug the sys_pll range
...@@ -241,7 +255,9 @@ static struct clk_fixed_factor g12a_sys_pll_div16 = { ...@@ -241,7 +255,9 @@ static struct clk_fixed_factor g12a_sys_pll_div16 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys_pll_div16", .name = "sys_pll_div16",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "sys_pll_div16_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_sys_pll_div16_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -252,11 +268,75 @@ static struct clk_fixed_factor g12b_sys1_pll_div16 = { ...@@ -252,11 +268,75 @@ static struct clk_fixed_factor g12b_sys1_pll_div16 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys1_pll_div16", .name = "sys1_pll_div16",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "sys1_pll_div16_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_sys1_pll_div16_en.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor g12a_fclk_div2_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "fclk_div2_div",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
.num_parents = 1,
},
};
static struct clk_regmap g12a_fclk_div2 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_FIX_PLL_CNTL1,
.bit_idx = 24,
},
.hw.init = &(struct clk_init_data){
.name = "fclk_div2",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_fclk_div2_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_fixed_factor g12a_fclk_div3_div = {
.mult = 1,
.div = 3,
.hw.init = &(struct clk_init_data){
.name = "fclk_div3_div",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
.num_parents = 1,
},
};
static struct clk_regmap g12a_fclk_div3 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_FIX_PLL_CNTL1,
.bit_idx = 20,
},
.hw.init = &(struct clk_init_data){
.name = "fclk_div3",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_fclk_div3_div.hw
},
.num_parents = 1,
/*
* This clock is used by the resident firmware and is required
* by the platform to operate correctly.
* Until the following condition are met, we need this clock to
* be marked as critical:
* a) Mark the clock used by a firmware resource, if possible
* b) CCF has a clock hand-off mechanism to make the sure the
* clock stays on until the proper driver comes along
*/
.flags = CLK_IS_CRITICAL,
},
};
/* Datasheet names this field as "premux0" */ /* Datasheet names this field as "premux0" */
static struct clk_regmap g12a_cpu_clk_premux0 = { static struct clk_regmap g12a_cpu_clk_premux0 = {
.data = &(struct clk_regmap_mux_data){ .data = &(struct clk_regmap_mux_data){
...@@ -266,26 +346,61 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { ...@@ -266,26 +346,61 @@ static struct clk_regmap g12a_cpu_clk_premux0 = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn0_sel", .name = "cpu_clk_dyn0_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal", .parent_data = (const struct clk_parent_data []) {
"fclk_div2", { .fw_name = "xtal", },
"fclk_div3" }, { .hw = &g12a_fclk_div2.hw },
{ .hw = &g12a_fclk_div3.hw },
},
.num_parents = 3, .num_parents = 3,
/* This sub-tree is used a parking clock */
.flags = CLK_SET_RATE_NO_REPARENT,
},
};
/* Datasheet names this field as "premux1" */
static struct clk_regmap g12a_cpu_clk_premux1 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL0,
.mask = 0x3,
.shift = 16,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn1_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal", },
{ .hw = &g12a_fclk_div2.hw },
{ .hw = &g12a_fclk_div3.hw },
},
.num_parents = 3,
/* This sub-tree is used a parking clock */
.flags = CLK_SET_RATE_NO_REPARENT
}, },
}; };
/* Datasheet names this field as "mux0_divn_tcnt" */ /* Datasheet names this field as "mux0_divn_tcnt" */
static struct clk_regmap g12a_cpu_clk_mux0_div = { static struct clk_regmap g12a_cpu_clk_mux0_div = {
.data = &(struct clk_regmap_div_data){ .data = &(struct meson_clk_cpu_dyndiv_data){
.offset = HHI_SYS_CPU_CLK_CNTL0, .div = {
.shift = 4, .reg_off = HHI_SYS_CPU_CLK_CNTL0,
.width = 6, .shift = 4,
.width = 6,
},
.dyn = {
.reg_off = HHI_SYS_CPU_CLK_CNTL0,
.shift = 26,
.width = 1,
},
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn0_div", .name = "cpu_clk_dyn0_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &meson_clk_cpu_dyndiv_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cpu_clk_premux0.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -298,27 +413,13 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = { ...@@ -298,27 +413,13 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn0", .name = "cpu_clk_dyn0",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn0_sel", .parent_hws = (const struct clk_hw *[]) {
"cpu_clk_dyn0_div" }, &g12a_cpu_clk_premux0.hw,
&g12a_cpu_clk_mux0_div.hw,
},
.num_parents = 2, .num_parents = 2,
}, .flags = CLK_SET_RATE_PARENT,
};
/* Datasheet names this field as "premux1" */
static struct clk_regmap g12a_cpu_clk_premux1 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL0,
.mask = 0x3,
.shift = 16,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn1_sel",
.ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal",
"fclk_div2",
"fclk_div3" },
.num_parents = 3,
}, },
}; };
...@@ -332,7 +433,9 @@ static struct clk_regmap g12a_cpu_clk_mux1_div = { ...@@ -332,7 +433,9 @@ static struct clk_regmap g12a_cpu_clk_mux1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn1_div", .name = "cpu_clk_dyn1_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cpu_clk_premux1.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -346,10 +449,14 @@ static struct clk_regmap g12a_cpu_clk_postmux1 = { ...@@ -346,10 +449,14 @@ static struct clk_regmap g12a_cpu_clk_postmux1 = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn1", .name = "cpu_clk_dyn1",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn1_sel", .parent_hws = (const struct clk_hw *[]) {
"cpu_clk_dyn1_div" }, &g12a_cpu_clk_premux1.hw,
&g12a_cpu_clk_mux1_div.hw,
},
.num_parents = 2, .num_parents = 2,
/* This sub-tree is used a parking clock */
.flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -362,10 +469,13 @@ static struct clk_regmap g12a_cpu_clk_dyn = { ...@@ -362,10 +469,13 @@ static struct clk_regmap g12a_cpu_clk_dyn = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn", .name = "cpu_clk_dyn",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn0", .parent_hws = (const struct clk_hw *[]) {
"cpu_clk_dyn1" }, &g12a_cpu_clk_postmux0.hw,
&g12a_cpu_clk_postmux1.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -378,10 +488,13 @@ static struct clk_regmap g12a_cpu_clk = { ...@@ -378,10 +488,13 @@ static struct clk_regmap g12a_cpu_clk = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk", .name = "cpu_clk",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn", .parent_hws = (const struct clk_hw *[]) {
"sys_pll" }, &g12a_cpu_clk_dyn.hw,
&g12a_sys_pll.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -394,10 +507,13 @@ static struct clk_regmap g12b_cpu_clk = { ...@@ -394,10 +507,13 @@ static struct clk_regmap g12b_cpu_clk = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk", .name = "cpu_clk",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn", .parent_hws = (const struct clk_hw *[]) {
"sys1_pll" }, &g12a_cpu_clk_dyn.hw,
&g12b_sys1_pll.hw
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -410,26 +526,38 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { ...@@ -410,26 +526,38 @@ static struct clk_regmap g12b_cpub_clk_premux0 = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_dyn0_sel", .name = "cpub_clk_dyn0_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal", .parent_data = (const struct clk_parent_data []) {
"fclk_div2", { .fw_name = "xtal", },
"fclk_div3" }, { .hw = &g12a_fclk_div2.hw },
{ .hw = &g12a_fclk_div3.hw },
},
.num_parents = 3, .num_parents = 3,
}, },
}; };
/* Datasheet names this field as "mux0_divn_tcnt" */ /* Datasheet names this field as "mux0_divn_tcnt" */
static struct clk_regmap g12b_cpub_clk_mux0_div = { static struct clk_regmap g12b_cpub_clk_mux0_div = {
.data = &(struct clk_regmap_div_data){ .data = &(struct meson_clk_cpu_dyndiv_data){
.offset = HHI_SYS_CPUB_CLK_CNTL, .div = {
.shift = 4, .reg_off = HHI_SYS_CPUB_CLK_CNTL,
.width = 6, .shift = 4,
.width = 6,
},
.dyn = {
.reg_off = HHI_SYS_CPUB_CLK_CNTL,
.shift = 26,
.width = 1,
},
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_dyn0_div", .name = "cpub_clk_dyn0_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &meson_clk_cpu_dyndiv_ops,
.parent_names = (const char *[]){ "cpub_clk_dyn0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk_premux0.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -442,10 +570,13 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = { ...@@ -442,10 +570,13 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_dyn0", .name = "cpub_clk_dyn0",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpub_clk_dyn0_sel", .parent_hws = (const struct clk_hw *[]) {
"cpub_clk_dyn0_div" }, &g12b_cpub_clk_premux0.hw,
&g12b_cpub_clk_mux0_div.hw
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -458,11 +589,15 @@ static struct clk_regmap g12b_cpub_clk_premux1 = { ...@@ -458,11 +589,15 @@ static struct clk_regmap g12b_cpub_clk_premux1 = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_dyn1_sel", .name = "cpub_clk_dyn1_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal", .parent_data = (const struct clk_parent_data []) {
"fclk_div2", { .fw_name = "xtal", },
"fclk_div3" }, { .hw = &g12a_fclk_div2.hw },
{ .hw = &g12a_fclk_div3.hw },
},
.num_parents = 3, .num_parents = 3,
/* This sub-tree is used a parking clock */
.flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -476,7 +611,9 @@ static struct clk_regmap g12b_cpub_clk_mux1_div = { ...@@ -476,7 +611,9 @@ static struct clk_regmap g12b_cpub_clk_mux1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_dyn1_div", .name = "cpub_clk_dyn1_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpub_clk_dyn1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk_premux1.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -490,10 +627,14 @@ static struct clk_regmap g12b_cpub_clk_postmux1 = { ...@@ -490,10 +627,14 @@ static struct clk_regmap g12b_cpub_clk_postmux1 = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_dyn1", .name = "cpub_clk_dyn1",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpub_clk_dyn1_sel", .parent_hws = (const struct clk_hw *[]) {
"cpub_clk_dyn1_div" }, &g12b_cpub_clk_premux1.hw,
&g12b_cpub_clk_mux1_div.hw
},
.num_parents = 2, .num_parents = 2,
/* This sub-tree is used a parking clock */
.flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -506,10 +647,13 @@ static struct clk_regmap g12b_cpub_clk_dyn = { ...@@ -506,10 +647,13 @@ static struct clk_regmap g12b_cpub_clk_dyn = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_dyn", .name = "cpub_clk_dyn",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpub_clk_dyn0", .parent_hws = (const struct clk_hw *[]) {
"cpub_clk_dyn1" }, &g12b_cpub_clk_postmux0.hw,
&g12b_cpub_clk_postmux1.hw
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -522,13 +666,227 @@ static struct clk_regmap g12b_cpub_clk = { ...@@ -522,13 +666,227 @@ static struct clk_regmap g12b_cpub_clk = {
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk", .name = "cpub_clk",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpub_clk_dyn", .parent_hws = (const struct clk_hw *[]) {
"sys_pll" }, &g12b_cpub_clk_dyn.hw,
&g12a_sys_pll.hw
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
/* Wait for clock propagation before/after changing the mux */
udelay(100);
return NOTIFY_OK;
}
return NOTIFY_DONE;
}
static struct notifier_block g12a_cpu_clk_mux_nb = {
.notifier_call = g12a_cpu_clk_mux_notifier_cb,
};
struct g12a_cpu_clk_postmux_nb_data {
struct notifier_block nb;
struct clk_hw *xtal;
struct clk_hw *cpu_clk_dyn;
struct clk_hw *cpu_clk_postmux0;
struct clk_hw *cpu_clk_postmux1;
struct clk_hw *cpu_clk_premux1;
};
static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct g12a_cpu_clk_postmux_nb_data *nb_data =
container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
switch (event) {
case PRE_RATE_CHANGE:
/*
* This notifier means cpu_clk_postmux0 clock will be changed
* to feed cpu_clk, this is the current path :
* cpu_clk
* \- cpu_clk_dyn
* \- cpu_clk_postmux0
* \- cpu_clk_muxX_div
* \- cpu_clk_premux0
* \- fclk_div3 or fclk_div2
* OR
* \- cpu_clk_premux0
* \- fclk_div3 or fclk_div2
*/
/* Setup cpu_clk_premux1 to xtal */
clk_hw_set_parent(nb_data->cpu_clk_premux1,
nb_data->xtal);
/* Setup cpu_clk_postmux1 to bypass divider */
clk_hw_set_parent(nb_data->cpu_clk_postmux1,
nb_data->cpu_clk_premux1);
/* Switch to parking clk on cpu_clk_postmux1 */
clk_hw_set_parent(nb_data->cpu_clk_dyn,
nb_data->cpu_clk_postmux1);
/*
* Now, cpu_clk is 24MHz in the current path :
* cpu_clk
* \- cpu_clk_dyn
* \- cpu_clk_postmux1
* \- cpu_clk_premux1
* \- xtal
*/
udelay(100);
return NOTIFY_OK;
case POST_RATE_CHANGE:
/*
* The cpu_clk_postmux0 has ben updated, now switch back
* cpu_clk_dyn to cpu_clk_postmux0 and take the changes
* in account.
*/
/* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
clk_hw_set_parent(nb_data->cpu_clk_dyn,
nb_data->cpu_clk_postmux0);
/*
* new path :
* cpu_clk
* \- cpu_clk_dyn
* \- cpu_clk_postmux0
* \- cpu_clk_muxX_div
* \- cpu_clk_premux0
* \- fclk_div3 or fclk_div2
* OR
* \- cpu_clk_premux0
* \- fclk_div3 or fclk_div2
*/
udelay(100);
return NOTIFY_OK;
default:
return NOTIFY_DONE;
}
}
static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
.cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
.cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
.cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
};
static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
.cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
.cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
.cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
};
struct g12a_sys_pll_nb_data {
struct notifier_block nb;
struct clk_hw *sys_pll;
struct clk_hw *cpu_clk;
struct clk_hw *cpu_clk_dyn;
};
static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct g12a_sys_pll_nb_data *nb_data =
container_of(nb, struct g12a_sys_pll_nb_data, nb);
switch (event) {
case PRE_RATE_CHANGE:
/*
* This notifier means sys_pll clock will be changed
* to feed cpu_clk, this the current path :
* cpu_clk
* \- sys_pll
* \- sys_pll_dco
*/
/* Configure cpu_clk to use cpu_clk_dyn */
clk_hw_set_parent(nb_data->cpu_clk,
nb_data->cpu_clk_dyn);
/*
* Now, cpu_clk uses the dyn path
* cpu_clk
* \- cpu_clk_dyn
* \- cpu_clk_dynX
* \- cpu_clk_dynX_sel
* \- cpu_clk_dynX_div
* \- xtal/fclk_div2/fclk_div3
* \- xtal/fclk_div2/fclk_div3
*/
udelay(100);
return NOTIFY_OK;
case POST_RATE_CHANGE:
/*
* The sys_pll has ben updated, now switch back cpu_clk to
* sys_pll
*/
/* Configure cpu_clk to use sys_pll */
clk_hw_set_parent(nb_data->cpu_clk,
nb_data->sys_pll);
udelay(100);
/* new path :
* cpu_clk
* \- sys_pll
* \- sys_pll_dco
*/
return NOTIFY_OK;
default:
return NOTIFY_DONE;
}
}
static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
.sys_pll = &g12a_sys_pll.hw,
.cpu_clk = &g12a_cpu_clk.hw,
.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
.nb.notifier_call = g12a_sys_pll_notifier_cb,
};
/* G12B first CPU cluster uses sys1_pll */
static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
.sys_pll = &g12b_sys1_pll.hw,
.cpu_clk = &g12b_cpu_clk.hw,
.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
.nb.notifier_call = g12a_sys_pll_notifier_cb,
};
/* G12B second CPU cluster uses sys_pll */
static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
.sys_pll = &g12a_sys_pll.hw,
.cpu_clk = &g12b_cpub_clk.hw,
.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
.nb.notifier_call = g12a_sys_pll_notifier_cb,
};
static struct clk_regmap g12a_cpu_clk_div16_en = { static struct clk_regmap g12a_cpu_clk_div16_en = {
.data = &(struct clk_regmap_gate_data){ .data = &(struct clk_regmap_gate_data){
.offset = HHI_SYS_CPU_CLK_CNTL1, .offset = HHI_SYS_CPU_CLK_CNTL1,
...@@ -537,7 +895,9 @@ static struct clk_regmap g12a_cpu_clk_div16_en = { ...@@ -537,7 +895,9 @@ static struct clk_regmap g12a_cpu_clk_div16_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cpu_clk_div16_en", .name = "cpu_clk_div16_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cpu_clk.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is used to debug the cpu_clk range * This clock is used to debug the cpu_clk range
...@@ -554,7 +914,9 @@ static struct clk_regmap g12b_cpub_clk_div16_en = { ...@@ -554,7 +914,9 @@ static struct clk_regmap g12b_cpub_clk_div16_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cpub_clk_div16_en", .name = "cpub_clk_div16_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpub_clk" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is used to debug the cpu_clk range * This clock is used to debug the cpu_clk range
...@@ -569,7 +931,9 @@ static struct clk_fixed_factor g12a_cpu_clk_div16 = { ...@@ -569,7 +931,9 @@ static struct clk_fixed_factor g12a_cpu_clk_div16 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_div16", .name = "cpu_clk_div16",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_clk_div16_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cpu_clk_div16_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -580,7 +944,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div16 = { ...@@ -580,7 +944,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div16 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_div16", .name = "cpub_clk_div16",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpub_clk_div16_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk_div16_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -595,7 +961,7 @@ static struct clk_regmap g12a_cpu_clk_apb_div = { ...@@ -595,7 +961,7 @@ static struct clk_regmap g12a_cpu_clk_apb_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_apb_div", .name = "cpu_clk_apb_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -608,7 +974,9 @@ static struct clk_regmap g12a_cpu_clk_apb = { ...@@ -608,7 +974,9 @@ static struct clk_regmap g12a_cpu_clk_apb = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cpu_clk_apb", .name = "cpu_clk_apb",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_apb_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cpu_clk_apb_div.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is set by the ROM monitor code, * This clock is set by the ROM monitor code,
...@@ -627,7 +995,7 @@ static struct clk_regmap g12a_cpu_clk_atb_div = { ...@@ -627,7 +995,7 @@ static struct clk_regmap g12a_cpu_clk_atb_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_atb_div", .name = "cpu_clk_atb_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -640,7 +1008,9 @@ static struct clk_regmap g12a_cpu_clk_atb = { ...@@ -640,7 +1008,9 @@ static struct clk_regmap g12a_cpu_clk_atb = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cpu_clk_atb", .name = "cpu_clk_atb",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_atb_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cpu_clk_atb_div.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is set by the ROM monitor code, * This clock is set by the ROM monitor code,
...@@ -659,7 +1029,7 @@ static struct clk_regmap g12a_cpu_clk_axi_div = { ...@@ -659,7 +1029,7 @@ static struct clk_regmap g12a_cpu_clk_axi_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_axi_div", .name = "cpu_clk_axi_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -672,7 +1042,9 @@ static struct clk_regmap g12a_cpu_clk_axi = { ...@@ -672,7 +1042,9 @@ static struct clk_regmap g12a_cpu_clk_axi = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cpu_clk_axi", .name = "cpu_clk_axi",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_axi_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cpu_clk_axi_div.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is set by the ROM monitor code, * This clock is set by the ROM monitor code,
...@@ -691,7 +1063,17 @@ static struct clk_regmap g12a_cpu_clk_trace_div = { ...@@ -691,7 +1063,17 @@ static struct clk_regmap g12a_cpu_clk_trace_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_trace_div", .name = "cpu_clk_trace_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_data = &(const struct clk_parent_data) {
/*
* Note:
* G12A and G12B have different cpu_clks (with
* different struct clk_hw). We fallback to the global
* naming string mechanism so cpu_clk_trace_div picks
* up the appropriate one.
*/
.name = "cpu_clk",
.index = -1,
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -704,7 +1086,9 @@ static struct clk_regmap g12a_cpu_clk_trace = { ...@@ -704,7 +1086,9 @@ static struct clk_regmap g12a_cpu_clk_trace = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cpu_clk_trace", .name = "cpu_clk_trace",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_trace_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cpu_clk_trace_div.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is set by the ROM monitor code, * This clock is set by the ROM monitor code,
...@@ -719,7 +1103,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div2 = { ...@@ -719,7 +1103,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_div2", .name = "cpub_clk_div2",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpub_clk" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -730,7 +1116,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div3 = { ...@@ -730,7 +1116,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div3 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_div3", .name = "cpub_clk_div3",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpub_clk" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -741,7 +1129,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div4 = { ...@@ -741,7 +1129,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div4 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_div4", .name = "cpub_clk_div4",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpub_clk" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -752,7 +1142,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div5 = { ...@@ -752,7 +1142,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div5 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_div5", .name = "cpub_clk_div5",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpub_clk" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -763,7 +1155,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div6 = { ...@@ -763,7 +1155,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div6 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_div6", .name = "cpub_clk_div6",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpub_clk" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -774,7 +1168,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div7 = { ...@@ -774,7 +1168,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div7 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_div7", .name = "cpub_clk_div7",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpub_clk" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -785,7 +1181,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div8 = { ...@@ -785,7 +1181,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div8 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_div8", .name = "cpub_clk_div8",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpub_clk" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -801,13 +1199,15 @@ static struct clk_regmap g12b_cpub_clk_apb_sel = { ...@@ -801,13 +1199,15 @@ static struct clk_regmap g12b_cpub_clk_apb_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_apb_sel", .name = "cpub_clk_apb_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ "cpub_clk_div2", .parent_hws = (const struct clk_hw *[]) {
"cpub_clk_div3", &g12b_cpub_clk_div2.hw,
"cpub_clk_div4", &g12b_cpub_clk_div3.hw,
"cpub_clk_div5", &g12b_cpub_clk_div4.hw,
"cpub_clk_div6", &g12b_cpub_clk_div5.hw,
"cpub_clk_div7", &g12b_cpub_clk_div6.hw,
"cpub_clk_div8" }, &g12b_cpub_clk_div7.hw,
&g12b_cpub_clk_div8.hw
},
.num_parents = 7, .num_parents = 7,
}, },
}; };
...@@ -821,7 +1221,9 @@ static struct clk_regmap g12b_cpub_clk_apb = { ...@@ -821,7 +1221,9 @@ static struct clk_regmap g12b_cpub_clk_apb = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cpub_clk_apb", .name = "cpub_clk_apb",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpub_clk_apb_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk_apb_sel.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is set by the ROM monitor code, * This clock is set by the ROM monitor code,
...@@ -840,13 +1242,15 @@ static struct clk_regmap g12b_cpub_clk_atb_sel = { ...@@ -840,13 +1242,15 @@ static struct clk_regmap g12b_cpub_clk_atb_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_atb_sel", .name = "cpub_clk_atb_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ "cpub_clk_div2", .parent_hws = (const struct clk_hw *[]) {
"cpub_clk_div3", &g12b_cpub_clk_div2.hw,
"cpub_clk_div4", &g12b_cpub_clk_div3.hw,
"cpub_clk_div5", &g12b_cpub_clk_div4.hw,
"cpub_clk_div6", &g12b_cpub_clk_div5.hw,
"cpub_clk_div7", &g12b_cpub_clk_div6.hw,
"cpub_clk_div8" }, &g12b_cpub_clk_div7.hw,
&g12b_cpub_clk_div8.hw
},
.num_parents = 7, .num_parents = 7,
}, },
}; };
...@@ -860,7 +1264,9 @@ static struct clk_regmap g12b_cpub_clk_atb = { ...@@ -860,7 +1264,9 @@ static struct clk_regmap g12b_cpub_clk_atb = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cpub_clk_atb", .name = "cpub_clk_atb",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpub_clk_atb_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk_atb_sel.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is set by the ROM monitor code, * This clock is set by the ROM monitor code,
...@@ -879,13 +1285,15 @@ static struct clk_regmap g12b_cpub_clk_axi_sel = { ...@@ -879,13 +1285,15 @@ static struct clk_regmap g12b_cpub_clk_axi_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_axi_sel", .name = "cpub_clk_axi_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ "cpub_clk_div2", .parent_hws = (const struct clk_hw *[]) {
"cpub_clk_div3", &g12b_cpub_clk_div2.hw,
"cpub_clk_div4", &g12b_cpub_clk_div3.hw,
"cpub_clk_div5", &g12b_cpub_clk_div4.hw,
"cpub_clk_div6", &g12b_cpub_clk_div5.hw,
"cpub_clk_div7", &g12b_cpub_clk_div6.hw,
"cpub_clk_div8" }, &g12b_cpub_clk_div7.hw,
&g12b_cpub_clk_div8.hw
},
.num_parents = 7, .num_parents = 7,
}, },
}; };
...@@ -899,7 +1307,9 @@ static struct clk_regmap g12b_cpub_clk_axi = { ...@@ -899,7 +1307,9 @@ static struct clk_regmap g12b_cpub_clk_axi = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cpub_clk_axi", .name = "cpub_clk_axi",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpub_clk_axi_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk_axi_sel.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is set by the ROM monitor code, * This clock is set by the ROM monitor code,
...@@ -918,13 +1328,15 @@ static struct clk_regmap g12b_cpub_clk_trace_sel = { ...@@ -918,13 +1328,15 @@ static struct clk_regmap g12b_cpub_clk_trace_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpub_clk_trace_sel", .name = "cpub_clk_trace_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ "cpub_clk_div2", .parent_hws = (const struct clk_hw *[]) {
"cpub_clk_div3", &g12b_cpub_clk_div2.hw,
"cpub_clk_div4", &g12b_cpub_clk_div3.hw,
"cpub_clk_div5", &g12b_cpub_clk_div4.hw,
"cpub_clk_div6", &g12b_cpub_clk_div5.hw,
"cpub_clk_div7", &g12b_cpub_clk_div6.hw,
"cpub_clk_div8" }, &g12b_cpub_clk_div7.hw,
&g12b_cpub_clk_div8.hw
},
.num_parents = 7, .num_parents = 7,
}, },
}; };
...@@ -938,7 +1350,9 @@ static struct clk_regmap g12b_cpub_clk_trace = { ...@@ -938,7 +1350,9 @@ static struct clk_regmap g12b_cpub_clk_trace = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cpub_clk_trace", .name = "cpub_clk_trace",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpub_clk_trace_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk_trace_sel.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock is set by the ROM monitor code, * This clock is set by the ROM monitor code,
...@@ -1003,7 +1417,9 @@ static struct clk_regmap g12a_gp0_pll_dco = { ...@@ -1003,7 +1417,9 @@ static struct clk_regmap g12a_gp0_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp0_pll_dco", .name = "gp0_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1019,7 +1435,9 @@ static struct clk_regmap g12a_gp0_pll = { ...@@ -1019,7 +1435,9 @@ static struct clk_regmap g12a_gp0_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp0_pll", .name = "gp0_pll",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "gp0_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_gp0_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1077,7 +1495,9 @@ static struct clk_regmap g12a_hifi_pll_dco = { ...@@ -1077,7 +1495,9 @@ static struct clk_regmap g12a_hifi_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hifi_pll_dco", .name = "hifi_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1093,7 +1513,9 @@ static struct clk_regmap g12a_hifi_pll = { ...@@ -1093,7 +1513,9 @@ static struct clk_regmap g12a_hifi_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hifi_pll", .name = "hifi_pll",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "hifi_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_hifi_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1164,7 +1586,9 @@ static struct clk_regmap g12a_pcie_pll_dco = { ...@@ -1164,7 +1586,9 @@ static struct clk_regmap g12a_pcie_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcie_pll_dco", .name = "pcie_pll_dco",
.ops = &meson_clk_pcie_pll_ops, .ops = &meson_clk_pcie_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1175,7 +1599,9 @@ static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = { ...@@ -1175,7 +1599,9 @@ static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcie_pll_dco_div2", .name = "pcie_pll_dco_div2",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "pcie_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_pcie_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1193,7 +1619,9 @@ static struct clk_regmap g12a_pcie_pll_od = { ...@@ -1193,7 +1619,9 @@ static struct clk_regmap g12a_pcie_pll_od = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcie_pll_od", .name = "pcie_pll_od",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "pcie_pll_dco_div2" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_pcie_pll_dco_div2.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1205,7 +1633,9 @@ static struct clk_fixed_factor g12a_pcie_pll = { ...@@ -1205,7 +1633,9 @@ static struct clk_fixed_factor g12a_pcie_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcie_pll_pll", .name = "pcie_pll_pll",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "pcie_pll_od" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_pcie_pll_od.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1247,7 +1677,9 @@ static struct clk_regmap g12a_hdmi_pll_dco = { ...@@ -1247,7 +1677,9 @@ static struct clk_regmap g12a_hdmi_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_dco", .name = "hdmi_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
/* /*
* Display directly handle hdmi pll registers ATM, we need * Display directly handle hdmi pll registers ATM, we need
...@@ -1267,7 +1699,9 @@ static struct clk_regmap g12a_hdmi_pll_od = { ...@@ -1267,7 +1699,9 @@ static struct clk_regmap g12a_hdmi_pll_od = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od", .name = "hdmi_pll_od",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_hdmi_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
}, },
...@@ -1283,7 +1717,9 @@ static struct clk_regmap g12a_hdmi_pll_od2 = { ...@@ -1283,7 +1717,9 @@ static struct clk_regmap g12a_hdmi_pll_od2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od2", .name = "hdmi_pll_od2",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_od" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_hdmi_pll_od.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
}, },
...@@ -1299,77 +1735,21 @@ static struct clk_regmap g12a_hdmi_pll = { ...@@ -1299,77 +1735,21 @@ static struct clk_regmap g12a_hdmi_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll", .name = "hdmi_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_od2" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_hdmi_pll_od2.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
}, },
}; };
static struct clk_fixed_factor g12a_fclk_div2_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "fclk_div2_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
static struct clk_regmap g12a_fclk_div2 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_FIX_PLL_CNTL1,
.bit_idx = 24,
},
.hw.init = &(struct clk_init_data){
.name = "fclk_div2",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div2_div" },
.num_parents = 1,
},
};
static struct clk_fixed_factor g12a_fclk_div3_div = {
.mult = 1,
.div = 3,
.hw.init = &(struct clk_init_data){
.name = "fclk_div3_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
static struct clk_regmap g12a_fclk_div3 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_FIX_PLL_CNTL1,
.bit_idx = 20,
},
.hw.init = &(struct clk_init_data){
.name = "fclk_div3",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div3_div" },
.num_parents = 1,
/*
* This clock is used by the resident firmware and is required
* by the platform to operate correctly.
* Until the following condition are met, we need this clock to
* be marked as critical:
* a) Mark the clock used by a firmware resource, if possible
* b) CCF has a clock hand-off mechanism to make the sure the
* clock stays on until the proper driver comes along
*/
.flags = CLK_IS_CRITICAL,
},
};
static struct clk_fixed_factor g12a_fclk_div4_div = { static struct clk_fixed_factor g12a_fclk_div4_div = {
.mult = 1, .mult = 1,
.div = 4, .div = 4,
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div4_div", .name = "fclk_div4_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1382,7 +1762,9 @@ static struct clk_regmap g12a_fclk_div4 = { ...@@ -1382,7 +1762,9 @@ static struct clk_regmap g12a_fclk_div4 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div4", .name = "fclk_div4",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div4_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_fclk_div4_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1393,7 +1775,7 @@ static struct clk_fixed_factor g12a_fclk_div5_div = { ...@@ -1393,7 +1775,7 @@ static struct clk_fixed_factor g12a_fclk_div5_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div5_div", .name = "fclk_div5_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1406,7 +1788,9 @@ static struct clk_regmap g12a_fclk_div5 = { ...@@ -1406,7 +1788,9 @@ static struct clk_regmap g12a_fclk_div5 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div5", .name = "fclk_div5",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div5_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_fclk_div5_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1417,7 +1801,7 @@ static struct clk_fixed_factor g12a_fclk_div7_div = { ...@@ -1417,7 +1801,7 @@ static struct clk_fixed_factor g12a_fclk_div7_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div7_div", .name = "fclk_div7_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1430,7 +1814,9 @@ static struct clk_regmap g12a_fclk_div7 = { ...@@ -1430,7 +1814,9 @@ static struct clk_regmap g12a_fclk_div7 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div7", .name = "fclk_div7",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div7_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_fclk_div7_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1441,7 +1827,9 @@ static struct clk_fixed_factor g12a_fclk_div2p5_div = { ...@@ -1441,7 +1827,9 @@ static struct clk_fixed_factor g12a_fclk_div2p5_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div2p5_div", .name = "fclk_div2p5_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_fixed_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1454,7 +1842,9 @@ static struct clk_regmap g12a_fclk_div2p5 = { ...@@ -1454,7 +1842,9 @@ static struct clk_regmap g12a_fclk_div2p5 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div2p5", .name = "fclk_div2p5",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div2p5_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_fclk_div2p5_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1465,7 +1855,9 @@ static struct clk_fixed_factor g12a_mpll_50m_div = { ...@@ -1465,7 +1855,9 @@ static struct clk_fixed_factor g12a_mpll_50m_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll_50m_div", .name = "mpll_50m_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_fixed_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1479,8 +1871,10 @@ static struct clk_regmap g12a_mpll_50m = { ...@@ -1479,8 +1871,10 @@ static struct clk_regmap g12a_mpll_50m = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll_50m", .name = "mpll_50m",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal", .parent_data = (const struct clk_parent_data []) {
"mpll_50m_div" }, { .fw_name = "xtal", },
{ .hw = &g12a_mpll_50m_div.hw },
},
.num_parents = 2, .num_parents = 2,
}, },
}; };
...@@ -1491,7 +1885,9 @@ static struct clk_fixed_factor g12a_mpll_prediv = { ...@@ -1491,7 +1885,9 @@ static struct clk_fixed_factor g12a_mpll_prediv = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll_prediv", .name = "mpll_prediv",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_fixed_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1529,7 +1925,9 @@ static struct clk_regmap g12a_mpll0_div = { ...@@ -1529,7 +1925,9 @@ static struct clk_regmap g12a_mpll0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0_div", .name = "mpll0_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1542,7 +1940,7 @@ static struct clk_regmap g12a_mpll0 = { ...@@ -1542,7 +1940,7 @@ static struct clk_regmap g12a_mpll0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0", .name = "mpll0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll0_div" }, .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1581,7 +1979,9 @@ static struct clk_regmap g12a_mpll1_div = { ...@@ -1581,7 +1979,9 @@ static struct clk_regmap g12a_mpll1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1_div", .name = "mpll1_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1594,7 +1994,7 @@ static struct clk_regmap g12a_mpll1 = { ...@@ -1594,7 +1994,7 @@ static struct clk_regmap g12a_mpll1 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1", .name = "mpll1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll1_div" }, .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1633,7 +2033,9 @@ static struct clk_regmap g12a_mpll2_div = { ...@@ -1633,7 +2033,9 @@ static struct clk_regmap g12a_mpll2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2_div", .name = "mpll2_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1646,7 +2048,7 @@ static struct clk_regmap g12a_mpll2 = { ...@@ -1646,7 +2048,7 @@ static struct clk_regmap g12a_mpll2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2", .name = "mpll2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll2_div" }, .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1685,7 +2087,9 @@ static struct clk_regmap g12a_mpll3_div = { ...@@ -1685,7 +2087,9 @@ static struct clk_regmap g12a_mpll3_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll3_div", .name = "mpll3_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1698,16 +2102,21 @@ static struct clk_regmap g12a_mpll3 = { ...@@ -1698,16 +2102,21 @@ static struct clk_regmap g12a_mpll3 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll3", .name = "mpll3",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll3_div" }, .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
static const char * const clk81_parent_names[] = { static const struct clk_parent_data clk81_parent_data[] = {
IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", { .fw_name = "xtal", },
"fclk_div3", "fclk_div5" { .hw = &g12a_fclk_div7.hw },
{ .hw = &g12a_mpll1.hw },
{ .hw = &g12a_mpll2.hw },
{ .hw = &g12a_fclk_div4.hw },
{ .hw = &g12a_fclk_div3.hw },
{ .hw = &g12a_fclk_div5.hw },
}; };
static struct clk_regmap g12a_mpeg_clk_sel = { static struct clk_regmap g12a_mpeg_clk_sel = {
...@@ -1720,8 +2129,8 @@ static struct clk_regmap g12a_mpeg_clk_sel = { ...@@ -1720,8 +2129,8 @@ static struct clk_regmap g12a_mpeg_clk_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpeg_clk_sel", .name = "mpeg_clk_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = clk81_parent_names, .parent_data = clk81_parent_data,
.num_parents = ARRAY_SIZE(clk81_parent_names), .num_parents = ARRAY_SIZE(clk81_parent_data),
}, },
}; };
...@@ -1734,7 +2143,9 @@ static struct clk_regmap g12a_mpeg_clk_div = { ...@@ -1734,7 +2143,9 @@ static struct clk_regmap g12a_mpeg_clk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div", .name = "mpeg_clk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "mpeg_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_mpeg_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1748,15 +2159,20 @@ static struct clk_regmap g12a_clk81 = { ...@@ -1748,15 +2159,20 @@ static struct clk_regmap g12a_clk81 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "clk81", .name = "clk81",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpeg_clk_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_mpeg_clk_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
}, },
}; };
static const char * const g12a_sd_emmc_clk0_parent_names[] = { static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", { .fw_name = "xtal", },
{ .hw = &g12a_fclk_div2.hw },
{ .hw = &g12a_fclk_div3.hw },
{ .hw = &g12a_fclk_div5.hw },
{ .hw = &g12a_fclk_div7.hw },
/* /*
* Following these parent clocks, we should also have had mpll2, mpll3 * Following these parent clocks, we should also have had mpll2, mpll3
* and gp0_pll but these clocks are too precious to be used here. All * and gp0_pll but these clocks are too precious to be used here. All
...@@ -1775,8 +2191,8 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_sel = { ...@@ -1775,8 +2191,8 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_a_clk0_sel", .name = "sd_emmc_a_clk0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_sd_emmc_clk0_parent_names, .parent_data = g12a_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1790,7 +2206,9 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_div = { ...@@ -1790,7 +2206,9 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_a_clk0_div", .name = "sd_emmc_a_clk0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_sd_emmc_a_clk0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1804,7 +2222,9 @@ static struct clk_regmap g12a_sd_emmc_a_clk0 = { ...@@ -1804,7 +2222,9 @@ static struct clk_regmap g12a_sd_emmc_a_clk0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sd_emmc_a_clk0", .name = "sd_emmc_a_clk0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_sd_emmc_a_clk0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1820,8 +2240,8 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_sel = { ...@@ -1820,8 +2240,8 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_sel", .name = "sd_emmc_b_clk0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_sd_emmc_clk0_parent_names, .parent_data = g12a_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1835,7 +2255,9 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_div = { ...@@ -1835,7 +2255,9 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_div", .name = "sd_emmc_b_clk0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_sd_emmc_b_clk0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1849,7 +2271,9 @@ static struct clk_regmap g12a_sd_emmc_b_clk0 = { ...@@ -1849,7 +2271,9 @@ static struct clk_regmap g12a_sd_emmc_b_clk0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sd_emmc_b_clk0", .name = "sd_emmc_b_clk0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_sd_emmc_b_clk0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1865,8 +2289,8 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_sel = { ...@@ -1865,8 +2289,8 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_sel", .name = "sd_emmc_c_clk0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_sd_emmc_clk0_parent_names, .parent_data = g12a_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1880,7 +2304,9 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_div = { ...@@ -1880,7 +2304,9 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_div", .name = "sd_emmc_c_clk0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_sd_emmc_c_clk0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1894,17 +2320,89 @@ static struct clk_regmap g12a_sd_emmc_c_clk0 = { ...@@ -1894,17 +2320,89 @@ static struct clk_regmap g12a_sd_emmc_c_clk0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sd_emmc_c_clk0", .name = "sd_emmc_c_clk0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_sd_emmc_c_clk0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
/* Video Clocks */
static struct clk_regmap g12a_vid_pll_div = {
.data = &(struct meson_vid_pll_div_data){
.val = {
.reg_off = HHI_VID_PLL_CLK_DIV,
.shift = 0,
.width = 15,
},
.sel = {
.reg_off = HHI_VID_PLL_CLK_DIV,
.shift = 16,
.width = 2,
},
},
.hw.init = &(struct clk_init_data) {
.name = "vid_pll_div",
.ops = &meson_vid_pll_div_ro_ops,
.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
};
static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
&g12a_vid_pll_div.hw,
&g12a_hdmi_pll.hw,
};
static struct clk_regmap g12a_vid_pll_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VID_PLL_CLK_DIV,
.mask = 0x1,
.shift = 18,
},
.hw.init = &(struct clk_init_data){
.name = "vid_pll_sel",
.ops = &clk_regmap_mux_ops,
/*
* bit 18 selects from 2 possible parents:
* vid_pll_div or hdmi_pll
*/
.parent_hws = g12a_vid_pll_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
static struct clk_regmap g12a_vid_pll = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_PLL_CLK_DIV,
.bit_idx = 19,
},
.hw.init = &(struct clk_init_data) {
.name = "vid_pll",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_vid_pll_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
};
/* VPU Clock */ /* VPU Clock */
static const char * const g12a_vpu_parent_names[] = { static const struct clk_hw *g12a_vpu_parent_hws[] = {
"fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7", &g12a_fclk_div3.hw,
"mpll1", "vid_pll", "hifi_pll", "gp0_pll", &g12a_fclk_div4.hw,
&g12a_fclk_div5.hw,
&g12a_fclk_div7.hw,
&g12a_mpll1.hw,
&g12a_vid_pll.hw,
&g12a_hifi_pll.hw,
&g12a_gp0_pll.hw,
}; };
static struct clk_regmap g12a_vpu_0_sel = { static struct clk_regmap g12a_vpu_0_sel = {
...@@ -1916,8 +2414,8 @@ static struct clk_regmap g12a_vpu_0_sel = { ...@@ -1916,8 +2414,8 @@ static struct clk_regmap g12a_vpu_0_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_0_sel", .name = "vpu_0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_vpu_parent_names, .parent_hws = g12a_vpu_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vpu_parent_names), .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -1931,7 +2429,7 @@ static struct clk_regmap g12a_vpu_0_div = { ...@@ -1931,7 +2429,7 @@ static struct clk_regmap g12a_vpu_0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_0_div", .name = "vpu_0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vpu_0_sel" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1945,7 +2443,7 @@ static struct clk_regmap g12a_vpu_0 = { ...@@ -1945,7 +2443,7 @@ static struct clk_regmap g12a_vpu_0 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vpu_0", .name = "vpu_0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vpu_0_div" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1960,8 +2458,8 @@ static struct clk_regmap g12a_vpu_1_sel = { ...@@ -1960,8 +2458,8 @@ static struct clk_regmap g12a_vpu_1_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_1_sel", .name = "vpu_1_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_vpu_parent_names, .parent_hws = g12a_vpu_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vpu_parent_names), .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -1975,7 +2473,7 @@ static struct clk_regmap g12a_vpu_1_div = { ...@@ -1975,7 +2473,7 @@ static struct clk_regmap g12a_vpu_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_1_div", .name = "vpu_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vpu_1_sel" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1989,7 +2487,7 @@ static struct clk_regmap g12a_vpu_1 = { ...@@ -1989,7 +2487,7 @@ static struct clk_regmap g12a_vpu_1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vpu_1", .name = "vpu_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vpu_1_div" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2008,7 +2506,10 @@ static struct clk_regmap g12a_vpu = { ...@@ -2008,7 +2506,10 @@ static struct clk_regmap g12a_vpu = {
* bit 31 selects from 2 possible parents: * bit 31 selects from 2 possible parents:
* vpu_0 or vpu_1 * vpu_0 or vpu_1
*/ */
.parent_names = (const char *[]){ "vpu_0", "vpu_1" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vpu_0.hw,
&g12a_vpu_1.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -2016,9 +2517,14 @@ static struct clk_regmap g12a_vpu = { ...@@ -2016,9 +2517,14 @@ static struct clk_regmap g12a_vpu = {
/* VDEC clocks */ /* VDEC clocks */
static const char * const g12a_vdec_parent_names[] = { static const struct clk_hw *g12a_vdec_parent_hws[] = {
"fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7", &g12a_fclk_div2p5.hw,
"hifi_pll", "gp0_pll", &g12a_fclk_div3.hw,
&g12a_fclk_div4.hw,
&g12a_fclk_div5.hw,
&g12a_fclk_div7.hw,
&g12a_hifi_pll.hw,
&g12a_gp0_pll.hw,
}; };
static struct clk_regmap g12a_vdec_1_sel = { static struct clk_regmap g12a_vdec_1_sel = {
...@@ -2031,8 +2537,8 @@ static struct clk_regmap g12a_vdec_1_sel = { ...@@ -2031,8 +2537,8 @@ static struct clk_regmap g12a_vdec_1_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_1_sel", .name = "vdec_1_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_vdec_parent_names, .parent_hws = g12a_vdec_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vdec_parent_names), .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -2047,7 +2553,9 @@ static struct clk_regmap g12a_vdec_1_div = { ...@@ -2047,7 +2553,9 @@ static struct clk_regmap g12a_vdec_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_1_div", .name = "vdec_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vdec_1_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2061,7 +2569,9 @@ static struct clk_regmap g12a_vdec_1 = { ...@@ -2061,7 +2569,9 @@ static struct clk_regmap g12a_vdec_1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vdec_1", .name = "vdec_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_1_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vdec_1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2077,8 +2587,8 @@ static struct clk_regmap g12a_vdec_hevcf_sel = { ...@@ -2077,8 +2587,8 @@ static struct clk_regmap g12a_vdec_hevcf_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_hevcf_sel", .name = "vdec_hevcf_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_vdec_parent_names, .parent_hws = g12a_vdec_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vdec_parent_names), .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -2093,7 +2603,9 @@ static struct clk_regmap g12a_vdec_hevcf_div = { ...@@ -2093,7 +2603,9 @@ static struct clk_regmap g12a_vdec_hevcf_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_hevcf_div", .name = "vdec_hevcf_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_hevcf_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vdec_hevcf_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2107,7 +2619,9 @@ static struct clk_regmap g12a_vdec_hevcf = { ...@@ -2107,7 +2619,9 @@ static struct clk_regmap g12a_vdec_hevcf = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vdec_hevcf", .name = "vdec_hevcf",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_hevcf_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vdec_hevcf_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2123,8 +2637,8 @@ static struct clk_regmap g12a_vdec_hevc_sel = { ...@@ -2123,8 +2637,8 @@ static struct clk_regmap g12a_vdec_hevc_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_hevc_sel", .name = "vdec_hevc_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_vdec_parent_names, .parent_hws = g12a_vdec_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vdec_parent_names), .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -2139,7 +2653,9 @@ static struct clk_regmap g12a_vdec_hevc_div = { ...@@ -2139,7 +2653,9 @@ static struct clk_regmap g12a_vdec_hevc_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_hevc_div", .name = "vdec_hevc_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_hevc_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vdec_hevc_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2153,7 +2669,9 @@ static struct clk_regmap g12a_vdec_hevc = { ...@@ -2153,7 +2669,9 @@ static struct clk_regmap g12a_vdec_hevc = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vdec_hevc", .name = "vdec_hevc",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_hevc_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vdec_hevc_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2161,9 +2679,15 @@ static struct clk_regmap g12a_vdec_hevc = { ...@@ -2161,9 +2679,15 @@ static struct clk_regmap g12a_vdec_hevc = {
/* VAPB Clock */ /* VAPB Clock */
static const char * const g12a_vapb_parent_names[] = { static const struct clk_hw *g12a_vapb_parent_hws[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", &g12a_fclk_div4.hw,
"mpll1", "vid_pll", "mpll2", "fclk_div2p5", &g12a_fclk_div3.hw,
&g12a_fclk_div5.hw,
&g12a_fclk_div7.hw,
&g12a_mpll1.hw,
&g12a_vid_pll.hw,
&g12a_mpll2.hw,
&g12a_fclk_div2p5.hw,
}; };
static struct clk_regmap g12a_vapb_0_sel = { static struct clk_regmap g12a_vapb_0_sel = {
...@@ -2175,8 +2699,8 @@ static struct clk_regmap g12a_vapb_0_sel = { ...@@ -2175,8 +2699,8 @@ static struct clk_regmap g12a_vapb_0_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vapb_0_sel", .name = "vapb_0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_vapb_parent_names, .parent_hws = g12a_vapb_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vapb_parent_names), .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -2190,7 +2714,9 @@ static struct clk_regmap g12a_vapb_0_div = { ...@@ -2190,7 +2714,9 @@ static struct clk_regmap g12a_vapb_0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vapb_0_div", .name = "vapb_0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vapb_0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vapb_0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2204,7 +2730,9 @@ static struct clk_regmap g12a_vapb_0 = { ...@@ -2204,7 +2730,9 @@ static struct clk_regmap g12a_vapb_0 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vapb_0", .name = "vapb_0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vapb_0_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vapb_0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2219,8 +2747,8 @@ static struct clk_regmap g12a_vapb_1_sel = { ...@@ -2219,8 +2747,8 @@ static struct clk_regmap g12a_vapb_1_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vapb_1_sel", .name = "vapb_1_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_vapb_parent_names, .parent_hws = g12a_vapb_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vapb_parent_names), .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -2234,7 +2762,9 @@ static struct clk_regmap g12a_vapb_1_div = { ...@@ -2234,7 +2762,9 @@ static struct clk_regmap g12a_vapb_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vapb_1_div", .name = "vapb_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vapb_1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vapb_1_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2248,7 +2778,9 @@ static struct clk_regmap g12a_vapb_1 = { ...@@ -2248,7 +2778,9 @@ static struct clk_regmap g12a_vapb_1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vapb_1", .name = "vapb_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vapb_1_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vapb_1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2267,7 +2799,10 @@ static struct clk_regmap g12a_vapb_sel = { ...@@ -2267,7 +2799,10 @@ static struct clk_regmap g12a_vapb_sel = {
* bit 31 selects from 2 possible parents: * bit 31 selects from 2 possible parents:
* vapb_0 or vapb_1 * vapb_0 or vapb_1
*/ */
.parent_names = (const char *[]){ "vapb_0", "vapb_1" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vapb_0.hw,
&g12a_vapb_1.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -2281,75 +2816,21 @@ static struct clk_regmap g12a_vapb = { ...@@ -2281,75 +2816,21 @@ static struct clk_regmap g12a_vapb = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vapb", .name = "vapb",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vapb_sel" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
}; };
/* Video Clocks */ static const struct clk_hw *g12a_vclk_parent_hws[] = {
&g12a_vid_pll.hw,
static struct clk_regmap g12a_vid_pll_div = { &g12a_gp0_pll.hw,
.data = &(struct meson_vid_pll_div_data){ &g12a_hifi_pll.hw,
.val = { &g12a_mpll1.hw,
.reg_off = HHI_VID_PLL_CLK_DIV, &g12a_fclk_div3.hw,
.shift = 0, &g12a_fclk_div4.hw,
.width = 15, &g12a_fclk_div5.hw,
}, &g12a_fclk_div7.hw,
.sel = {
.reg_off = HHI_VID_PLL_CLK_DIV,
.shift = 16,
.width = 2,
},
},
.hw.init = &(struct clk_init_data) {
.name = "vid_pll_div",
.ops = &meson_vid_pll_div_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
};
static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div",
"hdmi_pll" };
static struct clk_regmap g12a_vid_pll_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VID_PLL_CLK_DIV,
.mask = 0x1,
.shift = 18,
},
.hw.init = &(struct clk_init_data){
.name = "vid_pll_sel",
.ops = &clk_regmap_mux_ops,
/*
* bit 18 selects from 2 possible parents:
* vid_pll_div or hdmi_pll
*/
.parent_names = g12a_vid_pll_parent_names,
.num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
static struct clk_regmap g12a_vid_pll = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_PLL_CLK_DIV,
.bit_idx = 19,
},
.hw.init = &(struct clk_init_data) {
.name = "vid_pll",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vid_pll_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
};
static const char * const g12a_vclk_parent_names[] = {
"vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4",
"fclk_div5", "fclk_div7"
}; };
static struct clk_regmap g12a_vclk_sel = { static struct clk_regmap g12a_vclk_sel = {
...@@ -2361,8 +2842,8 @@ static struct clk_regmap g12a_vclk_sel = { ...@@ -2361,8 +2842,8 @@ static struct clk_regmap g12a_vclk_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_sel", .name = "vclk_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_vclk_parent_names, .parent_hws = g12a_vclk_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vclk_parent_names), .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -2376,8 +2857,8 @@ static struct clk_regmap g12a_vclk2_sel = { ...@@ -2376,8 +2857,8 @@ static struct clk_regmap g12a_vclk2_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_sel", .name = "vclk2_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_vclk_parent_names, .parent_hws = g12a_vclk_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vclk_parent_names), .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -2390,7 +2871,7 @@ static struct clk_regmap g12a_vclk_input = { ...@@ -2390,7 +2871,7 @@ static struct clk_regmap g12a_vclk_input = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_input", .name = "vclk_input",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk_sel" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2404,7 +2885,7 @@ static struct clk_regmap g12a_vclk2_input = { ...@@ -2404,7 +2885,7 @@ static struct clk_regmap g12a_vclk2_input = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_input", .name = "vclk2_input",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2_sel" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2419,7 +2900,9 @@ static struct clk_regmap g12a_vclk_div = { ...@@ -2419,7 +2900,9 @@ static struct clk_regmap g12a_vclk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div", .name = "vclk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vclk_input" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vclk_input.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE, .flags = CLK_GET_RATE_NOCACHE,
}, },
...@@ -2434,7 +2917,9 @@ static struct clk_regmap g12a_vclk2_div = { ...@@ -2434,7 +2917,9 @@ static struct clk_regmap g12a_vclk2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div", .name = "vclk2_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vclk2_input" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vclk2_input.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE, .flags = CLK_GET_RATE_NOCACHE,
}, },
...@@ -2448,7 +2933,7 @@ static struct clk_regmap g12a_vclk = { ...@@ -2448,7 +2933,7 @@ static struct clk_regmap g12a_vclk = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk", .name = "vclk",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk_div" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2462,7 +2947,7 @@ static struct clk_regmap g12a_vclk2 = { ...@@ -2462,7 +2947,7 @@ static struct clk_regmap g12a_vclk2 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2", .name = "vclk2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2_div" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2476,7 +2961,7 @@ static struct clk_regmap g12a_vclk_div1 = { ...@@ -2476,7 +2961,7 @@ static struct clk_regmap g12a_vclk_div1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_div1", .name = "vclk_div1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2490,7 +2975,7 @@ static struct clk_regmap g12a_vclk_div2_en = { ...@@ -2490,7 +2975,7 @@ static struct clk_regmap g12a_vclk_div2_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_div2_en", .name = "vclk_div2_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2504,7 +2989,7 @@ static struct clk_regmap g12a_vclk_div4_en = { ...@@ -2504,7 +2989,7 @@ static struct clk_regmap g12a_vclk_div4_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_div4_en", .name = "vclk_div4_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2518,7 +3003,7 @@ static struct clk_regmap g12a_vclk_div6_en = { ...@@ -2518,7 +3003,7 @@ static struct clk_regmap g12a_vclk_div6_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_div6_en", .name = "vclk_div6_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2532,7 +3017,7 @@ static struct clk_regmap g12a_vclk_div12_en = { ...@@ -2532,7 +3017,7 @@ static struct clk_regmap g12a_vclk_div12_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_div12_en", .name = "vclk_div12_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2546,7 +3031,7 @@ static struct clk_regmap g12a_vclk2_div1 = { ...@@ -2546,7 +3031,7 @@ static struct clk_regmap g12a_vclk2_div1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_div1", .name = "vclk2_div1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2560,7 +3045,7 @@ static struct clk_regmap g12a_vclk2_div2_en = { ...@@ -2560,7 +3045,7 @@ static struct clk_regmap g12a_vclk2_div2_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_div2_en", .name = "vclk2_div2_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2574,7 +3059,7 @@ static struct clk_regmap g12a_vclk2_div4_en = { ...@@ -2574,7 +3059,7 @@ static struct clk_regmap g12a_vclk2_div4_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_div4_en", .name = "vclk2_div4_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2588,7 +3073,7 @@ static struct clk_regmap g12a_vclk2_div6_en = { ...@@ -2588,7 +3073,7 @@ static struct clk_regmap g12a_vclk2_div6_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_div6_en", .name = "vclk2_div6_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2602,7 +3087,7 @@ static struct clk_regmap g12a_vclk2_div12_en = { ...@@ -2602,7 +3087,7 @@ static struct clk_regmap g12a_vclk2_div12_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_div12_en", .name = "vclk2_div12_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2" }, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2614,7 +3099,9 @@ static struct clk_fixed_factor g12a_vclk_div2 = { ...@@ -2614,7 +3099,9 @@ static struct clk_fixed_factor g12a_vclk_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div2", .name = "vclk_div2",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_div2_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vclk_div2_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -2625,7 +3112,9 @@ static struct clk_fixed_factor g12a_vclk_div4 = { ...@@ -2625,7 +3112,9 @@ static struct clk_fixed_factor g12a_vclk_div4 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div4", .name = "vclk_div4",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_div4_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vclk_div4_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -2636,7 +3125,9 @@ static struct clk_fixed_factor g12a_vclk_div6 = { ...@@ -2636,7 +3125,9 @@ static struct clk_fixed_factor g12a_vclk_div6 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div6", .name = "vclk_div6",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_div6_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vclk_div6_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -2647,7 +3138,9 @@ static struct clk_fixed_factor g12a_vclk_div12 = { ...@@ -2647,7 +3138,9 @@ static struct clk_fixed_factor g12a_vclk_div12 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div12", .name = "vclk_div12",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_div12_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vclk_div12_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -2658,7 +3151,9 @@ static struct clk_fixed_factor g12a_vclk2_div2 = { ...@@ -2658,7 +3151,9 @@ static struct clk_fixed_factor g12a_vclk2_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div2", .name = "vclk2_div2",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_div2_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vclk2_div2_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -2669,7 +3164,9 @@ static struct clk_fixed_factor g12a_vclk2_div4 = { ...@@ -2669,7 +3164,9 @@ static struct clk_fixed_factor g12a_vclk2_div4 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div4", .name = "vclk2_div4",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_div4_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vclk2_div4_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -2680,7 +3177,9 @@ static struct clk_fixed_factor g12a_vclk2_div6 = { ...@@ -2680,7 +3177,9 @@ static struct clk_fixed_factor g12a_vclk2_div6 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div6", .name = "vclk2_div6",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_div6_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vclk2_div6_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -2691,16 +3190,25 @@ static struct clk_fixed_factor g12a_vclk2_div12 = { ...@@ -2691,16 +3190,25 @@ static struct clk_fixed_factor g12a_vclk2_div12 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div12", .name = "vclk2_div12",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_div12_en" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_vclk2_div12_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
static const char * const g12a_cts_parent_names[] = { static const struct clk_hw *g12a_cts_parent_hws[] = {
"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", &g12a_vclk_div1.hw,
"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", &g12a_vclk_div2.hw,
"vclk2_div6", "vclk2_div12" &g12a_vclk_div4.hw,
&g12a_vclk_div6.hw,
&g12a_vclk_div12.hw,
&g12a_vclk2_div1.hw,
&g12a_vclk2_div2.hw,
&g12a_vclk2_div4.hw,
&g12a_vclk2_div6.hw,
&g12a_vclk2_div12.hw,
}; };
static struct clk_regmap g12a_cts_enci_sel = { static struct clk_regmap g12a_cts_enci_sel = {
...@@ -2713,8 +3221,8 @@ static struct clk_regmap g12a_cts_enci_sel = { ...@@ -2713,8 +3221,8 @@ static struct clk_regmap g12a_cts_enci_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_enci_sel", .name = "cts_enci_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_cts_parent_names, .parent_hws = g12a_cts_parent_hws,
.num_parents = ARRAY_SIZE(g12a_cts_parent_names), .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -2729,8 +3237,8 @@ static struct clk_regmap g12a_cts_encp_sel = { ...@@ -2729,8 +3237,8 @@ static struct clk_regmap g12a_cts_encp_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_encp_sel", .name = "cts_encp_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_cts_parent_names, .parent_hws = g12a_cts_parent_hws,
.num_parents = ARRAY_SIZE(g12a_cts_parent_names), .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -2745,18 +3253,25 @@ static struct clk_regmap g12a_cts_vdac_sel = { ...@@ -2745,18 +3253,25 @@ static struct clk_regmap g12a_cts_vdac_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_vdac_sel", .name = "cts_vdac_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_cts_parent_names, .parent_hws = g12a_cts_parent_hws,
.num_parents = ARRAY_SIZE(g12a_cts_parent_names), .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
/* TOFIX: add support for cts_tcon */ /* TOFIX: add support for cts_tcon */
static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
static const char * const g12a_cts_hdmi_tx_parent_names[] = { static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", &g12a_vclk_div1.hw,
"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", &g12a_vclk_div2.hw,
"vclk2_div6", "vclk2_div12" &g12a_vclk_div4.hw,
&g12a_vclk_div6.hw,
&g12a_vclk_div12.hw,
&g12a_vclk2_div1.hw,
&g12a_vclk2_div2.hw,
&g12a_vclk2_div4.hw,
&g12a_vclk2_div6.hw,
&g12a_vclk2_div12.hw,
}; };
static struct clk_regmap g12a_hdmi_tx_sel = { static struct clk_regmap g12a_hdmi_tx_sel = {
...@@ -2769,8 +3284,8 @@ static struct clk_regmap g12a_hdmi_tx_sel = { ...@@ -2769,8 +3284,8 @@ static struct clk_regmap g12a_hdmi_tx_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_tx_sel", .name = "hdmi_tx_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_cts_hdmi_tx_parent_names, .parent_hws = g12a_cts_hdmi_tx_parent_hws,
.num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names), .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -2783,7 +3298,9 @@ static struct clk_regmap g12a_cts_enci = { ...@@ -2783,7 +3298,9 @@ static struct clk_regmap g12a_cts_enci = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cts_enci", .name = "cts_enci",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_enci_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cts_enci_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2797,7 +3314,9 @@ static struct clk_regmap g12a_cts_encp = { ...@@ -2797,7 +3314,9 @@ static struct clk_regmap g12a_cts_encp = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cts_encp", .name = "cts_encp",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_encp_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cts_encp_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2811,7 +3330,9 @@ static struct clk_regmap g12a_cts_vdac = { ...@@ -2811,7 +3330,9 @@ static struct clk_regmap g12a_cts_vdac = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cts_vdac", .name = "cts_vdac",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_vdac_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_cts_vdac_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2825,7 +3346,9 @@ static struct clk_regmap g12a_hdmi_tx = { ...@@ -2825,7 +3346,9 @@ static struct clk_regmap g12a_hdmi_tx = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "hdmi_tx", .name = "hdmi_tx",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "hdmi_tx_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_hdmi_tx_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2833,8 +3356,11 @@ static struct clk_regmap g12a_hdmi_tx = { ...@@ -2833,8 +3356,11 @@ static struct clk_regmap g12a_hdmi_tx = {
/* HDMI Clocks */ /* HDMI Clocks */
static const char * const g12a_hdmi_parent_names[] = { static const struct clk_parent_data g12a_hdmi_parent_data[] = {
IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5" { .fw_name = "xtal", },
{ .hw = &g12a_fclk_div4.hw },
{ .hw = &g12a_fclk_div3.hw },
{ .hw = &g12a_fclk_div5.hw },
}; };
static struct clk_regmap g12a_hdmi_sel = { static struct clk_regmap g12a_hdmi_sel = {
...@@ -2847,8 +3373,8 @@ static struct clk_regmap g12a_hdmi_sel = { ...@@ -2847,8 +3373,8 @@ static struct clk_regmap g12a_hdmi_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_sel", .name = "hdmi_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_hdmi_parent_names, .parent_data = g12a_hdmi_parent_data,
.num_parents = ARRAY_SIZE(g12a_hdmi_parent_names), .num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -2862,7 +3388,7 @@ static struct clk_regmap g12a_hdmi_div = { ...@@ -2862,7 +3388,7 @@ static struct clk_regmap g12a_hdmi_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_div", .name = "hdmi_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "hdmi_sel" }, .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE, .flags = CLK_GET_RATE_NOCACHE,
}, },
...@@ -2876,7 +3402,7 @@ static struct clk_regmap g12a_hdmi = { ...@@ -2876,7 +3402,7 @@ static struct clk_regmap g12a_hdmi = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "hdmi", .name = "hdmi",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "hdmi_div" }, .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2886,10 +3412,15 @@ static struct clk_regmap g12a_hdmi = { ...@@ -2886,10 +3412,15 @@ static struct clk_regmap g12a_hdmi = {
* The MALI IP is clocked by two identical clocks (mali_0 and mali_1) * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
* muxed by a glitch-free switch. * muxed by a glitch-free switch.
*/ */
static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
static const char * const g12a_mali_0_1_parent_names[] = { { .fw_name = "xtal", },
IN_PREFIX "xtal", "gp0_pll", "hihi_pll", "fclk_div2p5", { .hw = &g12a_gp0_pll.hw },
"fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7" { .hw = &g12a_hifi_pll.hw },
{ .hw = &g12a_fclk_div2p5.hw },
{ .hw = &g12a_fclk_div3.hw },
{ .hw = &g12a_fclk_div4.hw },
{ .hw = &g12a_fclk_div5.hw },
{ .hw = &g12a_fclk_div7.hw },
}; };
static struct clk_regmap g12a_mali_0_sel = { static struct clk_regmap g12a_mali_0_sel = {
...@@ -2901,7 +3432,7 @@ static struct clk_regmap g12a_mali_0_sel = { ...@@ -2901,7 +3432,7 @@ static struct clk_regmap g12a_mali_0_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_0_sel", .name = "mali_0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_mali_0_1_parent_names, .parent_data = g12a_mali_0_1_parent_data,
.num_parents = 8, .num_parents = 8,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -2916,7 +3447,9 @@ static struct clk_regmap g12a_mali_0_div = { ...@@ -2916,7 +3447,9 @@ static struct clk_regmap g12a_mali_0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_0_div", .name = "mali_0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "mali_0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_mali_0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -2930,7 +3463,9 @@ static struct clk_regmap g12a_mali_0 = { ...@@ -2930,7 +3463,9 @@ static struct clk_regmap g12a_mali_0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_0", .name = "mali_0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mali_0_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_mali_0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2945,7 +3480,7 @@ static struct clk_regmap g12a_mali_1_sel = { ...@@ -2945,7 +3480,7 @@ static struct clk_regmap g12a_mali_1_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_1_sel", .name = "mali_1_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_mali_0_1_parent_names, .parent_data = g12a_mali_0_1_parent_data,
.num_parents = 8, .num_parents = 8,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -2960,7 +3495,9 @@ static struct clk_regmap g12a_mali_1_div = { ...@@ -2960,7 +3495,9 @@ static struct clk_regmap g12a_mali_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_1_div", .name = "mali_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "mali_1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_mali_1_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -2974,14 +3511,17 @@ static struct clk_regmap g12a_mali_1 = { ...@@ -2974,14 +3511,17 @@ static struct clk_regmap g12a_mali_1 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_1", .name = "mali_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mali_1_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_mali_1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
static const char * const g12a_mali_parent_names[] = { static const struct clk_hw *g12a_mali_parent_hws[] = {
"mali_0", "mali_1" &g12a_mali_0.hw,
&g12a_mali_1.hw,
}; };
static struct clk_regmap g12a_mali = { static struct clk_regmap g12a_mali = {
...@@ -2993,7 +3533,7 @@ static struct clk_regmap g12a_mali = { ...@@ -2993,7 +3533,7 @@ static struct clk_regmap g12a_mali = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali", .name = "mali",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = g12a_mali_parent_names, .parent_hws = g12a_mali_parent_hws,
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -3008,7 +3548,9 @@ static struct clk_regmap g12a_ts_div = { ...@@ -3008,7 +3548,9 @@ static struct clk_regmap g12a_ts_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ts_div", .name = "ts_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -3021,11 +3563,19 @@ static struct clk_regmap g12a_ts = { ...@@ -3021,11 +3563,19 @@ static struct clk_regmap g12a_ts = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ts", .name = "ts",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "ts_div" }, .parent_hws = (const struct clk_hw *[]) {
&g12a_ts_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
#define MESON_GATE(_name, _reg, _bit) \
MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
#define MESON_GATE_RO(_name, _reg, _bit) \
MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
/* Everything Else (EE) domain gates */ /* Everything Else (EE) domain gates */
static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0); static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1); static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
...@@ -3792,28 +4342,210 @@ static const struct reg_sequence g12a_init_regs[] = { ...@@ -3792,28 +4342,210 @@ static const struct reg_sequence g12a_init_regs[] = {
{ .reg = HHI_MPLL_CNTL0, .def = 0x00000543 }, { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
}; };
static const struct meson_eeclkc_data g12a_clkc_data = { static int meson_g12a_dvfs_setup_common(struct platform_device *pdev,
.regmap_clks = g12a_clk_regmaps, struct clk_hw **hws)
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), {
.hw_onecell_data = &g12a_hw_onecell_data, const char *notifier_clk_name;
.init_regs = g12a_init_regs, struct clk *notifier_clk;
.init_count = ARRAY_SIZE(g12a_init_regs), struct clk_hw *xtal;
}; int ret;
static const struct meson_eeclkc_data g12b_clkc_data = { xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), /* Setup clock notifier for cpu_clk_postmux0 */
.hw_onecell_data = &g12b_hw_onecell_data g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw);
notifier_clk = __clk_lookup(notifier_clk_name);
ret = clk_notifier_register(notifier_clk,
&g12a_cpu_clk_postmux0_nb_data.nb);
if (ret) {
dev_err(&pdev->dev, "failed to register the cpu_clk_postmux0 notifier\n");
return ret;
}
/* Setup clock notifier for cpu_clk_dyn mux */
notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw);
notifier_clk = __clk_lookup(notifier_clk_name);
ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
if (ret) {
dev_err(&pdev->dev, "failed to register the cpu_clk_dyn notifier\n");
return ret;
}
return 0;
}
static int meson_g12b_dvfs_setup(struct platform_device *pdev)
{
struct clk_hw **hws = g12b_hw_onecell_data.hws;
const char *notifier_clk_name;
struct clk *notifier_clk;
struct clk_hw *xtal;
int ret;
ret = meson_g12a_dvfs_setup_common(pdev, hws);
if (ret)
return ret;
xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
/* Setup clock notifier for cpu_clk mux */
notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw);
notifier_clk = __clk_lookup(notifier_clk_name);
ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
if (ret) {
dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
return ret;
}
/* Setup clock notifier for sys1_pll */
notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw);
notifier_clk = __clk_lookup(notifier_clk_name);
ret = clk_notifier_register(notifier_clk,
&g12b_cpu_clk_sys1_pll_nb_data.nb);
if (ret) {
dev_err(&pdev->dev, "failed to register the sys1_pll notifier\n");
return ret;
}
/* Add notifiers for the second CPU cluster */
/* Setup clock notifier for cpub_clk_postmux0 */
g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw);
notifier_clk = __clk_lookup(notifier_clk_name);
ret = clk_notifier_register(notifier_clk,
&g12b_cpub_clk_postmux0_nb_data.nb);
if (ret) {
dev_err(&pdev->dev, "failed to register the cpub_clk_postmux0 notifier\n");
return ret;
}
/* Setup clock notifier for cpub_clk_dyn mux */
notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw);
notifier_clk = __clk_lookup(notifier_clk_name);
ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
if (ret) {
dev_err(&pdev->dev, "failed to register the cpub_clk_dyn notifier\n");
return ret;
}
/* Setup clock notifier for cpub_clk mux */
notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw);
notifier_clk = __clk_lookup(notifier_clk_name);
ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
if (ret) {
dev_err(&pdev->dev, "failed to register the cpub_clk notifier\n");
return ret;
}
/* Setup clock notifier for sys_pll */
notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
notifier_clk = __clk_lookup(notifier_clk_name);
ret = clk_notifier_register(notifier_clk,
&g12b_cpub_clk_sys_pll_nb_data.nb);
if (ret) {
dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
return ret;
}
return 0;
}
static int meson_g12a_dvfs_setup(struct platform_device *pdev)
{
struct clk_hw **hws = g12a_hw_onecell_data.hws;
const char *notifier_clk_name;
struct clk *notifier_clk;
int ret;
ret = meson_g12a_dvfs_setup_common(pdev, hws);
if (ret)
return ret;
/* Setup clock notifier for cpu_clk mux */
notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw);
notifier_clk = __clk_lookup(notifier_clk_name);
ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
if (ret) {
dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
return ret;
}
/* Setup clock notifier for sys_pll */
notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
notifier_clk = __clk_lookup(notifier_clk_name);
ret = clk_notifier_register(notifier_clk, &g12a_sys_pll_nb_data.nb);
if (ret) {
dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
return ret;
}
return 0;
}
struct meson_g12a_data {
const struct meson_eeclkc_data eeclkc_data;
int (*dvfs_setup)(struct platform_device *pdev);
};
static int meson_g12a_probe(struct platform_device *pdev)
{
const struct meson_eeclkc_data *eeclkc_data;
const struct meson_g12a_data *g12a_data;
int ret;
eeclkc_data = of_device_get_match_data(&pdev->dev);
if (!eeclkc_data)
return -EINVAL;
ret = meson_eeclkc_probe(pdev);
if (ret)
return ret;
g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
eeclkc_data);
if (g12a_data->dvfs_setup)
return g12a_data->dvfs_setup(pdev);
return 0;
}
static const struct meson_g12a_data g12a_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
.hw_onecell_data = &g12a_hw_onecell_data,
.init_regs = g12a_init_regs,
.init_count = ARRAY_SIZE(g12a_init_regs),
},
.dvfs_setup = meson_g12a_dvfs_setup,
};
static const struct meson_g12a_data g12b_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
.hw_onecell_data = &g12b_hw_onecell_data,
},
.dvfs_setup = meson_g12b_dvfs_setup,
}; };
static const struct of_device_id clkc_match_table[] = { static const struct of_device_id clkc_match_table[] = {
{ .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data }, {
{ .compatible = "amlogic,g12b-clkc", .data = &g12b_clkc_data }, .compatible = "amlogic,g12a-clkc",
.data = &g12a_clkc_data.eeclkc_data
},
{
.compatible = "amlogic,g12b-clkc",
.data = &g12b_clkc_data.eeclkc_data
},
{} {}
}; };
static struct platform_driver g12a_driver = { static struct platform_driver g12a_driver = {
.probe = meson_eeclkc_probe, .probe = meson_g12a_probe,
.driver = { .driver = {
.name = "g12a-clkc", .name = "g12a-clkc",
.of_match_table = clkc_match_table, .of_match_table = clkc_match_table,
......
drivers/clk/meson/g12a.h
View file @ b69337d3
...@@ -216,7 +216,6 @@ ...@@ -216,7 +216,6 @@
#define CLKID_CPUB_CLK_DYN1_DIV 221 #define CLKID_CPUB_CLK_DYN1_DIV 221
#define CLKID_CPUB_CLK_DYN1 222 #define CLKID_CPUB_CLK_DYN1 222
#define CLKID_CPUB_CLK_DYN 223 #define CLKID_CPUB_CLK_DYN 223
#define CLKID_CPUB_CLK 224
#define CLKID_CPUB_CLK_DIV16_EN 225 #define CLKID_CPUB_CLK_DIV16_EN 225
#define CLKID_CPUB_CLK_DIV16 226 #define CLKID_CPUB_CLK_DIV16 226
#define CLKID_CPUB_CLK_DIV2 227 #define CLKID_CPUB_CLK_DIV2 227
......
drivers/clk/meson/gxbb-aoclk.c
View file @ b69337d3
...@@ -11,8 +11,6 @@ ...@@ -11,8 +11,6 @@
#include "clk-regmap.h" #include "clk-regmap.h"
#include "clk-dualdiv.h" #include "clk-dualdiv.h"
#define IN_PREFIX "ao-in-"
/* AO Configuration Clock registers offsets */ /* AO Configuration Clock registers offsets */
#define AO_RTI_PWR_CNTL_REG1 0x0c #define AO_RTI_PWR_CNTL_REG1 0x0c
#define AO_RTI_PWR_CNTL_REG0 0x10 #define AO_RTI_PWR_CNTL_REG0 0x10
...@@ -31,7 +29,9 @@ static struct clk_regmap _name##_ao = { \ ...@@ -31,7 +29,9 @@ static struct clk_regmap _name##_ao = { \
.hw.init = &(struct clk_init_data) { \ .hw.init = &(struct clk_init_data) { \
.name = #_name "_ao", \ .name = #_name "_ao", \
.ops = &clk_regmap_gate_ops, \ .ops = &clk_regmap_gate_ops, \
.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \ .parent_data = &(const struct clk_parent_data) { \
.fw_name = "mpeg-clk", \
}, \
.num_parents = 1, \ .num_parents = 1, \
.flags = CLK_IGNORE_UNUSED, \ .flags = CLK_IGNORE_UNUSED, \
}, \ }, \
...@@ -52,7 +52,9 @@ static struct clk_regmap ao_cts_oscin = { ...@@ -52,7 +52,9 @@ static struct clk_regmap ao_cts_oscin = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ao_cts_oscin", .name = "ao_cts_oscin",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -65,7 +67,7 @@ static struct clk_regmap ao_32k_pre = { ...@@ -65,7 +67,7 @@ static struct clk_regmap ao_32k_pre = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ao_32k_pre", .name = "ao_32k_pre",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "ao_cts_oscin" }, .parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -112,7 +114,7 @@ static struct clk_regmap ao_32k_div = { ...@@ -112,7 +114,7 @@ static struct clk_regmap ao_32k_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ao_32k_div", .name = "ao_32k_div",
.ops = &meson_clk_dualdiv_ops, .ops = &meson_clk_dualdiv_ops,
.parent_names = (const char *[]){ "ao_32k_pre" }, .parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -127,8 +129,10 @@ static struct clk_regmap ao_32k_sel = { ...@@ -127,8 +129,10 @@ static struct clk_regmap ao_32k_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ao_32k_sel", .name = "ao_32k_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "ao_32k_div", .parent_hws = (const struct clk_hw *[]) {
"ao_32k_pre" }, &ao_32k_div.hw,
&ao_32k_pre.hw
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -142,7 +146,7 @@ static struct clk_regmap ao_32k = { ...@@ -142,7 +146,7 @@ static struct clk_regmap ao_32k = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ao_32k", .name = "ao_32k",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "ao_32k_sel" }, .parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -159,10 +163,12 @@ static struct clk_regmap ao_cts_rtc_oscin = { ...@@ -159,10 +163,12 @@ static struct clk_regmap ao_cts_rtc_oscin = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ao_cts_rtc_oscin", .name = "ao_cts_rtc_oscin",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ IN_PREFIX "ext-32k-0", .parent_data = (const struct clk_parent_data []) {
IN_PREFIX "ext-32k-1", { .fw_name = "ext-32k-0", },
IN_PREFIX "ext-32k-2", { .fw_name = "ext-32k-1", },
"ao_32k" }, { .fw_name = "ext-32k-2", },
{ .hw = &ao_32k.hw },
},
.num_parents = 4, .num_parents = 4,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -178,8 +184,10 @@ static struct clk_regmap ao_clk81 = { ...@@ -178,8 +184,10 @@ static struct clk_regmap ao_clk81 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ao_clk81", .name = "ao_clk81",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk", .parent_data = (const struct clk_parent_data []) {
"ao_cts_rtc_oscin" }, { .fw_name = "mpeg-clk", },
{ .hw = &ao_cts_rtc_oscin.hw },
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -208,8 +216,10 @@ static struct clk_regmap ao_cts_cec = { ...@@ -208,8 +216,10 @@ static struct clk_regmap ao_cts_cec = {
* Until CCF gets fixed, adding this fake parent that won't * Until CCF gets fixed, adding this fake parent that won't
* ever be registered should work around the problem * ever be registered should work around the problem
*/ */
.parent_names = (const char *[]){ "fixme", .parent_data = (const struct clk_parent_data []) {
"ao_cts_rtc_oscin" }, { .name = "fixme", .index = -1, },
{ .hw = &ao_cts_rtc_oscin.hw },
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -261,14 +271,6 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = { ...@@ -261,14 +271,6 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
.num = NR_CLKS, .num = NR_CLKS,
}; };
static const struct meson_aoclk_input gxbb_aoclk_inputs[] = {
{ .name = "xtal", .required = true, },
{ .name = "mpeg-clk", .required = true, },
{. name = "ext-32k-0", .required = false, },
{. name = "ext-32k-1", .required = false, },
{. name = "ext-32k-2", .required = false, },
};
static const struct meson_aoclk_data gxbb_aoclkc_data = { static const struct meson_aoclk_data gxbb_aoclkc_data = {
.reset_reg = AO_RTI_GEN_CNTL_REG0, .reset_reg = AO_RTI_GEN_CNTL_REG0,
.num_reset = ARRAY_SIZE(gxbb_aoclk_reset), .num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
...@@ -276,9 +278,6 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = { ...@@ -276,9 +278,6 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = {
.num_clks = ARRAY_SIZE(gxbb_aoclk), .num_clks = ARRAY_SIZE(gxbb_aoclk),
.clks = gxbb_aoclk, .clks = gxbb_aoclk,
.hw_data = &gxbb_aoclk_onecell_data, .hw_data = &gxbb_aoclk_onecell_data,
.inputs = gxbb_aoclk_inputs,
.num_inputs = ARRAY_SIZE(gxbb_aoclk_inputs),
.input_prefix = IN_PREFIX,
}; };
static const struct of_device_id gxbb_aoclkc_match_table[] = { static const struct of_device_id gxbb_aoclkc_match_table[] = {
......
drivers/clk/meson/gxbb.c
View file @ b69337d3
...@@ -10,15 +10,12 @@ ...@@ -10,15 +10,12 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include "gxbb.h" #include "gxbb.h"
#include "clk-input.h"
#include "clk-regmap.h" #include "clk-regmap.h"
#include "clk-pll.h" #include "clk-pll.h"
#include "clk-mpll.h" #include "clk-mpll.h"
#include "meson-eeclk.h" #include "meson-eeclk.h"
#include "vid-pll-div.h" #include "vid-pll-div.h"
#define IN_PREFIX "ee-in-"
static DEFINE_SPINLOCK(meson_clk_lock); static DEFINE_SPINLOCK(meson_clk_lock);
static const struct pll_params_table gxbb_gp0_pll_params_table[] = { static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
...@@ -121,7 +118,9 @@ static struct clk_regmap gxbb_fixed_pll_dco = { ...@@ -121,7 +118,9 @@ static struct clk_regmap gxbb_fixed_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fixed_pll_dco", .name = "fixed_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -136,7 +135,9 @@ static struct clk_regmap gxbb_fixed_pll = { ...@@ -136,7 +135,9 @@ static struct clk_regmap gxbb_fixed_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fixed_pll", .name = "fixed_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "fixed_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_fixed_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock won't ever change at runtime so * This clock won't ever change at runtime so
...@@ -151,7 +152,9 @@ static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { ...@@ -151,7 +152,9 @@ static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_pre_mult", .name = "hdmi_pll_pre_mult",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -192,7 +195,9 @@ static struct clk_regmap gxbb_hdmi_pll_dco = { ...@@ -192,7 +195,9 @@ static struct clk_regmap gxbb_hdmi_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_dco", .name = "hdmi_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_pre_mult" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_hdmi_pll_pre_mult.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* Display directly handle hdmi pll registers ATM, we need * Display directly handle hdmi pll registers ATM, we need
...@@ -244,7 +249,9 @@ static struct clk_regmap gxl_hdmi_pll_dco = { ...@@ -244,7 +249,9 @@ static struct clk_regmap gxl_hdmi_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_dco", .name = "hdmi_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
/* /*
* Display directly handle hdmi pll registers ATM, we need * Display directly handle hdmi pll registers ATM, we need
...@@ -264,7 +271,9 @@ static struct clk_regmap gxbb_hdmi_pll_od = { ...@@ -264,7 +271,9 @@ static struct clk_regmap gxbb_hdmi_pll_od = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od", .name = "hdmi_pll_od",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_hdmi_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
}, },
...@@ -280,7 +289,9 @@ static struct clk_regmap gxbb_hdmi_pll_od2 = { ...@@ -280,7 +289,9 @@ static struct clk_regmap gxbb_hdmi_pll_od2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od2", .name = "hdmi_pll_od2",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_od" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_hdmi_pll_od.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
}, },
...@@ -296,7 +307,9 @@ static struct clk_regmap gxbb_hdmi_pll = { ...@@ -296,7 +307,9 @@ static struct clk_regmap gxbb_hdmi_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll", .name = "hdmi_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_od2" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_hdmi_pll_od2.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
}, },
...@@ -312,7 +325,9 @@ static struct clk_regmap gxl_hdmi_pll_od = { ...@@ -312,7 +325,9 @@ static struct clk_regmap gxl_hdmi_pll_od = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od", .name = "hdmi_pll_od",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&gxl_hdmi_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
}, },
...@@ -328,7 +343,9 @@ static struct clk_regmap gxl_hdmi_pll_od2 = { ...@@ -328,7 +343,9 @@ static struct clk_regmap gxl_hdmi_pll_od2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od2", .name = "hdmi_pll_od2",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_od" }, .parent_hws = (const struct clk_hw *[]) {
&gxl_hdmi_pll_od.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
}, },
...@@ -344,7 +361,9 @@ static struct clk_regmap gxl_hdmi_pll = { ...@@ -344,7 +361,9 @@ static struct clk_regmap gxl_hdmi_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll", .name = "hdmi_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_od2" }, .parent_hws = (const struct clk_hw *[]) {
&gxl_hdmi_pll_od2.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
}, },
...@@ -381,7 +400,9 @@ static struct clk_regmap gxbb_sys_pll_dco = { ...@@ -381,7 +400,9 @@ static struct clk_regmap gxbb_sys_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys_pll_dco", .name = "sys_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -396,7 +417,9 @@ static struct clk_regmap gxbb_sys_pll = { ...@@ -396,7 +417,9 @@ static struct clk_regmap gxbb_sys_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys_pll", .name = "sys_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "sys_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_sys_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -442,7 +465,9 @@ static struct clk_regmap gxbb_gp0_pll_dco = { ...@@ -442,7 +465,9 @@ static struct clk_regmap gxbb_gp0_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp0_pll_dco", .name = "gp0_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -494,7 +519,9 @@ static struct clk_regmap gxl_gp0_pll_dco = { ...@@ -494,7 +519,9 @@ static struct clk_regmap gxl_gp0_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp0_pll_dco", .name = "gp0_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -509,7 +536,17 @@ static struct clk_regmap gxbb_gp0_pll = { ...@@ -509,7 +536,17 @@ static struct clk_regmap gxbb_gp0_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp0_pll", .name = "gp0_pll",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "gp0_pll_dco" }, .parent_data = &(const struct clk_parent_data) {
/*
* Note:
* GXL and GXBB have different gp0_pll_dco (with
* different struct clk_hw). We fallback to the global
* naming string mechanism so gp0_pll picks up the
* appropriate one.
*/
.name = "gp0_pll_dco",
.index = -1,
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -521,7 +558,9 @@ static struct clk_fixed_factor gxbb_fclk_div2_div = { ...@@ -521,7 +558,9 @@ static struct clk_fixed_factor gxbb_fclk_div2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div2_div", .name = "fclk_div2_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_fixed_pll.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -534,7 +573,9 @@ static struct clk_regmap gxbb_fclk_div2 = { ...@@ -534,7 +573,9 @@ static struct clk_regmap gxbb_fclk_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div2", .name = "fclk_div2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div2_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_fclk_div2_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_IS_CRITICAL, .flags = CLK_IS_CRITICAL,
}, },
...@@ -546,7 +587,7 @@ static struct clk_fixed_factor gxbb_fclk_div3_div = { ...@@ -546,7 +587,7 @@ static struct clk_fixed_factor gxbb_fclk_div3_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div3_div", .name = "fclk_div3_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -559,7 +600,9 @@ static struct clk_regmap gxbb_fclk_div3 = { ...@@ -559,7 +600,9 @@ static struct clk_regmap gxbb_fclk_div3 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div3", .name = "fclk_div3",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div3_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_fclk_div3_div.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* FIXME: * FIXME:
...@@ -582,7 +625,7 @@ static struct clk_fixed_factor gxbb_fclk_div4_div = { ...@@ -582,7 +625,7 @@ static struct clk_fixed_factor gxbb_fclk_div4_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div4_div", .name = "fclk_div4_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -595,7 +638,9 @@ static struct clk_regmap gxbb_fclk_div4 = { ...@@ -595,7 +638,9 @@ static struct clk_regmap gxbb_fclk_div4 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div4", .name = "fclk_div4",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div4_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_fclk_div4_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -606,7 +651,7 @@ static struct clk_fixed_factor gxbb_fclk_div5_div = { ...@@ -606,7 +651,7 @@ static struct clk_fixed_factor gxbb_fclk_div5_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div5_div", .name = "fclk_div5_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -619,7 +664,9 @@ static struct clk_regmap gxbb_fclk_div5 = { ...@@ -619,7 +664,9 @@ static struct clk_regmap gxbb_fclk_div5 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div5", .name = "fclk_div5",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div5_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_fclk_div5_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -630,7 +677,7 @@ static struct clk_fixed_factor gxbb_fclk_div7_div = { ...@@ -630,7 +677,7 @@ static struct clk_fixed_factor gxbb_fclk_div7_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div7_div", .name = "fclk_div7_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -643,7 +690,9 @@ static struct clk_regmap gxbb_fclk_div7 = { ...@@ -643,7 +690,9 @@ static struct clk_regmap gxbb_fclk_div7 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div7", .name = "fclk_div7",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div7_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_fclk_div7_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -657,7 +706,7 @@ static struct clk_regmap gxbb_mpll_prediv = { ...@@ -657,7 +706,7 @@ static struct clk_regmap gxbb_mpll_prediv = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll_prediv", .name = "mpll_prediv",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -684,7 +733,9 @@ static struct clk_regmap gxbb_mpll0_div = { ...@@ -684,7 +733,9 @@ static struct clk_regmap gxbb_mpll0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0_div", .name = "mpll0_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -697,7 +748,7 @@ static struct clk_regmap gxbb_mpll0 = { ...@@ -697,7 +748,7 @@ static struct clk_regmap gxbb_mpll0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0", .name = "mpll0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll0_div" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -725,7 +776,9 @@ static struct clk_regmap gxbb_mpll1_div = { ...@@ -725,7 +776,9 @@ static struct clk_regmap gxbb_mpll1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1_div", .name = "mpll1_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -738,7 +791,7 @@ static struct clk_regmap gxbb_mpll1 = { ...@@ -738,7 +791,7 @@ static struct clk_regmap gxbb_mpll1 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1", .name = "mpll1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll1_div" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -766,7 +819,9 @@ static struct clk_regmap gxbb_mpll2_div = { ...@@ -766,7 +819,9 @@ static struct clk_regmap gxbb_mpll2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2_div", .name = "mpll2_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -779,16 +834,21 @@ static struct clk_regmap gxbb_mpll2 = { ...@@ -779,16 +834,21 @@ static struct clk_regmap gxbb_mpll2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2", .name = "mpll2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll2_div" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
static const char * const clk81_parent_names[] = { static const struct clk_parent_data clk81_parent_data[] = {
IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", { .fw_name = "xtal", },
"fclk_div3", "fclk_div5" { .hw = &gxbb_fclk_div7.hw },
{ .hw = &gxbb_mpll1.hw },
{ .hw = &gxbb_mpll2.hw },
{ .hw = &gxbb_fclk_div4.hw },
{ .hw = &gxbb_fclk_div3.hw },
{ .hw = &gxbb_fclk_div5.hw },
}; };
static struct clk_regmap gxbb_mpeg_clk_sel = { static struct clk_regmap gxbb_mpeg_clk_sel = {
...@@ -806,8 +866,8 @@ static struct clk_regmap gxbb_mpeg_clk_sel = { ...@@ -806,8 +866,8 @@ static struct clk_regmap gxbb_mpeg_clk_sel = {
* xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
* fclk_div4, fclk_div3, fclk_div5 * fclk_div4, fclk_div3, fclk_div5
*/ */
.parent_names = clk81_parent_names, .parent_data = clk81_parent_data,
.num_parents = ARRAY_SIZE(clk81_parent_names), .num_parents = ARRAY_SIZE(clk81_parent_data),
}, },
}; };
...@@ -820,7 +880,9 @@ static struct clk_regmap gxbb_mpeg_clk_div = { ...@@ -820,7 +880,9 @@ static struct clk_regmap gxbb_mpeg_clk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div", .name = "mpeg_clk_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "mpeg_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mpeg_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -834,7 +896,9 @@ static struct clk_regmap gxbb_clk81 = { ...@@ -834,7 +896,9 @@ static struct clk_regmap gxbb_clk81 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "clk81", .name = "clk81",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpeg_clk_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mpeg_clk_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_IS_CRITICAL, .flags = CLK_IS_CRITICAL,
}, },
...@@ -850,7 +914,10 @@ static struct clk_regmap gxbb_sar_adc_clk_sel = { ...@@ -850,7 +914,10 @@ static struct clk_regmap gxbb_sar_adc_clk_sel = {
.name = "sar_adc_clk_sel", .name = "sar_adc_clk_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
/* NOTE: The datasheet doesn't list the parents for bit 10 */ /* NOTE: The datasheet doesn't list the parents for bit 10 */
.parent_names = (const char *[]){ IN_PREFIX "xtal", "clk81", }, .parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal", },
{ .hw = &gxbb_clk81.hw },
},
.num_parents = 2, .num_parents = 2,
}, },
}; };
...@@ -864,7 +931,9 @@ static struct clk_regmap gxbb_sar_adc_clk_div = { ...@@ -864,7 +931,9 @@ static struct clk_regmap gxbb_sar_adc_clk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sar_adc_clk_div", .name = "sar_adc_clk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sar_adc_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_sar_adc_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -877,7 +946,9 @@ static struct clk_regmap gxbb_sar_adc_clk = { ...@@ -877,7 +946,9 @@ static struct clk_regmap gxbb_sar_adc_clk = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sar_adc_clk", .name = "sar_adc_clk",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sar_adc_clk_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_sar_adc_clk_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -888,9 +959,15 @@ static struct clk_regmap gxbb_sar_adc_clk = { ...@@ -888,9 +959,15 @@ static struct clk_regmap gxbb_sar_adc_clk = {
* muxed by a glitch-free switch. * muxed by a glitch-free switch.
*/ */
static const char * const gxbb_mali_0_1_parent_names[] = { static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
IN_PREFIX "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", { .fw_name = "xtal", },
"fclk_div4", "fclk_div3", "fclk_div5" { .hw = &gxbb_gp0_pll.hw },
{ .hw = &gxbb_mpll2.hw },
{ .hw = &gxbb_mpll1.hw },
{ .hw = &gxbb_fclk_div7.hw },
{ .hw = &gxbb_fclk_div4.hw },
{ .hw = &gxbb_fclk_div3.hw },
{ .hw = &gxbb_fclk_div5.hw },
}; };
static struct clk_regmap gxbb_mali_0_sel = { static struct clk_regmap gxbb_mali_0_sel = {
...@@ -907,7 +984,7 @@ static struct clk_regmap gxbb_mali_0_sel = { ...@@ -907,7 +984,7 @@ static struct clk_regmap gxbb_mali_0_sel = {
* xtal, gp0_pll, mpll2, mpll1, fclk_div7, * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
* fclk_div4, fclk_div3, fclk_div5 * fclk_div4, fclk_div3, fclk_div5
*/ */
.parent_names = gxbb_mali_0_1_parent_names, .parent_data = gxbb_mali_0_1_parent_data,
.num_parents = 8, .num_parents = 8,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -922,7 +999,9 @@ static struct clk_regmap gxbb_mali_0_div = { ...@@ -922,7 +999,9 @@ static struct clk_regmap gxbb_mali_0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_0_div", .name = "mali_0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "mali_0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mali_0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -936,7 +1015,9 @@ static struct clk_regmap gxbb_mali_0 = { ...@@ -936,7 +1015,9 @@ static struct clk_regmap gxbb_mali_0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_0", .name = "mali_0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mali_0_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mali_0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -956,7 +1037,7 @@ static struct clk_regmap gxbb_mali_1_sel = { ...@@ -956,7 +1037,7 @@ static struct clk_regmap gxbb_mali_1_sel = {
* xtal, gp0_pll, mpll2, mpll1, fclk_div7, * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
* fclk_div4, fclk_div3, fclk_div5 * fclk_div4, fclk_div3, fclk_div5
*/ */
.parent_names = gxbb_mali_0_1_parent_names, .parent_data = gxbb_mali_0_1_parent_data,
.num_parents = 8, .num_parents = 8,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -971,7 +1052,9 @@ static struct clk_regmap gxbb_mali_1_div = { ...@@ -971,7 +1052,9 @@ static struct clk_regmap gxbb_mali_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_1_div", .name = "mali_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "mali_1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mali_1_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -985,14 +1068,17 @@ static struct clk_regmap gxbb_mali_1 = { ...@@ -985,14 +1068,17 @@ static struct clk_regmap gxbb_mali_1 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_1", .name = "mali_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mali_1_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mali_1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
static const char * const gxbb_mali_parent_names[] = { static const struct clk_hw *gxbb_mali_parent_hws[] = {
"mali_0", "mali_1" &gxbb_mali_0.hw,
&gxbb_mali_1.hw,
}; };
static struct clk_regmap gxbb_mali = { static struct clk_regmap gxbb_mali = {
...@@ -1004,7 +1090,7 @@ static struct clk_regmap gxbb_mali = { ...@@ -1004,7 +1090,7 @@ static struct clk_regmap gxbb_mali = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali", .name = "mali",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = gxbb_mali_parent_names, .parent_hws = gxbb_mali_parent_hws,
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -1021,7 +1107,11 @@ static struct clk_regmap gxbb_cts_amclk_sel = { ...@@ -1021,7 +1107,11 @@ static struct clk_regmap gxbb_cts_amclk_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_amclk_sel", .name = "cts_amclk_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mpll0.hw,
&gxbb_mpll1.hw,
&gxbb_mpll2.hw,
},
.num_parents = 3, .num_parents = 3,
}, },
}; };
...@@ -1036,7 +1126,9 @@ static struct clk_regmap gxbb_cts_amclk_div = { ...@@ -1036,7 +1126,9 @@ static struct clk_regmap gxbb_cts_amclk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_amclk_div", .name = "cts_amclk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "cts_amclk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_cts_amclk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1050,7 +1142,9 @@ static struct clk_regmap gxbb_cts_amclk = { ...@@ -1050,7 +1142,9 @@ static struct clk_regmap gxbb_cts_amclk = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_amclk", .name = "cts_amclk",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_amclk_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_cts_amclk_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1067,7 +1161,11 @@ static struct clk_regmap gxbb_cts_mclk_i958_sel = { ...@@ -1067,7 +1161,11 @@ static struct clk_regmap gxbb_cts_mclk_i958_sel = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cts_mclk_i958_sel", .name = "cts_mclk_i958_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_mpll0.hw,
&gxbb_mpll1.hw,
&gxbb_mpll2.hw,
},
.num_parents = 3, .num_parents = 3,
}, },
}; };
...@@ -1082,7 +1180,9 @@ static struct clk_regmap gxbb_cts_mclk_i958_div = { ...@@ -1082,7 +1180,9 @@ static struct clk_regmap gxbb_cts_mclk_i958_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cts_mclk_i958_div", .name = "cts_mclk_i958_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "cts_mclk_i958_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_cts_mclk_i958_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1096,7 +1196,9 @@ static struct clk_regmap gxbb_cts_mclk_i958 = { ...@@ -1096,7 +1196,9 @@ static struct clk_regmap gxbb_cts_mclk_i958 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_mclk_i958", .name = "cts_mclk_i958",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_mclk_i958_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_cts_mclk_i958_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1111,7 +1213,10 @@ static struct clk_regmap gxbb_cts_i958 = { ...@@ -1111,7 +1213,10 @@ static struct clk_regmap gxbb_cts_i958 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_i958", .name = "cts_i958",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_cts_amclk.hw,
&gxbb_cts_mclk_i958.hw
},
.num_parents = 2, .num_parents = 2,
/* /*
*The parent is specific to origin of the audio data. Let the *The parent is specific to origin of the audio data. Let the
...@@ -1121,6 +1226,33 @@ static struct clk_regmap gxbb_cts_i958 = { ...@@ -1121,6 +1226,33 @@ static struct clk_regmap gxbb_cts_i958 = {
}, },
}; };
static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
{ .fw_name = "xtal", },
/*
* FIXME: This clock is provided by the ao clock controller but the
* clock is not yet part of the binding of this controller, so string
* name must be use to set this parent.
*/
{ .name = "cts_slow_oscin", .index = -1 },
{ .hw = &gxbb_fclk_div3.hw },
{ .hw = &gxbb_fclk_div5.hw },
};
static struct clk_regmap gxbb_32k_clk_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_32K_CLK_CNTL,
.mask = 0x3,
.shift = 16,
},
.hw.init = &(struct clk_init_data){
.name = "32k_clk_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = gxbb_32k_clk_parent_data,
.num_parents = 4,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap gxbb_32k_clk_div = { static struct clk_regmap gxbb_32k_clk_div = {
.data = &(struct clk_regmap_div_data){ .data = &(struct clk_regmap_div_data){
.offset = HHI_32K_CLK_CNTL, .offset = HHI_32K_CLK_CNTL,
...@@ -1130,7 +1262,9 @@ static struct clk_regmap gxbb_32k_clk_div = { ...@@ -1130,7 +1262,9 @@ static struct clk_regmap gxbb_32k_clk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "32k_clk_div", .name = "32k_clk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "32k_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_32k_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
}, },
...@@ -1144,34 +1278,20 @@ static struct clk_regmap gxbb_32k_clk = { ...@@ -1144,34 +1278,20 @@ static struct clk_regmap gxbb_32k_clk = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "32k_clk", .name = "32k_clk",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "32k_clk_div" }, .parent_hws = (const struct clk_hw *[]) {
.num_parents = 1, &gxbb_32k_clk_div.hw
.flags = CLK_SET_RATE_PARENT,
},
};
static const char * const gxbb_32k_clk_parent_names[] = {
IN_PREFIX "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
};
static struct clk_regmap gxbb_32k_clk_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_32K_CLK_CNTL,
.mask = 0x3,
.shift = 16,
}, },
.hw.init = &(struct clk_init_data){ .num_parents = 1,
.name = "32k_clk_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = gxbb_32k_clk_parent_names,
.num_parents = 4,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
static const char * const gxbb_sd_emmc_clk0_parent_names[] = { static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", { .fw_name = "xtal", },
{ .hw = &gxbb_fclk_div2.hw },
{ .hw = &gxbb_fclk_div3.hw },
{ .hw = &gxbb_fclk_div5.hw },
{ .hw = &gxbb_fclk_div7.hw },
/* /*
* Following these parent clocks, we should also have had mpll2, mpll3 * Following these parent clocks, we should also have had mpll2, mpll3
* and gp0_pll but these clocks are too precious to be used here. All * and gp0_pll but these clocks are too precious to be used here. All
...@@ -1190,8 +1310,8 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { ...@@ -1190,8 +1310,8 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_a_clk0_sel", .name = "sd_emmc_a_clk0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = gxbb_sd_emmc_clk0_parent_names, .parent_data = gxbb_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1206,7 +1326,9 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { ...@@ -1206,7 +1326,9 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_a_clk0_div", .name = "sd_emmc_a_clk0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_sd_emmc_a_clk0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1220,7 +1342,9 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0 = { ...@@ -1220,7 +1342,9 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sd_emmc_a_clk0", .name = "sd_emmc_a_clk0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_sd_emmc_a_clk0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1236,8 +1360,8 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { ...@@ -1236,8 +1360,8 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_sel", .name = "sd_emmc_b_clk0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = gxbb_sd_emmc_clk0_parent_names, .parent_data = gxbb_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1252,7 +1376,9 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { ...@@ -1252,7 +1376,9 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_div", .name = "sd_emmc_b_clk0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_sd_emmc_b_clk0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1266,7 +1392,9 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0 = { ...@@ -1266,7 +1392,9 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sd_emmc_b_clk0", .name = "sd_emmc_b_clk0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_sd_emmc_b_clk0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1282,8 +1410,8 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { ...@@ -1282,8 +1410,8 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_sel", .name = "sd_emmc_c_clk0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = gxbb_sd_emmc_clk0_parent_names, .parent_data = gxbb_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1298,7 +1426,9 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { ...@@ -1298,7 +1426,9 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_div", .name = "sd_emmc_c_clk0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_sd_emmc_c_clk0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1312,7 +1442,9 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = { ...@@ -1312,7 +1442,9 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sd_emmc_c_clk0", .name = "sd_emmc_c_clk0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_sd_emmc_c_clk0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1320,8 +1452,11 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = { ...@@ -1320,8 +1452,11 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
/* VPU Clock */ /* VPU Clock */
static const char * const gxbb_vpu_parent_names[] = { static const struct clk_hw *gxbb_vpu_parent_hws[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" &gxbb_fclk_div4.hw,
&gxbb_fclk_div3.hw,
&gxbb_fclk_div5.hw,
&gxbb_fclk_div7.hw,
}; };
static struct clk_regmap gxbb_vpu_0_sel = { static struct clk_regmap gxbb_vpu_0_sel = {
...@@ -1337,8 +1472,8 @@ static struct clk_regmap gxbb_vpu_0_sel = { ...@@ -1337,8 +1472,8 @@ static struct clk_regmap gxbb_vpu_0_sel = {
* bits 9:10 selects from 4 possible parents: * bits 9:10 selects from 4 possible parents:
* fclk_div4, fclk_div3, fclk_div5, fclk_div7, * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
*/ */
.parent_names = gxbb_vpu_parent_names, .parent_hws = gxbb_vpu_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -1352,7 +1487,7 @@ static struct clk_regmap gxbb_vpu_0_div = { ...@@ -1352,7 +1487,7 @@ static struct clk_regmap gxbb_vpu_0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_0_div", .name = "vpu_0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vpu_0_sel" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1366,7 +1501,7 @@ static struct clk_regmap gxbb_vpu_0 = { ...@@ -1366,7 +1501,7 @@ static struct clk_regmap gxbb_vpu_0 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vpu_0", .name = "vpu_0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vpu_0_div" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1385,8 +1520,8 @@ static struct clk_regmap gxbb_vpu_1_sel = { ...@@ -1385,8 +1520,8 @@ static struct clk_regmap gxbb_vpu_1_sel = {
* bits 25:26 selects from 4 possible parents: * bits 25:26 selects from 4 possible parents:
* fclk_div4, fclk_div3, fclk_div5, fclk_div7, * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
*/ */
.parent_names = gxbb_vpu_parent_names, .parent_hws = gxbb_vpu_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -1400,7 +1535,7 @@ static struct clk_regmap gxbb_vpu_1_div = { ...@@ -1400,7 +1535,7 @@ static struct clk_regmap gxbb_vpu_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_1_div", .name = "vpu_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vpu_1_sel" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1414,7 +1549,7 @@ static struct clk_regmap gxbb_vpu_1 = { ...@@ -1414,7 +1549,7 @@ static struct clk_regmap gxbb_vpu_1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vpu_1", .name = "vpu_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vpu_1_div" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1433,7 +1568,10 @@ static struct clk_regmap gxbb_vpu = { ...@@ -1433,7 +1568,10 @@ static struct clk_regmap gxbb_vpu = {
* bit 31 selects from 2 possible parents: * bit 31 selects from 2 possible parents:
* vpu_0 or vpu_1 * vpu_0 or vpu_1
*/ */
.parent_names = (const char *[]){ "vpu_0", "vpu_1" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vpu_0.hw,
&gxbb_vpu_1.hw
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -1441,8 +1579,11 @@ static struct clk_regmap gxbb_vpu = { ...@@ -1441,8 +1579,11 @@ static struct clk_regmap gxbb_vpu = {
/* VAPB Clock */ /* VAPB Clock */
static const char * const gxbb_vapb_parent_names[] = { static const struct clk_hw *gxbb_vapb_parent_hws[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" &gxbb_fclk_div4.hw,
&gxbb_fclk_div3.hw,
&gxbb_fclk_div5.hw,
&gxbb_fclk_div7.hw,
}; };
static struct clk_regmap gxbb_vapb_0_sel = { static struct clk_regmap gxbb_vapb_0_sel = {
...@@ -1458,8 +1599,8 @@ static struct clk_regmap gxbb_vapb_0_sel = { ...@@ -1458,8 +1599,8 @@ static struct clk_regmap gxbb_vapb_0_sel = {
* bits 9:10 selects from 4 possible parents: * bits 9:10 selects from 4 possible parents:
* fclk_div4, fclk_div3, fclk_div5, fclk_div7, * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
*/ */
.parent_names = gxbb_vapb_parent_names, .parent_hws = gxbb_vapb_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -1473,7 +1614,9 @@ static struct clk_regmap gxbb_vapb_0_div = { ...@@ -1473,7 +1614,9 @@ static struct clk_regmap gxbb_vapb_0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vapb_0_div", .name = "vapb_0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vapb_0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vapb_0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1487,7 +1630,9 @@ static struct clk_regmap gxbb_vapb_0 = { ...@@ -1487,7 +1630,9 @@ static struct clk_regmap gxbb_vapb_0 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vapb_0", .name = "vapb_0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vapb_0_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vapb_0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1506,8 +1651,8 @@ static struct clk_regmap gxbb_vapb_1_sel = { ...@@ -1506,8 +1651,8 @@ static struct clk_regmap gxbb_vapb_1_sel = {
* bits 25:26 selects from 4 possible parents: * bits 25:26 selects from 4 possible parents:
* fclk_div4, fclk_div3, fclk_div5, fclk_div7, * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
*/ */
.parent_names = gxbb_vapb_parent_names, .parent_hws = gxbb_vapb_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -1521,7 +1666,9 @@ static struct clk_regmap gxbb_vapb_1_div = { ...@@ -1521,7 +1666,9 @@ static struct clk_regmap gxbb_vapb_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vapb_1_div", .name = "vapb_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vapb_1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vapb_1_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1535,7 +1682,9 @@ static struct clk_regmap gxbb_vapb_1 = { ...@@ -1535,7 +1682,9 @@ static struct clk_regmap gxbb_vapb_1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vapb_1", .name = "vapb_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vapb_1_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vapb_1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1554,7 +1703,10 @@ static struct clk_regmap gxbb_vapb_sel = { ...@@ -1554,7 +1703,10 @@ static struct clk_regmap gxbb_vapb_sel = {
* bit 31 selects from 2 possible parents: * bit 31 selects from 2 possible parents:
* vapb_0 or vapb_1 * vapb_0 or vapb_1
*/ */
.parent_names = (const char *[]){ "vapb_0", "vapb_1" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vapb_0.hw,
&gxbb_vapb_1.hw
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -1568,7 +1720,7 @@ static struct clk_regmap gxbb_vapb = { ...@@ -1568,7 +1720,7 @@ static struct clk_regmap gxbb_vapb = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vapb", .name = "vapb",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vapb_sel" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1592,13 +1744,33 @@ static struct clk_regmap gxbb_vid_pll_div = { ...@@ -1592,13 +1744,33 @@ static struct clk_regmap gxbb_vid_pll_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vid_pll_div", .name = "vid_pll_div",
.ops = &meson_vid_pll_div_ro_ops, .ops = &meson_vid_pll_div_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll" }, .parent_data = &(const struct clk_parent_data) {
/*
* Note:
* GXL and GXBB have different hdmi_plls (with
* different struct clk_hw). We fallback to the global
* naming string mechanism so vid_pll_div picks up the
* appropriate one.
*/
.name = "hdmi_pll",
.index = -1,
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" }; static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
{ .hw = &gxbb_vid_pll_div.hw },
/*
* Note:
* GXL and GXBB have different hdmi_plls (with
* different struct clk_hw). We fallback to the global
* naming string mechanism so vid_pll_div picks up the
* appropriate one.
*/
{ .name = "hdmi_pll", .index = -1 },
};
static struct clk_regmap gxbb_vid_pll_sel = { static struct clk_regmap gxbb_vid_pll_sel = {
.data = &(struct clk_regmap_mux_data){ .data = &(struct clk_regmap_mux_data){
...@@ -1613,8 +1785,8 @@ static struct clk_regmap gxbb_vid_pll_sel = { ...@@ -1613,8 +1785,8 @@ static struct clk_regmap gxbb_vid_pll_sel = {
* bit 18 selects from 2 possible parents: * bit 18 selects from 2 possible parents:
* vid_pll_div or hdmi_pll * vid_pll_div or hdmi_pll
*/ */
.parent_names = gxbb_vid_pll_parent_names, .parent_data = gxbb_vid_pll_parent_data,
.num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_names), .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -1627,15 +1799,22 @@ static struct clk_regmap gxbb_vid_pll = { ...@@ -1627,15 +1799,22 @@ static struct clk_regmap gxbb_vid_pll = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vid_pll", .name = "vid_pll",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vid_pll_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vid_pll_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
}; };
static const char * const gxbb_vclk_parent_names[] = { static const struct clk_hw *gxbb_vclk_parent_hws[] = {
"vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll", &gxbb_vid_pll.hw,
"fclk_div7", "mpll1", &gxbb_fclk_div4.hw,
&gxbb_fclk_div3.hw,
&gxbb_fclk_div5.hw,
&gxbb_vid_pll.hw,
&gxbb_fclk_div7.hw,
&gxbb_mpll1.hw,
}; };
static struct clk_regmap gxbb_vclk_sel = { static struct clk_regmap gxbb_vclk_sel = {
...@@ -1652,8 +1831,8 @@ static struct clk_regmap gxbb_vclk_sel = { ...@@ -1652,8 +1831,8 @@ static struct clk_regmap gxbb_vclk_sel = {
* vid_pll, fclk_div4, fclk_div3, fclk_div5, * vid_pll, fclk_div4, fclk_div3, fclk_div5,
* vid_pll, fclk_div7, mp1 * vid_pll, fclk_div7, mp1
*/ */
.parent_names = gxbb_vclk_parent_names, .parent_hws = gxbb_vclk_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vclk_parent_names), .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -1672,8 +1851,8 @@ static struct clk_regmap gxbb_vclk2_sel = { ...@@ -1672,8 +1851,8 @@ static struct clk_regmap gxbb_vclk2_sel = {
* vid_pll, fclk_div4, fclk_div3, fclk_div5, * vid_pll, fclk_div4, fclk_div3, fclk_div5,
* vid_pll, fclk_div7, mp1 * vid_pll, fclk_div7, mp1
*/ */
.parent_names = gxbb_vclk_parent_names, .parent_hws = gxbb_vclk_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vclk_parent_names), .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -1686,7 +1865,7 @@ static struct clk_regmap gxbb_vclk_input = { ...@@ -1686,7 +1865,7 @@ static struct clk_regmap gxbb_vclk_input = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_input", .name = "vclk_input",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk_sel" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1700,7 +1879,7 @@ static struct clk_regmap gxbb_vclk2_input = { ...@@ -1700,7 +1879,7 @@ static struct clk_regmap gxbb_vclk2_input = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_input", .name = "vclk2_input",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2_sel" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1715,7 +1894,9 @@ static struct clk_regmap gxbb_vclk_div = { ...@@ -1715,7 +1894,9 @@ static struct clk_regmap gxbb_vclk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div", .name = "vclk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vclk_input" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vclk_input.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE, .flags = CLK_GET_RATE_NOCACHE,
}, },
...@@ -1730,7 +1911,9 @@ static struct clk_regmap gxbb_vclk2_div = { ...@@ -1730,7 +1911,9 @@ static struct clk_regmap gxbb_vclk2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div", .name = "vclk2_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vclk2_input" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vclk2_input.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE, .flags = CLK_GET_RATE_NOCACHE,
}, },
...@@ -1744,7 +1927,7 @@ static struct clk_regmap gxbb_vclk = { ...@@ -1744,7 +1927,7 @@ static struct clk_regmap gxbb_vclk = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk", .name = "vclk",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk_div" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1758,7 +1941,7 @@ static struct clk_regmap gxbb_vclk2 = { ...@@ -1758,7 +1941,7 @@ static struct clk_regmap gxbb_vclk2 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2", .name = "vclk2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2_div" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1772,7 +1955,7 @@ static struct clk_regmap gxbb_vclk_div1 = { ...@@ -1772,7 +1955,7 @@ static struct clk_regmap gxbb_vclk_div1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_div1", .name = "vclk_div1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1786,7 +1969,7 @@ static struct clk_regmap gxbb_vclk_div2_en = { ...@@ -1786,7 +1969,7 @@ static struct clk_regmap gxbb_vclk_div2_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_div2_en", .name = "vclk_div2_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1800,7 +1983,7 @@ static struct clk_regmap gxbb_vclk_div4_en = { ...@@ -1800,7 +1983,7 @@ static struct clk_regmap gxbb_vclk_div4_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_div4_en", .name = "vclk_div4_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1814,7 +1997,7 @@ static struct clk_regmap gxbb_vclk_div6_en = { ...@@ -1814,7 +1997,7 @@ static struct clk_regmap gxbb_vclk_div6_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_div6_en", .name = "vclk_div6_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1828,7 +2011,7 @@ static struct clk_regmap gxbb_vclk_div12_en = { ...@@ -1828,7 +2011,7 @@ static struct clk_regmap gxbb_vclk_div12_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk_div12_en", .name = "vclk_div12_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1842,7 +2025,7 @@ static struct clk_regmap gxbb_vclk2_div1 = { ...@@ -1842,7 +2025,7 @@ static struct clk_regmap gxbb_vclk2_div1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_div1", .name = "vclk2_div1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1856,7 +2039,7 @@ static struct clk_regmap gxbb_vclk2_div2_en = { ...@@ -1856,7 +2039,7 @@ static struct clk_regmap gxbb_vclk2_div2_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_div2_en", .name = "vclk2_div2_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1870,7 +2053,7 @@ static struct clk_regmap gxbb_vclk2_div4_en = { ...@@ -1870,7 +2053,7 @@ static struct clk_regmap gxbb_vclk2_div4_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_div4_en", .name = "vclk2_div4_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1884,7 +2067,7 @@ static struct clk_regmap gxbb_vclk2_div6_en = { ...@@ -1884,7 +2067,7 @@ static struct clk_regmap gxbb_vclk2_div6_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_div6_en", .name = "vclk2_div6_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1898,7 +2081,7 @@ static struct clk_regmap gxbb_vclk2_div12_en = { ...@@ -1898,7 +2081,7 @@ static struct clk_regmap gxbb_vclk2_div12_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vclk2_div12_en", .name = "vclk2_div12_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vclk2" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -1910,7 +2093,9 @@ static struct clk_fixed_factor gxbb_vclk_div2 = { ...@@ -1910,7 +2093,9 @@ static struct clk_fixed_factor gxbb_vclk_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div2", .name = "vclk_div2",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_div2_en" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vclk_div2_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1921,7 +2106,9 @@ static struct clk_fixed_factor gxbb_vclk_div4 = { ...@@ -1921,7 +2106,9 @@ static struct clk_fixed_factor gxbb_vclk_div4 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div4", .name = "vclk_div4",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_div4_en" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vclk_div4_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1932,7 +2119,9 @@ static struct clk_fixed_factor gxbb_vclk_div6 = { ...@@ -1932,7 +2119,9 @@ static struct clk_fixed_factor gxbb_vclk_div6 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div6", .name = "vclk_div6",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_div6_en" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vclk_div6_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1943,7 +2132,9 @@ static struct clk_fixed_factor gxbb_vclk_div12 = { ...@@ -1943,7 +2132,9 @@ static struct clk_fixed_factor gxbb_vclk_div12 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div12", .name = "vclk_div12",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_div12_en" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vclk_div12_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1954,7 +2145,9 @@ static struct clk_fixed_factor gxbb_vclk2_div2 = { ...@@ -1954,7 +2145,9 @@ static struct clk_fixed_factor gxbb_vclk2_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div2", .name = "vclk2_div2",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_div2_en" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vclk2_div2_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1965,7 +2158,9 @@ static struct clk_fixed_factor gxbb_vclk2_div4 = { ...@@ -1965,7 +2158,9 @@ static struct clk_fixed_factor gxbb_vclk2_div4 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div4", .name = "vclk2_div4",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_div4_en" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vclk2_div4_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1976,7 +2171,9 @@ static struct clk_fixed_factor gxbb_vclk2_div6 = { ...@@ -1976,7 +2171,9 @@ static struct clk_fixed_factor gxbb_vclk2_div6 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div6", .name = "vclk2_div6",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_div6_en" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vclk2_div6_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1987,16 +2184,25 @@ static struct clk_fixed_factor gxbb_vclk2_div12 = { ...@@ -1987,16 +2184,25 @@ static struct clk_fixed_factor gxbb_vclk2_div12 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div12", .name = "vclk2_div12",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_div12_en" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vclk2_div12_en.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
static const char * const gxbb_cts_parent_names[] = { static const struct clk_hw *gxbb_cts_parent_hws[] = {
"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", &gxbb_vclk_div1.hw,
"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", &gxbb_vclk_div2.hw,
"vclk2_div6", "vclk2_div12" &gxbb_vclk_div4.hw,
&gxbb_vclk_div6.hw,
&gxbb_vclk_div12.hw,
&gxbb_vclk2_div1.hw,
&gxbb_vclk2_div2.hw,
&gxbb_vclk2_div4.hw,
&gxbb_vclk2_div6.hw,
&gxbb_vclk2_div12.hw,
}; };
static struct clk_regmap gxbb_cts_enci_sel = { static struct clk_regmap gxbb_cts_enci_sel = {
...@@ -2009,8 +2215,8 @@ static struct clk_regmap gxbb_cts_enci_sel = { ...@@ -2009,8 +2215,8 @@ static struct clk_regmap gxbb_cts_enci_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_enci_sel", .name = "cts_enci_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = gxbb_cts_parent_names, .parent_hws = gxbb_cts_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_cts_parent_names), .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -2025,8 +2231,8 @@ static struct clk_regmap gxbb_cts_encp_sel = { ...@@ -2025,8 +2231,8 @@ static struct clk_regmap gxbb_cts_encp_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_encp_sel", .name = "cts_encp_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = gxbb_cts_parent_names, .parent_hws = gxbb_cts_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_cts_parent_names), .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -2041,18 +2247,25 @@ static struct clk_regmap gxbb_cts_vdac_sel = { ...@@ -2041,18 +2247,25 @@ static struct clk_regmap gxbb_cts_vdac_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_vdac_sel", .name = "cts_vdac_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = gxbb_cts_parent_names, .parent_hws = gxbb_cts_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_cts_parent_names), .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
/* TOFIX: add support for cts_tcon */ /* TOFIX: add support for cts_tcon */
static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
static const char * const gxbb_cts_hdmi_tx_parent_names[] = { static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", &gxbb_vclk_div1.hw,
"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", &gxbb_vclk_div2.hw,
"vclk2_div6", "vclk2_div12" &gxbb_vclk_div4.hw,
&gxbb_vclk_div6.hw,
&gxbb_vclk_div12.hw,
&gxbb_vclk2_div1.hw,
&gxbb_vclk2_div2.hw,
&gxbb_vclk2_div4.hw,
&gxbb_vclk2_div6.hw,
&gxbb_vclk2_div12.hw,
}; };
static struct clk_regmap gxbb_hdmi_tx_sel = { static struct clk_regmap gxbb_hdmi_tx_sel = {
...@@ -2071,8 +2284,8 @@ static struct clk_regmap gxbb_hdmi_tx_sel = { ...@@ -2071,8 +2284,8 @@ static struct clk_regmap gxbb_hdmi_tx_sel = {
* vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
* cts_tcon * cts_tcon
*/ */
.parent_names = gxbb_cts_hdmi_tx_parent_names, .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_names), .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -2085,7 +2298,9 @@ static struct clk_regmap gxbb_cts_enci = { ...@@ -2085,7 +2298,9 @@ static struct clk_regmap gxbb_cts_enci = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cts_enci", .name = "cts_enci",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_enci_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_cts_enci_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2099,7 +2314,9 @@ static struct clk_regmap gxbb_cts_encp = { ...@@ -2099,7 +2314,9 @@ static struct clk_regmap gxbb_cts_encp = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cts_encp", .name = "cts_encp",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_encp_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_cts_encp_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2113,7 +2330,9 @@ static struct clk_regmap gxbb_cts_vdac = { ...@@ -2113,7 +2330,9 @@ static struct clk_regmap gxbb_cts_vdac = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cts_vdac", .name = "cts_vdac",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_vdac_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_cts_vdac_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2127,7 +2346,9 @@ static struct clk_regmap gxbb_hdmi_tx = { ...@@ -2127,7 +2346,9 @@ static struct clk_regmap gxbb_hdmi_tx = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "hdmi_tx", .name = "hdmi_tx",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "hdmi_tx_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_hdmi_tx_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2135,8 +2356,11 @@ static struct clk_regmap gxbb_hdmi_tx = { ...@@ -2135,8 +2356,11 @@ static struct clk_regmap gxbb_hdmi_tx = {
/* HDMI Clocks */ /* HDMI Clocks */
static const char * const gxbb_hdmi_parent_names[] = { static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5" { .fw_name = "xtal", },
{ .hw = &gxbb_fclk_div4.hw },
{ .hw = &gxbb_fclk_div3.hw },
{ .hw = &gxbb_fclk_div5.hw },
}; };
static struct clk_regmap gxbb_hdmi_sel = { static struct clk_regmap gxbb_hdmi_sel = {
...@@ -2149,8 +2373,8 @@ static struct clk_regmap gxbb_hdmi_sel = { ...@@ -2149,8 +2373,8 @@ static struct clk_regmap gxbb_hdmi_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_sel", .name = "hdmi_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = gxbb_hdmi_parent_names, .parent_data = gxbb_hdmi_parent_data,
.num_parents = ARRAY_SIZE(gxbb_hdmi_parent_names), .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
}, },
}; };
...@@ -2164,7 +2388,7 @@ static struct clk_regmap gxbb_hdmi_div = { ...@@ -2164,7 +2388,7 @@ static struct clk_regmap gxbb_hdmi_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_div", .name = "hdmi_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "hdmi_sel" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE, .flags = CLK_GET_RATE_NOCACHE,
}, },
...@@ -2178,7 +2402,7 @@ static struct clk_regmap gxbb_hdmi = { ...@@ -2178,7 +2402,7 @@ static struct clk_regmap gxbb_hdmi = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "hdmi", .name = "hdmi",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "hdmi_div" }, .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
}, },
...@@ -2186,8 +2410,11 @@ static struct clk_regmap gxbb_hdmi = { ...@@ -2186,8 +2410,11 @@ static struct clk_regmap gxbb_hdmi = {
/* VDEC clocks */ /* VDEC clocks */
static const char * const gxbb_vdec_parent_names[] = { static const struct clk_hw *gxbb_vdec_parent_hws[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" &gxbb_fclk_div4.hw,
&gxbb_fclk_div3.hw,
&gxbb_fclk_div5.hw,
&gxbb_fclk_div7.hw,
}; };
static struct clk_regmap gxbb_vdec_1_sel = { static struct clk_regmap gxbb_vdec_1_sel = {
...@@ -2200,8 +2427,8 @@ static struct clk_regmap gxbb_vdec_1_sel = { ...@@ -2200,8 +2427,8 @@ static struct clk_regmap gxbb_vdec_1_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_1_sel", .name = "vdec_1_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = gxbb_vdec_parent_names, .parent_hws = gxbb_vdec_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -2216,7 +2443,9 @@ static struct clk_regmap gxbb_vdec_1_div = { ...@@ -2216,7 +2443,9 @@ static struct clk_regmap gxbb_vdec_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_1_div", .name = "vdec_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vdec_1_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2230,7 +2459,9 @@ static struct clk_regmap gxbb_vdec_1 = { ...@@ -2230,7 +2459,9 @@ static struct clk_regmap gxbb_vdec_1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vdec_1", .name = "vdec_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_1_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vdec_1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2246,8 +2477,8 @@ static struct clk_regmap gxbb_vdec_hevc_sel = { ...@@ -2246,8 +2477,8 @@ static struct clk_regmap gxbb_vdec_hevc_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_hevc_sel", .name = "vdec_hevc_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = gxbb_vdec_parent_names, .parent_hws = gxbb_vdec_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -2262,7 +2493,9 @@ static struct clk_regmap gxbb_vdec_hevc_div = { ...@@ -2262,7 +2493,9 @@ static struct clk_regmap gxbb_vdec_hevc_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_hevc_div", .name = "vdec_hevc_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_hevc_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vdec_hevc_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2276,7 +2509,9 @@ static struct clk_regmap gxbb_vdec_hevc = { ...@@ -2276,7 +2509,9 @@ static struct clk_regmap gxbb_vdec_hevc = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vdec_hevc", .name = "vdec_hevc",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_hevc_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_vdec_hevc_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2284,9 +2519,18 @@ static struct clk_regmap gxbb_vdec_hevc = { ...@@ -2284,9 +2519,18 @@ static struct clk_regmap gxbb_vdec_hevc = {
static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
9, 10, 11, 13, 14, }; 9, 10, 11, 13, 14, };
static const char * const gen_clk_parent_names[] = { static const struct clk_parent_data gen_clk_parent_data[] = {
IN_PREFIX "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2", { .fw_name = "xtal", },
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll", { .hw = &gxbb_vdec_1.hw },
{ .hw = &gxbb_vdec_hevc.hw },
{ .hw = &gxbb_mpll0.hw },
{ .hw = &gxbb_mpll1.hw },
{ .hw = &gxbb_mpll2.hw },
{ .hw = &gxbb_fclk_div4.hw },
{ .hw = &gxbb_fclk_div3.hw },
{ .hw = &gxbb_fclk_div5.hw },
{ .hw = &gxbb_fclk_div7.hw },
{ .hw = &gxbb_gp0_pll.hw },
}; };
static struct clk_regmap gxbb_gen_clk_sel = { static struct clk_regmap gxbb_gen_clk_sel = {
...@@ -2305,8 +2549,8 @@ static struct clk_regmap gxbb_gen_clk_sel = { ...@@ -2305,8 +2549,8 @@ static struct clk_regmap gxbb_gen_clk_sel = {
* vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
*/ */
.parent_names = gen_clk_parent_names, .parent_data = gen_clk_parent_data,
.num_parents = ARRAY_SIZE(gen_clk_parent_names), .num_parents = ARRAY_SIZE(gen_clk_parent_data),
}, },
}; };
...@@ -2319,7 +2563,9 @@ static struct clk_regmap gxbb_gen_clk_div = { ...@@ -2319,7 +2563,9 @@ static struct clk_regmap gxbb_gen_clk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gen_clk_div", .name = "gen_clk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "gen_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_gen_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2333,12 +2579,17 @@ static struct clk_regmap gxbb_gen_clk = { ...@@ -2333,12 +2579,17 @@ static struct clk_regmap gxbb_gen_clk = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gen_clk", .name = "gen_clk",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "gen_clk_div" }, .parent_hws = (const struct clk_hw *[]) {
&gxbb_gen_clk_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
#define MESON_GATE(_name, _reg, _bit) \
MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
/* Everything Else (EE) domain gates */ /* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
......
drivers/clk/meson/meson-aoclk.c
View file @ b69337d3
...@@ -17,8 +17,6 @@ ...@@ -17,8 +17,6 @@
#include <linux/slab.h> #include <linux/slab.h>
#include "meson-aoclk.h" #include "meson-aoclk.h"
#include "clk-input.h"
static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev, static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
unsigned long id) unsigned long id)
{ {
...@@ -33,37 +31,6 @@ static const struct reset_control_ops meson_aoclk_reset_ops = { ...@@ -33,37 +31,6 @@ static const struct reset_control_ops meson_aoclk_reset_ops = {
.reset = meson_aoclk_do_reset, .reset = meson_aoclk_do_reset,
}; };
static int meson_aoclkc_register_inputs(struct device *dev,
struct meson_aoclk_data *data)
{
struct clk_hw *hw;
char *str;
int i;
for (i = 0; i < data->num_inputs; i++) {
const struct meson_aoclk_input *in = &data->inputs[i];
str = kasprintf(GFP_KERNEL, "%s%s", data->input_prefix,
in->name);
if (!str)
return -ENOMEM;
hw = meson_clk_hw_register_input(dev, in->name, str, 0);
kfree(str);
if (IS_ERR(hw)) {
if (!in->required && PTR_ERR(hw) == -ENOENT)
continue;
else if (PTR_ERR(hw) != -EPROBE_DEFER)
dev_err(dev, "failed to register input %s\n",
in->name);
return PTR_ERR(hw);
}
}
return 0;
}
int meson_aoclkc_probe(struct platform_device *pdev) int meson_aoclkc_probe(struct platform_device *pdev)
{ {
struct meson_aoclk_reset_controller *rstc; struct meson_aoclk_reset_controller *rstc;
...@@ -86,10 +53,6 @@ int meson_aoclkc_probe(struct platform_device *pdev) ...@@ -86,10 +53,6 @@ int meson_aoclkc_probe(struct platform_device *pdev)
return PTR_ERR(regmap); return PTR_ERR(regmap);
} }
ret = meson_aoclkc_register_inputs(dev, data);
if (ret)
return ret;
/* Reset Controller */ /* Reset Controller */
rstc->data = data; rstc->data = data;
rstc->regmap = regmap; rstc->regmap = regmap;
......
drivers/clk/meson/meson-aoclk.h
View file @ b69337d3
...@@ -18,20 +18,12 @@ ...@@ -18,20 +18,12 @@
#include "clk-regmap.h" #include "clk-regmap.h"
struct meson_aoclk_input {
const char *name;
bool required;
};
struct meson_aoclk_data { struct meson_aoclk_data {
const unsigned int reset_reg; const unsigned int reset_reg;
const int num_reset; const int num_reset;
const unsigned int *reset; const unsigned int *reset;
const int num_clks; const int num_clks;
struct clk_regmap **clks; struct clk_regmap **clks;
const int num_inputs;
const struct meson_aoclk_input *inputs;
const char *input_prefix;
const struct clk_hw_onecell_data *hw_data; const struct clk_hw_onecell_data *hw_data;
}; };
......
drivers/clk/meson/meson-eeclk.c
View file @ b69337d3
...@@ -10,7 +10,6 @@ ...@@ -10,7 +10,6 @@
#include <linux/mfd/syscon.h> #include <linux/mfd/syscon.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include "clk-input.h"
#include "clk-regmap.h" #include "clk-regmap.h"
#include "meson-eeclk.h" #include "meson-eeclk.h"
...@@ -18,7 +17,6 @@ int meson_eeclkc_probe(struct platform_device *pdev) ...@@ -18,7 +17,6 @@ int meson_eeclkc_probe(struct platform_device *pdev)
{ {
const struct meson_eeclkc_data *data; const struct meson_eeclkc_data *data;
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
struct clk_hw *input;
struct regmap *map; struct regmap *map;
int ret, i; int ret, i;
...@@ -37,14 +35,6 @@ int meson_eeclkc_probe(struct platform_device *pdev) ...@@ -37,14 +35,6 @@ int meson_eeclkc_probe(struct platform_device *pdev)
if (data->init_count) if (data->init_count)
regmap_multi_reg_write(map, data->init_regs, data->init_count); regmap_multi_reg_write(map, data->init_regs, data->init_count);
input = meson_clk_hw_register_input(dev, "xtal", IN_PREFIX "xtal", 0);
if (IS_ERR(input)) {
ret = PTR_ERR(input);
if (ret != -EPROBE_DEFER)
dev_err(dev, "failed to get input clock");
return ret;
}
/* Populate regmap for the regmap backed clocks */ /* Populate regmap for the regmap backed clocks */
for (i = 0; i < data->regmap_clk_num; i++) for (i = 0; i < data->regmap_clk_num; i++)
data->regmap_clks[i]->map = map; data->regmap_clks[i]->map = map;
......
drivers/clk/meson/meson-eeclk.h
View file @ b69337d3
...@@ -10,8 +10,6 @@ ...@@ -10,8 +10,6 @@
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include "clk-regmap.h" #include "clk-regmap.h"
#define IN_PREFIX "ee-in-"
struct platform_device; struct platform_device;
struct meson_eeclkc_data { struct meson_eeclkc_data {
......
drivers/clk/meson/meson8b.c
View file @ b69337d3
...@@ -97,7 +97,9 @@ static struct clk_regmap meson8b_fixed_pll_dco = { ...@@ -97,7 +97,9 @@ static struct clk_regmap meson8b_fixed_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fixed_pll_dco", .name = "fixed_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_xtal.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -112,7 +114,9 @@ static struct clk_regmap meson8b_fixed_pll = { ...@@ -112,7 +114,9 @@ static struct clk_regmap meson8b_fixed_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fixed_pll", .name = "fixed_pll",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "fixed_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fixed_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* This clock won't ever change at runtime so * This clock won't ever change at runtime so
...@@ -158,7 +162,9 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { ...@@ -158,7 +162,9 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
/* sometimes also called "HPLL" or "HPLL PLL" */ /* sometimes also called "HPLL" or "HPLL PLL" */
.name = "hdmi_pll_dco", .name = "hdmi_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_xtal.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -173,7 +179,9 @@ static struct clk_regmap meson8b_hdmi_pll_lvds_out = { ...@@ -173,7 +179,9 @@ static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_lvds_out", .name = "hdmi_pll_lvds_out",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_hdmi_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -189,7 +197,9 @@ static struct clk_regmap meson8b_hdmi_pll_hdmi_out = { ...@@ -189,7 +197,9 @@ static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_hdmi_out", .name = "hdmi_pll_hdmi_out",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_hdmi_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -227,7 +237,9 @@ static struct clk_regmap meson8b_sys_pll_dco = { ...@@ -227,7 +237,9 @@ static struct clk_regmap meson8b_sys_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys_pll_dco", .name = "sys_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_xtal.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -242,7 +254,9 @@ static struct clk_regmap meson8b_sys_pll = { ...@@ -242,7 +254,9 @@ static struct clk_regmap meson8b_sys_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys_pll", .name = "sys_pll",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "sys_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_sys_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -254,7 +268,9 @@ static struct clk_fixed_factor meson8b_fclk_div2_div = { ...@@ -254,7 +268,9 @@ static struct clk_fixed_factor meson8b_fclk_div2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div2_div", .name = "fclk_div2_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fixed_pll.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -267,7 +283,9 @@ static struct clk_regmap meson8b_fclk_div2 = { ...@@ -267,7 +283,9 @@ static struct clk_regmap meson8b_fclk_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div2", .name = "fclk_div2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div2_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fclk_div2_div.hw
},
.num_parents = 1, .num_parents = 1,
/* /*
* FIXME: Ethernet with a RGMII PHYs is not working if * FIXME: Ethernet with a RGMII PHYs is not working if
...@@ -285,7 +303,9 @@ static struct clk_fixed_factor meson8b_fclk_div3_div = { ...@@ -285,7 +303,9 @@ static struct clk_fixed_factor meson8b_fclk_div3_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div3_div", .name = "fclk_div3_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fixed_pll.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -298,7 +318,9 @@ static struct clk_regmap meson8b_fclk_div3 = { ...@@ -298,7 +318,9 @@ static struct clk_regmap meson8b_fclk_div3 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div3", .name = "fclk_div3",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div3_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fclk_div3_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -309,7 +331,9 @@ static struct clk_fixed_factor meson8b_fclk_div4_div = { ...@@ -309,7 +331,9 @@ static struct clk_fixed_factor meson8b_fclk_div4_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div4_div", .name = "fclk_div4_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fixed_pll.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -322,7 +346,9 @@ static struct clk_regmap meson8b_fclk_div4 = { ...@@ -322,7 +346,9 @@ static struct clk_regmap meson8b_fclk_div4 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div4", .name = "fclk_div4",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div4_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fclk_div4_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -333,7 +359,9 @@ static struct clk_fixed_factor meson8b_fclk_div5_div = { ...@@ -333,7 +359,9 @@ static struct clk_fixed_factor meson8b_fclk_div5_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div5_div", .name = "fclk_div5_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fixed_pll.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -346,7 +374,9 @@ static struct clk_regmap meson8b_fclk_div5 = { ...@@ -346,7 +374,9 @@ static struct clk_regmap meson8b_fclk_div5 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div5", .name = "fclk_div5",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div5_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fclk_div5_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -357,7 +387,9 @@ static struct clk_fixed_factor meson8b_fclk_div7_div = { ...@@ -357,7 +387,9 @@ static struct clk_fixed_factor meson8b_fclk_div7_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div7_div", .name = "fclk_div7_div",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fixed_pll.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -370,7 +402,9 @@ static struct clk_regmap meson8b_fclk_div7 = { ...@@ -370,7 +402,9 @@ static struct clk_regmap meson8b_fclk_div7 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fclk_div7", .name = "fclk_div7",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div7_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fclk_div7_div.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -384,7 +418,9 @@ static struct clk_regmap meson8b_mpll_prediv = { ...@@ -384,7 +418,9 @@ static struct clk_regmap meson8b_mpll_prediv = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll_prediv", .name = "mpll_prediv",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_fixed_pll.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -416,7 +452,9 @@ static struct clk_regmap meson8b_mpll0_div = { ...@@ -416,7 +452,9 @@ static struct clk_regmap meson8b_mpll0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0_div", .name = "mpll0_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -429,7 +467,9 @@ static struct clk_regmap meson8b_mpll0 = { ...@@ -429,7 +467,9 @@ static struct clk_regmap meson8b_mpll0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0", .name = "mpll0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll0_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mpll0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -457,7 +497,9 @@ static struct clk_regmap meson8b_mpll1_div = { ...@@ -457,7 +497,9 @@ static struct clk_regmap meson8b_mpll1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1_div", .name = "mpll1_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -470,7 +512,9 @@ static struct clk_regmap meson8b_mpll1 = { ...@@ -470,7 +512,9 @@ static struct clk_regmap meson8b_mpll1 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1", .name = "mpll1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll1_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mpll1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -498,7 +542,9 @@ static struct clk_regmap meson8b_mpll2_div = { ...@@ -498,7 +542,9 @@ static struct clk_regmap meson8b_mpll2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2_div", .name = "mpll2_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "mpll_prediv" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mpll_prediv.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -511,7 +557,9 @@ static struct clk_regmap meson8b_mpll2 = { ...@@ -511,7 +557,9 @@ static struct clk_regmap meson8b_mpll2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2", .name = "mpll2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll2_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mpll2_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -533,8 +581,11 @@ static struct clk_regmap meson8b_mpeg_clk_sel = { ...@@ -533,8 +581,11 @@ static struct clk_regmap meson8b_mpeg_clk_sel = {
* xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
* fclk_div4, fclk_div3, fclk_div5 * fclk_div4, fclk_div3, fclk_div5
*/ */
.parent_names = (const char *[]){ "fclk_div3", "fclk_div4", .parent_hws = (const struct clk_hw *[]) {
"fclk_div5" }, &meson8b_fclk_div3.hw,
&meson8b_fclk_div4.hw,
&meson8b_fclk_div5.hw,
},
.num_parents = 3, .num_parents = 3,
}, },
}; };
...@@ -548,7 +599,9 @@ static struct clk_regmap meson8b_mpeg_clk_div = { ...@@ -548,7 +599,9 @@ static struct clk_regmap meson8b_mpeg_clk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div", .name = "mpeg_clk_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "mpeg_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mpeg_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -561,7 +614,9 @@ static struct clk_regmap meson8b_clk81 = { ...@@ -561,7 +614,9 @@ static struct clk_regmap meson8b_clk81 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "clk81", .name = "clk81",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpeg_clk_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mpeg_clk_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_IS_CRITICAL, .flags = CLK_IS_CRITICAL,
}, },
...@@ -576,7 +631,10 @@ static struct clk_regmap meson8b_cpu_in_sel = { ...@@ -576,7 +631,10 @@ static struct clk_regmap meson8b_cpu_in_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_in_sel", .name = "cpu_in_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "xtal", "sys_pll" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_xtal.hw,
&meson8b_sys_pll.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = (CLK_SET_RATE_PARENT | .flags = (CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT), CLK_SET_RATE_NO_REPARENT),
...@@ -589,7 +647,9 @@ static struct clk_fixed_factor meson8b_cpu_in_div2 = { ...@@ -589,7 +647,9 @@ static struct clk_fixed_factor meson8b_cpu_in_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_in_div2", .name = "cpu_in_div2",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_in_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cpu_in_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -601,7 +661,9 @@ static struct clk_fixed_factor meson8b_cpu_in_div3 = { ...@@ -601,7 +661,9 @@ static struct clk_fixed_factor meson8b_cpu_in_div3 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_in_div3", .name = "cpu_in_div3",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_in_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cpu_in_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -630,7 +692,9 @@ static struct clk_regmap meson8b_cpu_scale_div = { ...@@ -630,7 +692,9 @@ static struct clk_regmap meson8b_cpu_scale_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_scale_div", .name = "cpu_scale_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "cpu_in_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cpu_in_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -649,13 +713,15 @@ static struct clk_regmap meson8b_cpu_scale_out_sel = { ...@@ -649,13 +713,15 @@ static struct clk_regmap meson8b_cpu_scale_out_sel = {
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
/* /*
* NOTE: We are skipping the parent with value 0x2 (which is * NOTE: We are skipping the parent with value 0x2 (which is
* "cpu_in_div3") because it results in a duty cycle of 33% * meson8b_cpu_in_div3) because it results in a duty cycle of
* which makes the system unstable and can result in a lockup * 33% which makes the system unstable and can result in a
* of the whole system. * lockup of the whole system.
*/ */
.parent_names = (const char *[]) { "cpu_in_sel", .parent_hws = (const struct clk_hw *[]) {
"cpu_in_div2", &meson8b_cpu_in_sel.hw,
"cpu_scale_div" }, &meson8b_cpu_in_div2.hw,
&meson8b_cpu_scale_div.hw,
},
.num_parents = 3, .num_parents = 3,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -670,8 +736,10 @@ static struct clk_regmap meson8b_cpu_clk = { ...@@ -670,8 +736,10 @@ static struct clk_regmap meson8b_cpu_clk = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk", .name = "cpu_clk",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "xtal", .parent_hws = (const struct clk_hw *[]) {
"cpu_scale_out_sel" }, &meson8b_xtal.hw,
&meson8b_cpu_scale_out_sel.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = (CLK_SET_RATE_PARENT | .flags = (CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_NO_REPARENT |
...@@ -690,8 +758,13 @@ static struct clk_regmap meson8b_nand_clk_sel = { ...@@ -690,8 +758,13 @@ static struct clk_regmap meson8b_nand_clk_sel = {
.name = "nand_clk_sel", .name = "nand_clk_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
/* FIXME all other parents are unknown: */ /* FIXME all other parents are unknown: */
.parent_names = (const char *[]){ "fclk_div4", "fclk_div3", .parent_hws = (const struct clk_hw *[]) {
"fclk_div5", "fclk_div7", "xtal" }, &meson8b_fclk_div4.hw,
&meson8b_fclk_div3.hw,
&meson8b_fclk_div5.hw,
&meson8b_fclk_div7.hw,
&meson8b_xtal.hw,
},
.num_parents = 5, .num_parents = 5,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -707,7 +780,9 @@ static struct clk_regmap meson8b_nand_clk_div = { ...@@ -707,7 +780,9 @@ static struct clk_regmap meson8b_nand_clk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "nand_clk_div", .name = "nand_clk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "nand_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_nand_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -721,7 +796,9 @@ static struct clk_regmap meson8b_nand_clk_gate = { ...@@ -721,7 +796,9 @@ static struct clk_regmap meson8b_nand_clk_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "nand_clk_gate", .name = "nand_clk_gate",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "nand_clk_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_nand_clk_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -733,7 +810,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div2 = { ...@@ -733,7 +810,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_div2", .name = "cpu_clk_div2",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cpu_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -744,7 +823,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div3 = { ...@@ -744,7 +823,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_div3", .name = "cpu_clk_div3",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cpu_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -755,7 +836,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div4 = { ...@@ -755,7 +836,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_div4", .name = "cpu_clk_div4",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cpu_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -766,7 +849,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div5 = { ...@@ -766,7 +849,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_div5", .name = "cpu_clk_div5",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cpu_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -777,7 +862,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div6 = { ...@@ -777,7 +862,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_div6", .name = "cpu_clk_div6",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cpu_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -788,7 +875,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div7 = { ...@@ -788,7 +875,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_div7", .name = "cpu_clk_div7",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cpu_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -799,7 +888,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div8 = { ...@@ -799,7 +888,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cpu_clk_div8", .name = "cpu_clk_div8",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_clk" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cpu_clk.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -815,13 +906,15 @@ static struct clk_regmap meson8b_apb_clk_sel = { ...@@ -815,13 +906,15 @@ static struct clk_regmap meson8b_apb_clk_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "apb_clk_sel", .name = "apb_clk_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpu_clk_div2", .parent_hws = (const struct clk_hw *[]) {
"cpu_clk_div3", &meson8b_cpu_clk_div2.hw,
"cpu_clk_div4", &meson8b_cpu_clk_div3.hw,
"cpu_clk_div5", &meson8b_cpu_clk_div4.hw,
"cpu_clk_div6", &meson8b_cpu_clk_div5.hw,
"cpu_clk_div7", &meson8b_cpu_clk_div6.hw,
"cpu_clk_div8", }, &meson8b_cpu_clk_div7.hw,
&meson8b_cpu_clk_div8.hw,
},
.num_parents = 7, .num_parents = 7,
}, },
}; };
...@@ -835,7 +928,9 @@ static struct clk_regmap meson8b_apb_clk_gate = { ...@@ -835,7 +928,9 @@ static struct clk_regmap meson8b_apb_clk_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "apb_clk_dis", .name = "apb_clk_dis",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "apb_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_apb_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -850,13 +945,15 @@ static struct clk_regmap meson8b_periph_clk_sel = { ...@@ -850,13 +945,15 @@ static struct clk_regmap meson8b_periph_clk_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "periph_clk_sel", .name = "periph_clk_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpu_clk_div2", .parent_hws = (const struct clk_hw *[]) {
"cpu_clk_div3", &meson8b_cpu_clk_div2.hw,
"cpu_clk_div4", &meson8b_cpu_clk_div3.hw,
"cpu_clk_div5", &meson8b_cpu_clk_div4.hw,
"cpu_clk_div6", &meson8b_cpu_clk_div5.hw,
"cpu_clk_div7", &meson8b_cpu_clk_div6.hw,
"cpu_clk_div8", }, &meson8b_cpu_clk_div7.hw,
&meson8b_cpu_clk_div8.hw,
},
.num_parents = 7, .num_parents = 7,
}, },
}; };
...@@ -870,7 +967,9 @@ static struct clk_regmap meson8b_periph_clk_gate = { ...@@ -870,7 +967,9 @@ static struct clk_regmap meson8b_periph_clk_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "periph_clk_dis", .name = "periph_clk_dis",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "periph_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_periph_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -887,13 +986,15 @@ static struct clk_regmap meson8b_axi_clk_sel = { ...@@ -887,13 +986,15 @@ static struct clk_regmap meson8b_axi_clk_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axi_clk_sel", .name = "axi_clk_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpu_clk_div2", .parent_hws = (const struct clk_hw *[]) {
"cpu_clk_div3", &meson8b_cpu_clk_div2.hw,
"cpu_clk_div4", &meson8b_cpu_clk_div3.hw,
"cpu_clk_div5", &meson8b_cpu_clk_div4.hw,
"cpu_clk_div6", &meson8b_cpu_clk_div5.hw,
"cpu_clk_div7", &meson8b_cpu_clk_div6.hw,
"cpu_clk_div8", }, &meson8b_cpu_clk_div7.hw,
&meson8b_cpu_clk_div8.hw,
},
.num_parents = 7, .num_parents = 7,
}, },
}; };
...@@ -907,7 +1008,9 @@ static struct clk_regmap meson8b_axi_clk_gate = { ...@@ -907,7 +1008,9 @@ static struct clk_regmap meson8b_axi_clk_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "axi_clk_dis", .name = "axi_clk_dis",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "axi_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_axi_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -922,13 +1025,15 @@ static struct clk_regmap meson8b_l2_dram_clk_sel = { ...@@ -922,13 +1025,15 @@ static struct clk_regmap meson8b_l2_dram_clk_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "l2_dram_clk_sel", .name = "l2_dram_clk_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpu_clk_div2", .parent_hws = (const struct clk_hw *[]) {
"cpu_clk_div3", &meson8b_cpu_clk_div2.hw,
"cpu_clk_div4", &meson8b_cpu_clk_div3.hw,
"cpu_clk_div5", &meson8b_cpu_clk_div4.hw,
"cpu_clk_div6", &meson8b_cpu_clk_div5.hw,
"cpu_clk_div7", &meson8b_cpu_clk_div6.hw,
"cpu_clk_div8", }, &meson8b_cpu_clk_div7.hw,
&meson8b_cpu_clk_div8.hw,
},
.num_parents = 7, .num_parents = 7,
}, },
}; };
...@@ -942,7 +1047,9 @@ static struct clk_regmap meson8b_l2_dram_clk_gate = { ...@@ -942,7 +1047,9 @@ static struct clk_regmap meson8b_l2_dram_clk_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "l2_dram_clk_dis", .name = "l2_dram_clk_dis",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "l2_dram_clk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_l2_dram_clk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -963,7 +1070,9 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { ...@@ -963,7 +1070,9 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
* Meson8b: hdmi_pll_dco * Meson8b: hdmi_pll_dco
* Meson8m2: vid2_pll * Meson8m2: vid2_pll
*/ */
.parent_names = (const char *[]){ "hdmi_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_hdmi_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -977,7 +1086,9 @@ static struct clk_regmap meson8b_vid_pll_in_en = { ...@@ -977,7 +1086,9 @@ static struct clk_regmap meson8b_vid_pll_in_en = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vid_pll_in_en", .name = "vid_pll_in_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vid_pll_in_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vid_pll_in_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -992,7 +1103,9 @@ static struct clk_regmap meson8b_vid_pll_pre_div = { ...@@ -992,7 +1103,9 @@ static struct clk_regmap meson8b_vid_pll_pre_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vid_pll_pre_div", .name = "vid_pll_pre_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "vid_pll_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vid_pll_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1007,7 +1120,9 @@ static struct clk_regmap meson8b_vid_pll_post_div = { ...@@ -1007,7 +1120,9 @@ static struct clk_regmap meson8b_vid_pll_post_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vid_pll_post_div", .name = "vid_pll_post_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "vid_pll_pre_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vid_pll_pre_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1023,8 +1138,10 @@ static struct clk_regmap meson8b_vid_pll = { ...@@ -1023,8 +1138,10 @@ static struct clk_regmap meson8b_vid_pll = {
.name = "vid_pll", .name = "vid_pll",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
/* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */ /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
.parent_names = (const char *[]){ "vid_pll_pre_div", .parent_hws = (const struct clk_hw *[]) {
"vid_pll_post_div" }, &meson8b_vid_pll_pre_div.hw,
&meson8b_vid_pll_post_div.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1039,15 +1156,22 @@ static struct clk_regmap meson8b_vid_pll_final_div = { ...@@ -1039,15 +1156,22 @@ static struct clk_regmap meson8b_vid_pll_final_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vid_pll_final_div", .name = "vid_pll_final_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "vid_pll" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vid_pll.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
static const char * const meson8b_vclk_mux_parents[] = { static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
"vid_pll_final_div", "fclk_div4", "fclk_div3", "fclk_div5", &meson8b_vid_pll_final_div.hw,
"vid_pll_final_div", "fclk_div7", "mpll1" &meson8b_fclk_div4.hw,
&meson8b_fclk_div3.hw,
&meson8b_fclk_div5.hw,
&meson8b_vid_pll_final_div.hw,
&meson8b_fclk_div7.hw,
&meson8b_mpll1.hw,
}; };
static struct clk_regmap meson8b_vclk_in_sel = { static struct clk_regmap meson8b_vclk_in_sel = {
...@@ -1059,8 +1183,8 @@ static struct clk_regmap meson8b_vclk_in_sel = { ...@@ -1059,8 +1183,8 @@ static struct clk_regmap meson8b_vclk_in_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_in_sel", .name = "vclk_in_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = meson8b_vclk_mux_parents, .parent_hws = meson8b_vclk_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents), .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1073,7 +1197,9 @@ static struct clk_regmap meson8b_vclk_in_en = { ...@@ -1073,7 +1197,9 @@ static struct clk_regmap meson8b_vclk_in_en = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_in_en", .name = "vclk_in_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk_in_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_in_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1087,7 +1213,9 @@ static struct clk_regmap meson8b_vclk_div1_gate = { ...@@ -1087,7 +1213,9 @@ static struct clk_regmap meson8b_vclk_div1_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div1_en", .name = "vclk_div1_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1099,7 +1227,9 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = { ...@@ -1099,7 +1227,9 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div2", .name = "vclk_div2",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
} }
...@@ -1113,7 +1243,9 @@ static struct clk_regmap meson8b_vclk_div2_div_gate = { ...@@ -1113,7 +1243,9 @@ static struct clk_regmap meson8b_vclk_div2_div_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div2_en", .name = "vclk_div2_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk_div2" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_div2_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1125,7 +1257,9 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = { ...@@ -1125,7 +1257,9 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div4", .name = "vclk_div4",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
} }
...@@ -1139,7 +1273,9 @@ static struct clk_regmap meson8b_vclk_div4_div_gate = { ...@@ -1139,7 +1273,9 @@ static struct clk_regmap meson8b_vclk_div4_div_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div4_en", .name = "vclk_div4_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk_div4" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_div4_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1151,7 +1287,9 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = { ...@@ -1151,7 +1287,9 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div6", .name = "vclk_div6",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
} }
...@@ -1165,7 +1303,9 @@ static struct clk_regmap meson8b_vclk_div6_div_gate = { ...@@ -1165,7 +1303,9 @@ static struct clk_regmap meson8b_vclk_div6_div_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div6_en", .name = "vclk_div6_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk_div6" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_div6_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1177,7 +1317,9 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = { ...@@ -1177,7 +1317,9 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div12", .name = "vclk_div12",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
} }
...@@ -1191,7 +1333,9 @@ static struct clk_regmap meson8b_vclk_div12_div_gate = { ...@@ -1191,7 +1333,9 @@ static struct clk_regmap meson8b_vclk_div12_div_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk_div12_en", .name = "vclk_div12_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk_div12" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_div12_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1206,8 +1350,8 @@ static struct clk_regmap meson8b_vclk2_in_sel = { ...@@ -1206,8 +1350,8 @@ static struct clk_regmap meson8b_vclk2_in_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_in_sel", .name = "vclk2_in_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = meson8b_vclk_mux_parents, .parent_hws = meson8b_vclk_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents), .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1220,7 +1364,9 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = { ...@@ -1220,7 +1364,9 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_in_en", .name = "vclk2_in_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk2_in_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_in_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1234,7 +1380,9 @@ static struct clk_regmap meson8b_vclk2_div1_gate = { ...@@ -1234,7 +1380,9 @@ static struct clk_regmap meson8b_vclk2_div1_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div1_en", .name = "vclk2_div1_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk2_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_clk_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1246,7 +1394,9 @@ static struct clk_fixed_factor meson8b_vclk2_div2_div = { ...@@ -1246,7 +1394,9 @@ static struct clk_fixed_factor meson8b_vclk2_div2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div2", .name = "vclk2_div2",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_clk_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
} }
...@@ -1260,7 +1410,9 @@ static struct clk_regmap meson8b_vclk2_div2_div_gate = { ...@@ -1260,7 +1410,9 @@ static struct clk_regmap meson8b_vclk2_div2_div_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div2_en", .name = "vclk2_div2_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk2_div2" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_div2_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1272,7 +1424,9 @@ static struct clk_fixed_factor meson8b_vclk2_div4_div = { ...@@ -1272,7 +1424,9 @@ static struct clk_fixed_factor meson8b_vclk2_div4_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div4", .name = "vclk2_div4",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_clk_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
} }
...@@ -1286,7 +1440,9 @@ static struct clk_regmap meson8b_vclk2_div4_div_gate = { ...@@ -1286,7 +1440,9 @@ static struct clk_regmap meson8b_vclk2_div4_div_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div4_en", .name = "vclk2_div4_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk2_div4" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_div4_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1298,7 +1454,9 @@ static struct clk_fixed_factor meson8b_vclk2_div6_div = { ...@@ -1298,7 +1454,9 @@ static struct clk_fixed_factor meson8b_vclk2_div6_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div6", .name = "vclk2_div6",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_clk_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
} }
...@@ -1312,7 +1470,9 @@ static struct clk_regmap meson8b_vclk2_div6_div_gate = { ...@@ -1312,7 +1470,9 @@ static struct clk_regmap meson8b_vclk2_div6_div_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div6_en", .name = "vclk2_div6_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk2_div6" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_div6_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1324,7 +1484,9 @@ static struct clk_fixed_factor meson8b_vclk2_div12_div = { ...@@ -1324,7 +1484,9 @@ static struct clk_fixed_factor meson8b_vclk2_div12_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div12", .name = "vclk2_div12",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "vclk2_in_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_clk_in_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
} }
...@@ -1338,15 +1500,20 @@ static struct clk_regmap meson8b_vclk2_div12_div_gate = { ...@@ -1338,15 +1500,20 @@ static struct clk_regmap meson8b_vclk2_div12_div_gate = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vclk2_div12_en", .name = "vclk2_div12_en",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "vclk2_div12" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_div12_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
static const char * const meson8b_vclk_enc_mux_parents[] = { static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
"vclk_div1_en", "vclk_div2_en", "vclk_div4_en", "vclk_div6_en", &meson8b_vclk_div1_gate.hw,
"vclk_div12_en", &meson8b_vclk_div2_div_gate.hw,
&meson8b_vclk_div4_div_gate.hw,
&meson8b_vclk_div6_div_gate.hw,
&meson8b_vclk_div12_div_gate.hw,
}; };
static struct clk_regmap meson8b_cts_enct_sel = { static struct clk_regmap meson8b_cts_enct_sel = {
...@@ -1358,8 +1525,8 @@ static struct clk_regmap meson8b_cts_enct_sel = { ...@@ -1358,8 +1525,8 @@ static struct clk_regmap meson8b_cts_enct_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_enct_sel", .name = "cts_enct_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = meson8b_vclk_enc_mux_parents, .parent_hws = meson8b_vclk_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1372,7 +1539,9 @@ static struct clk_regmap meson8b_cts_enct = { ...@@ -1372,7 +1539,9 @@ static struct clk_regmap meson8b_cts_enct = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_enct", .name = "cts_enct",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cts_enct_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_enct_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1387,8 +1556,8 @@ static struct clk_regmap meson8b_cts_encp_sel = { ...@@ -1387,8 +1556,8 @@ static struct clk_regmap meson8b_cts_encp_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_encp_sel", .name = "cts_encp_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = meson8b_vclk_enc_mux_parents, .parent_hws = meson8b_vclk_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1401,7 +1570,9 @@ static struct clk_regmap meson8b_cts_encp = { ...@@ -1401,7 +1570,9 @@ static struct clk_regmap meson8b_cts_encp = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_encp", .name = "cts_encp",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cts_encp_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_encp_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1416,8 +1587,8 @@ static struct clk_regmap meson8b_cts_enci_sel = { ...@@ -1416,8 +1587,8 @@ static struct clk_regmap meson8b_cts_enci_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_enci_sel", .name = "cts_enci_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = meson8b_vclk_enc_mux_parents, .parent_hws = meson8b_vclk_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1430,7 +1601,9 @@ static struct clk_regmap meson8b_cts_enci = { ...@@ -1430,7 +1601,9 @@ static struct clk_regmap meson8b_cts_enci = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_enci", .name = "cts_enci",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cts_enci_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_enci_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1445,8 +1618,8 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = { ...@@ -1445,8 +1618,8 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_tx_pixel_sel", .name = "hdmi_tx_pixel_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = meson8b_vclk_enc_mux_parents, .parent_hws = meson8b_vclk_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1459,15 +1632,20 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = { ...@@ -1459,15 +1632,20 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_tx_pixel", .name = "hdmi_tx_pixel",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "hdmi_tx_pixel_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_hdmi_tx_pixel_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
static const char * const meson8b_vclk2_enc_mux_parents[] = { static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
"vclk2_div1_en", "vclk2_div2_en", "vclk2_div4_en", "vclk2_div6_en", &meson8b_vclk2_div1_gate.hw,
"vclk2_div12_en", &meson8b_vclk2_div2_div_gate.hw,
&meson8b_vclk2_div4_div_gate.hw,
&meson8b_vclk2_div6_div_gate.hw,
&meson8b_vclk2_div12_div_gate.hw,
}; };
static struct clk_regmap meson8b_cts_encl_sel = { static struct clk_regmap meson8b_cts_encl_sel = {
...@@ -1479,8 +1657,8 @@ static struct clk_regmap meson8b_cts_encl_sel = { ...@@ -1479,8 +1657,8 @@ static struct clk_regmap meson8b_cts_encl_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_encl_sel", .name = "cts_encl_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = meson8b_vclk2_enc_mux_parents, .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents), .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1493,7 +1671,9 @@ static struct clk_regmap meson8b_cts_encl = { ...@@ -1493,7 +1671,9 @@ static struct clk_regmap meson8b_cts_encl = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_encl", .name = "cts_encl",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cts_encl_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_encl_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1508,8 +1688,8 @@ static struct clk_regmap meson8b_cts_vdac0_sel = { ...@@ -1508,8 +1688,8 @@ static struct clk_regmap meson8b_cts_vdac0_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_vdac0_sel", .name = "cts_vdac0_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
.parent_names = meson8b_vclk2_enc_mux_parents, .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents), .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1522,7 +1702,9 @@ static struct clk_regmap meson8b_cts_vdac0 = { ...@@ -1522,7 +1702,9 @@ static struct clk_regmap meson8b_cts_vdac0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_vdac0", .name = "cts_vdac0",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cts_vdac0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_vdac0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1539,7 +1721,9 @@ static struct clk_regmap meson8b_hdmi_sys_sel = { ...@@ -1539,7 +1721,9 @@ static struct clk_regmap meson8b_hdmi_sys_sel = {
.name = "hdmi_sys_sel", .name = "hdmi_sys_sel",
.ops = &clk_regmap_mux_ro_ops, .ops = &clk_regmap_mux_ro_ops,
/* FIXME: all other parents are unknown */ /* FIXME: all other parents are unknown */
.parent_names = (const char *[]){ "xtal" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_xtal.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
...@@ -1554,7 +1738,9 @@ static struct clk_regmap meson8b_hdmi_sys_div = { ...@@ -1554,7 +1738,9 @@ static struct clk_regmap meson8b_hdmi_sys_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_sys_div", .name = "hdmi_sys_div",
.ops = &clk_regmap_divider_ro_ops, .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "hdmi_sys_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_hdmi_sys_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1568,7 +1754,9 @@ static struct clk_regmap meson8b_hdmi_sys = { ...@@ -1568,7 +1754,9 @@ static struct clk_regmap meson8b_hdmi_sys = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "hdmi_sys", .name = "hdmi_sys",
.ops = &clk_regmap_gate_ro_ops, .ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "hdmi_sys_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_hdmi_sys_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1579,9 +1767,14 @@ static struct clk_regmap meson8b_hdmi_sys = { ...@@ -1579,9 +1767,14 @@ static struct clk_regmap meson8b_hdmi_sys = {
* muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
* has mali_0 and no glitch-free mux. * has mali_0 and no glitch-free mux.
*/ */
static const char * const meson8b_mali_0_1_parent_names[] = { static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = {
"xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3", &meson8b_xtal.hw,
"fclk_div5" &meson8b_mpll2.hw,
&meson8b_mpll1.hw,
&meson8b_fclk_div7.hw,
&meson8b_fclk_div4.hw,
&meson8b_fclk_div3.hw,
&meson8b_fclk_div5.hw,
}; };
static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 }; static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
...@@ -1596,8 +1789,8 @@ static struct clk_regmap meson8b_mali_0_sel = { ...@@ -1596,8 +1789,8 @@ static struct clk_regmap meson8b_mali_0_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_0_sel", .name = "mali_0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = meson8b_mali_0_1_parent_names, .parent_hws = meson8b_mali_0_1_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names), .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
/* /*
* Don't propagate rate changes up because the only changeable * Don't propagate rate changes up because the only changeable
* parents are mpll1 and mpll2 but we need those for audio and * parents are mpll1 and mpll2 but we need those for audio and
...@@ -1617,7 +1810,9 @@ static struct clk_regmap meson8b_mali_0_div = { ...@@ -1617,7 +1810,9 @@ static struct clk_regmap meson8b_mali_0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_0_div", .name = "mali_0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "mali_0_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mali_0_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1631,7 +1826,9 @@ static struct clk_regmap meson8b_mali_0 = { ...@@ -1631,7 +1826,9 @@ static struct clk_regmap meson8b_mali_0 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_0", .name = "mali_0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mali_0_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mali_0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1647,8 +1844,8 @@ static struct clk_regmap meson8b_mali_1_sel = { ...@@ -1647,8 +1844,8 @@ static struct clk_regmap meson8b_mali_1_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_1_sel", .name = "mali_1_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = meson8b_mali_0_1_parent_names, .parent_hws = meson8b_mali_0_1_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names), .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
/* /*
* Don't propagate rate changes up because the only changeable * Don't propagate rate changes up because the only changeable
* parents are mpll1 and mpll2 but we need those for audio and * parents are mpll1 and mpll2 but we need those for audio and
...@@ -1668,7 +1865,9 @@ static struct clk_regmap meson8b_mali_1_div = { ...@@ -1668,7 +1865,9 @@ static struct clk_regmap meson8b_mali_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_1_div", .name = "mali_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "mali_1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mali_1_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1682,7 +1881,9 @@ static struct clk_regmap meson8b_mali_1 = { ...@@ -1682,7 +1881,9 @@ static struct clk_regmap meson8b_mali_1 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali_1", .name = "mali_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mali_1_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mali_1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1697,7 +1898,10 @@ static struct clk_regmap meson8b_mali = { ...@@ -1697,7 +1898,10 @@ static struct clk_regmap meson8b_mali = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mali", .name = "mali",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "mali_0", "mali_1" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_mali_0.hw,
&meson8b_mali_1.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1740,7 +1944,9 @@ static struct clk_regmap meson8m2_gp_pll_dco = { ...@@ -1740,7 +1944,9 @@ static struct clk_regmap meson8m2_gp_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp_pll_dco", .name = "gp_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_xtal.hw
},
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -1755,18 +1961,26 @@ static struct clk_regmap meson8m2_gp_pll = { ...@@ -1755,18 +1961,26 @@ static struct clk_regmap meson8m2_gp_pll = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp_pll", .name = "gp_pll",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "gp_pll_dco" }, .parent_hws = (const struct clk_hw *[]) {
&meson8m2_gp_pll_dco.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
static const char * const meson8b_vpu_0_1_parent_names[] = { static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" &meson8b_fclk_div4.hw,
&meson8b_fclk_div3.hw,
&meson8b_fclk_div5.hw,
&meson8b_fclk_div7.hw,
}; };
static const char * const mmeson8m2_vpu_0_1_parent_names[] = { static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "gp_pll" &meson8b_fclk_div4.hw,
&meson8b_fclk_div3.hw,
&meson8b_fclk_div5.hw,
&meson8m2_gp_pll.hw,
}; };
static struct clk_regmap meson8b_vpu_0_sel = { static struct clk_regmap meson8b_vpu_0_sel = {
...@@ -1778,8 +1992,8 @@ static struct clk_regmap meson8b_vpu_0_sel = { ...@@ -1778,8 +1992,8 @@ static struct clk_regmap meson8b_vpu_0_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_0_sel", .name = "vpu_0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = meson8b_vpu_0_1_parent_names, .parent_hws = meson8b_vpu_0_1_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names), .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1793,8 +2007,8 @@ static struct clk_regmap meson8m2_vpu_0_sel = { ...@@ -1793,8 +2007,8 @@ static struct clk_regmap meson8m2_vpu_0_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_0_sel", .name = "vpu_0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = mmeson8m2_vpu_0_1_parent_names, .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names), .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1808,7 +2022,17 @@ static struct clk_regmap meson8b_vpu_0_div = { ...@@ -1808,7 +2022,17 @@ static struct clk_regmap meson8b_vpu_0_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_0_div", .name = "vpu_0_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vpu_0_sel" }, .parent_data = &(const struct clk_parent_data) {
/*
* Note:
* meson8b and meson8m2 have different vpu_0_sels (with
* different struct clk_hw). We fallback to the global
* naming string mechanism so vpu_0_div picks up the
* appropriate one.
*/
.name = "vpu_0_sel",
.index = -1,
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1822,7 +2046,9 @@ static struct clk_regmap meson8b_vpu_0 = { ...@@ -1822,7 +2046,9 @@ static struct clk_regmap meson8b_vpu_0 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vpu_0", .name = "vpu_0",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vpu_0_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vpu_0_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1837,8 +2063,8 @@ static struct clk_regmap meson8b_vpu_1_sel = { ...@@ -1837,8 +2063,8 @@ static struct clk_regmap meson8b_vpu_1_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_1_sel", .name = "vpu_1_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = meson8b_vpu_0_1_parent_names, .parent_hws = meson8b_vpu_0_1_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names), .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1852,8 +2078,8 @@ static struct clk_regmap meson8m2_vpu_1_sel = { ...@@ -1852,8 +2078,8 @@ static struct clk_regmap meson8m2_vpu_1_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_1_sel", .name = "vpu_1_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = mmeson8m2_vpu_0_1_parent_names, .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names), .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1867,7 +2093,17 @@ static struct clk_regmap meson8b_vpu_1_div = { ...@@ -1867,7 +2093,17 @@ static struct clk_regmap meson8b_vpu_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_1_div", .name = "vpu_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vpu_1_sel" }, .parent_data = &(const struct clk_parent_data) {
/*
* Note:
* meson8b and meson8m2 have different vpu_1_sels (with
* different struct clk_hw). We fallback to the global
* naming string mechanism so vpu_1_div picks up the
* appropriate one.
*/
.name = "vpu_1_sel",
.index = -1,
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1881,7 +2117,9 @@ static struct clk_regmap meson8b_vpu_1 = { ...@@ -1881,7 +2117,9 @@ static struct clk_regmap meson8b_vpu_1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vpu_1", .name = "vpu_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vpu_1_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vpu_1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1896,14 +2134,22 @@ static struct clk_regmap meson8b_vpu = { ...@@ -1896,14 +2134,22 @@ static struct clk_regmap meson8b_vpu = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu", .name = "vpu",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "vpu_0", "vpu_1" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vpu_0.hw,
&meson8b_vpu_1.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_NO_REPARENT, .flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
static const char * const meson8b_vdec_parent_names[] = { static const struct clk_hw *meson8b_vdec_parent_hws[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll1" &meson8b_fclk_div4.hw,
&meson8b_fclk_div3.hw,
&meson8b_fclk_div5.hw,
&meson8b_fclk_div7.hw,
&meson8b_mpll2.hw,
&meson8b_mpll1.hw,
}; };
static struct clk_regmap meson8b_vdec_1_sel = { static struct clk_regmap meson8b_vdec_1_sel = {
...@@ -1916,8 +2162,8 @@ static struct clk_regmap meson8b_vdec_1_sel = { ...@@ -1916,8 +2162,8 @@ static struct clk_regmap meson8b_vdec_1_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_1_sel", .name = "vdec_1_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = meson8b_vdec_parent_names, .parent_hws = meson8b_vdec_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names), .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1932,7 +2178,9 @@ static struct clk_regmap meson8b_vdec_1_1_div = { ...@@ -1932,7 +2178,9 @@ static struct clk_regmap meson8b_vdec_1_1_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_1_1_div", .name = "vdec_1_1_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_1_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1946,7 +2194,9 @@ static struct clk_regmap meson8b_vdec_1_1 = { ...@@ -1946,7 +2194,9 @@ static struct clk_regmap meson8b_vdec_1_1 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vdec_1_1", .name = "vdec_1_1",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_1_1_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_1_1_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1962,7 +2212,9 @@ static struct clk_regmap meson8b_vdec_1_2_div = { ...@@ -1962,7 +2212,9 @@ static struct clk_regmap meson8b_vdec_1_2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_1_2_div", .name = "vdec_1_2_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_1_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_1_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1976,7 +2228,9 @@ static struct clk_regmap meson8b_vdec_1_2 = { ...@@ -1976,7 +2228,9 @@ static struct clk_regmap meson8b_vdec_1_2 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vdec_1_2", .name = "vdec_1_2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_1_2_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_1_2_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1992,7 +2246,10 @@ static struct clk_regmap meson8b_vdec_1 = { ...@@ -1992,7 +2246,10 @@ static struct clk_regmap meson8b_vdec_1 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_1", .name = "vdec_1",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "vdec_1_1", "vdec_1_2" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_1_1.hw,
&meson8b_vdec_1_2.hw,
},
.num_parents = 2, .num_parents = 2,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2008,8 +2265,8 @@ static struct clk_regmap meson8b_vdec_hcodec_sel = { ...@@ -2008,8 +2265,8 @@ static struct clk_regmap meson8b_vdec_hcodec_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_hcodec_sel", .name = "vdec_hcodec_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = meson8b_vdec_parent_names, .parent_hws = meson8b_vdec_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names), .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -2024,7 +2281,9 @@ static struct clk_regmap meson8b_vdec_hcodec_div = { ...@@ -2024,7 +2281,9 @@ static struct clk_regmap meson8b_vdec_hcodec_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_hcodec_div", .name = "vdec_hcodec_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_hcodec_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_hcodec_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2038,7 +2297,9 @@ static struct clk_regmap meson8b_vdec_hcodec = { ...@@ -2038,7 +2297,9 @@ static struct clk_regmap meson8b_vdec_hcodec = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vdec_hcodec", .name = "vdec_hcodec",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_hcodec_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_hcodec_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2054,8 +2315,8 @@ static struct clk_regmap meson8b_vdec_2_sel = { ...@@ -2054,8 +2315,8 @@ static struct clk_regmap meson8b_vdec_2_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_2_sel", .name = "vdec_2_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = meson8b_vdec_parent_names, .parent_hws = meson8b_vdec_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names), .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -2070,7 +2331,9 @@ static struct clk_regmap meson8b_vdec_2_div = { ...@@ -2070,7 +2331,9 @@ static struct clk_regmap meson8b_vdec_2_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_2_div", .name = "vdec_2_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_2_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_2_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2084,7 +2347,9 @@ static struct clk_regmap meson8b_vdec_2 = { ...@@ -2084,7 +2347,9 @@ static struct clk_regmap meson8b_vdec_2 = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vdec_2", .name = "vdec_2",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_2_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_2_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2100,8 +2365,8 @@ static struct clk_regmap meson8b_vdec_hevc_sel = { ...@@ -2100,8 +2365,8 @@ static struct clk_regmap meson8b_vdec_hevc_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_hevc_sel", .name = "vdec_hevc_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = meson8b_vdec_parent_names, .parent_hws = meson8b_vdec_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names), .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -2116,7 +2381,9 @@ static struct clk_regmap meson8b_vdec_hevc_div = { ...@@ -2116,7 +2381,9 @@ static struct clk_regmap meson8b_vdec_hevc_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vdec_hevc_div", .name = "vdec_hevc_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_hevc_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_hevc_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2130,7 +2397,9 @@ static struct clk_regmap meson8b_vdec_hevc_en = { ...@@ -2130,7 +2397,9 @@ static struct clk_regmap meson8b_vdec_hevc_en = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "vdec_hevc_en", .name = "vdec_hevc_en",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_hevc_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_hevc_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2147,15 +2416,19 @@ static struct clk_regmap meson8b_vdec_hevc = { ...@@ -2147,15 +2416,19 @@ static struct clk_regmap meson8b_vdec_hevc = {
.name = "vdec_hevc", .name = "vdec_hevc",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
/* TODO: The second parent is currently unknown */ /* TODO: The second parent is currently unknown */
.parent_names = (const char *[]){ "vdec_hevc_en" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_vdec_hevc_en.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
static const char * const meson8b_cts_amclk_parent_names[] = { static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
"mpll0", "mpll1", "mpll2" &meson8b_mpll0.hw,
&meson8b_mpll1.hw,
&meson8b_mpll2.hw
}; };
static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 }; static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
...@@ -2171,8 +2444,8 @@ static struct clk_regmap meson8b_cts_amclk_sel = { ...@@ -2171,8 +2444,8 @@ static struct clk_regmap meson8b_cts_amclk_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_amclk_sel", .name = "cts_amclk_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = meson8b_cts_amclk_parent_names, .parent_hws = meson8b_cts_amclk_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_names), .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
}, },
}; };
...@@ -2186,7 +2459,9 @@ static struct clk_regmap meson8b_cts_amclk_div = { ...@@ -2186,7 +2459,9 @@ static struct clk_regmap meson8b_cts_amclk_div = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_amclk_div", .name = "cts_amclk_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "cts_amclk_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_amclk_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2200,15 +2475,19 @@ static struct clk_regmap meson8b_cts_amclk = { ...@@ -2200,15 +2475,19 @@ static struct clk_regmap meson8b_cts_amclk = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_amclk", .name = "cts_amclk",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_amclk_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_amclk_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
static const char * const meson8b_cts_mclk_i958_parent_names[] = { static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
"mpll0", "mpll1", "mpll2" &meson8b_mpll0.hw,
&meson8b_mpll1.hw,
&meson8b_mpll2.hw
}; };
static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 }; static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
...@@ -2224,8 +2503,8 @@ static struct clk_regmap meson8b_cts_mclk_i958_sel = { ...@@ -2224,8 +2503,8 @@ static struct clk_regmap meson8b_cts_mclk_i958_sel = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cts_mclk_i958_sel", .name = "cts_mclk_i958_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = meson8b_cts_mclk_i958_parent_names, .parent_hws = meson8b_cts_mclk_i958_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_names), .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
}, },
}; };
...@@ -2239,7 +2518,9 @@ static struct clk_regmap meson8b_cts_mclk_i958_div = { ...@@ -2239,7 +2518,9 @@ static struct clk_regmap meson8b_cts_mclk_i958_div = {
.hw.init = &(struct clk_init_data) { .hw.init = &(struct clk_init_data) {
.name = "cts_mclk_i958_div", .name = "cts_mclk_i958_div",
.ops = &clk_regmap_divider_ops, .ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "cts_mclk_i958_sel" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_mclk_i958_sel.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2253,7 +2534,9 @@ static struct clk_regmap meson8b_cts_mclk_i958 = { ...@@ -2253,7 +2534,9 @@ static struct clk_regmap meson8b_cts_mclk_i958 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_mclk_i958", .name = "cts_mclk_i958",
.ops = &clk_regmap_gate_ops, .ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "cts_mclk_i958_div" }, .parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_mclk_i958_div.hw
},
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -2268,8 +2551,10 @@ static struct clk_regmap meson8b_cts_i958 = { ...@@ -2268,8 +2551,10 @@ static struct clk_regmap meson8b_cts_i958 = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cts_i958", .name = "cts_i958",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cts_amclk", .parent_hws = (const struct clk_hw *[]) {
"cts_mclk_i958" }, &meson8b_cts_amclk.hw,
&meson8b_cts_mclk_i958.hw
},
.num_parents = 2, .num_parents = 2,
/* /*
* The parent is specific to origin of the audio data. Let the * The parent is specific to origin of the audio data. Let the
...@@ -2279,6 +2564,9 @@ static struct clk_regmap meson8b_cts_i958 = { ...@@ -2279,6 +2564,9 @@ static struct clk_regmap meson8b_cts_i958 = {
}, },
}; };
#define MESON_GATE(_name, _reg, _bit) \
MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
/* Everything Else (EE) domain gates */ /* Everything Else (EE) domain gates */
static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
......
include/dt-bindings/clock/g12a-clkc.h
View file @ b69337d3
...@@ -137,5 +137,6 @@ ...@@ -137,5 +137,6 @@
#define CLKID_VDEC_HEVC 207 #define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF 210 #define CLKID_VDEC_HEVCF 210
#define CLKID_TS 212 #define CLKID_TS 212
#define CLKID_CPUB_CLK 224
#endif /* __G12A_CLKC_H */ #endif /* __G12A_CLKC_H */
include/linux/clk-provider.h
View file @ b69337d3
...@@ -817,6 +817,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); ...@@ -817,6 +817,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
unsigned int index); unsigned int index);
int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
unsigned int __clk_get_enable_count(struct clk *clk); unsigned int __clk_get_enable_count(struct clk *clk);
unsigned long clk_hw_get_rate(const struct clk_hw *hw); unsigned long clk_hw_get_rate(const struct clk_hw *hw);
unsigned long __clk_get_flags(struct clk *clk); unsigned long __clk_get_flags(struct clk *clk);
......
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