Commit b6ae4055 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 perf updates from Will Deacon:
 "The main addition here is support for Broadcom's Vulcan core using the
  architected ID registers for discovering supported events.

   - Support for the PMU in Broadcom's Vulcan CPU

   - Dynamic event detection using the PMCEIDn_EL0 ID registers"

* tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: perf: don't expose CHAIN event in sysfs
  arm64/perf: Add Broadcom Vulcan PMU support
  arm64/perf: Filter common events based on PMCEIDn_EL0
  arm64/perf: Access pmu register using <read/write>_sys_reg
  arm64/perf: Define complete ARMv8 recommended implementation defined events
  arm64/perf: Changed events naming as per the ARM ARM
  arm64: dts: Add Broadcom Vulcan PMU in dts
  Documentation: arm64: pmu: Add Broadcom Vulcan PMU binding
parents be092017 4ba2578f
...@@ -22,10 +22,11 @@ Required properties: ...@@ -22,10 +22,11 @@ Required properties:
"arm,arm11mpcore-pmu" "arm,arm11mpcore-pmu"
"arm,arm1176-pmu" "arm,arm1176-pmu"
"arm,arm1136-pmu" "arm,arm1136-pmu"
"brcm,vulcan-pmu"
"cavium,thunder-pmu"
"qcom,scorpion-pmu" "qcom,scorpion-pmu"
"qcom,scorpion-mp-pmu" "qcom,scorpion-mp-pmu"
"qcom,krait-pmu" "qcom,krait-pmu"
"cavium,thunder-pmu"
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
interrupt (PPI) then 1 interrupt should be specified. interrupt (PPI) then 1 interrupt should be specified.
......
...@@ -86,7 +86,7 @@ timer { ...@@ -86,7 +86,7 @@ timer {
}; };
pmu { pmu {
compatible = "arm,armv8-pmuv3"; compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
}; };
......
This diff is collapsed.
...@@ -105,6 +105,8 @@ struct arm_pmu { ...@@ -105,6 +105,8 @@ struct arm_pmu {
struct mutex reserve_mutex; struct mutex reserve_mutex;
u64 max_period; u64 max_period;
bool secure_access; /* 32-bit ARM only */ bool secure_access; /* 32-bit ARM only */
#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
struct platform_device *plat_device; struct platform_device *plat_device;
struct pmu_hw_events __percpu *hw_events; struct pmu_hw_events __percpu *hw_events;
struct notifier_block hotplug_nb; struct notifier_block hotplug_nb;
......
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