Commit b77bd62d authored by Juerg Haefliger's avatar Juerg Haefliger Committed by Kleber Sacilotto de Souza

UBUNTU: SAUCE: x86: Move hunks and sync to upstream stable 4.9

BugLink: https://bugs.launchpad.net/bugs/1820872

Trivial changes to reduce the delta between Xenial 4.4 and upstream
stable 4.9 so that future cherry-picking results in fewer conflicts.
Signed-off-by: default avatarJuerg Haefliger <juergh@canonical.com>
Acked-by: default avatarKleber Sacilotto de Souza <kleber.souza@canonical.com>
Acked-by: default avatarStefan Bader <stefan.bader@canonical.com>
Signed-off-by: default avatarKleber Sacilotto de Souza <kleber.souza@canonical.com>
parent 0aef3d06
...@@ -202,9 +202,6 @@ enum spectre_v2_mitigation { ...@@ -202,9 +202,6 @@ enum spectre_v2_mitigation {
SPECTRE_V2_IBRS_ENHANCED, SPECTRE_V2_IBRS_ENHANCED,
}; };
/* The Intel SPEC CTRL MSR base value cache */
extern u64 x86_spec_ctrl_base;
/* The Speculative Store Bypass disable variants */ /* The Speculative Store Bypass disable variants */
enum ssb_mitigation { enum ssb_mitigation {
SPEC_STORE_BYPASS_NONE, SPEC_STORE_BYPASS_NONE,
...@@ -256,6 +253,9 @@ static inline void indirect_branch_prediction_barrier(void) ...@@ -256,6 +253,9 @@ static inline void indirect_branch_prediction_barrier(void)
X86_FEATURE_USE_IBPB); X86_FEATURE_USE_IBPB);
} }
/* The Intel SPEC CTRL MSR base value cache */
extern u64 x86_spec_ctrl_base;
/* /*
* With retpoline, we must use IBRS to restrict branch prediction * With retpoline, we must use IBRS to restrict branch prediction
* before calling into firmware. * before calling into firmware.
...@@ -265,6 +265,7 @@ static inline void indirect_branch_prediction_barrier(void) ...@@ -265,6 +265,7 @@ static inline void indirect_branch_prediction_barrier(void)
#define firmware_restrict_branch_speculation_start() \ #define firmware_restrict_branch_speculation_start() \
do { \ do { \
u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS; \ u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS; \
\
preempt_disable(); \ preempt_disable(); \
alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \ alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
X86_FEATURE_USE_IBRS_FW); \ X86_FEATURE_USE_IBRS_FW); \
......
...@@ -296,10 +296,8 @@ static int nearby_node(int apicid) ...@@ -296,10 +296,8 @@ static int nearby_node(int apicid)
static void amd_get_topology_early(struct cpuinfo_x86 *c) static void amd_get_topology_early(struct cpuinfo_x86 *c)
{ {
#ifdef CONFIG_SMP if (cpu_has(c, X86_FEATURE_TOPOEXT))
if (boot_cpu_has(X86_FEATURE_TOPOEXT))
smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0x3) + 1; smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0x3) + 1;
#endif
} }
/* /*
......
...@@ -396,7 +396,7 @@ static void __init spectre_v2_select_mitigation(void) ...@@ -396,7 +396,7 @@ static void __init spectre_v2_select_mitigation(void)
if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
retpoline_amd: retpoline_amd:
if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
pr_err("Spectre mitigation: LFENCE not serializing. Switching to generic retpoline\n"); pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
goto retpoline_generic; goto retpoline_generic;
} }
mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
...@@ -860,7 +860,6 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr ...@@ -860,7 +860,6 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr
case X86_BUG_SPECTRE_V1: case X86_BUG_SPECTRE_V1:
return sprintf(buf, "Mitigation: __user pointer sanitization\n"); return sprintf(buf, "Mitigation: __user pointer sanitization\n");
break;
case X86_BUG_SPECTRE_V2: case X86_BUG_SPECTRE_V2:
return sprintf(buf, "%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], return sprintf(buf, "%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
......
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