Commit b9f9e9b8 authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard

dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description

This commit adds necessary description and dt includes for H6 DE3 clock.
It is very similar to others, but memory region has some additional
registers not found in DE2.
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent ed443341
Allwinner Display Engine 2.0 Clock Control Binding Allwinner Display Engine 2.0/3.0 Clock Control Binding
-------------------------------------------------- ------------------------------------------------------
Required properties : Required properties :
- compatible: must contain one of the following compatibles: - compatible: must contain one of the following compatibles:
...@@ -8,6 +8,7 @@ Required properties : ...@@ -8,6 +8,7 @@ Required properties :
- "allwinner,sun8i-v3s-de2-clk" - "allwinner,sun8i-v3s-de2-clk"
- "allwinner,sun50i-a64-de2-clk" - "allwinner,sun50i-a64-de2-clk"
- "allwinner,sun50i-h5-de2-clk" - "allwinner,sun50i-h5-de2-clk"
- "allwinner,sun50i-h6-de3-clk"
- reg: Must contain the registers base address and length - reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem. - clocks: phandle to the clocks feeding the display engine subsystem.
......
...@@ -15,4 +15,7 @@ ...@@ -15,4 +15,7 @@
#define CLK_MIXER1 7 #define CLK_MIXER1 7
#define CLK_WB 8 #define CLK_WB 8
#define CLK_BUS_ROT 9
#define CLK_ROT 10
#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ #endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
...@@ -10,5 +10,6 @@ ...@@ -10,5 +10,6 @@
#define RST_MIXER0 0 #define RST_MIXER0 0
#define RST_MIXER1 1 #define RST_MIXER1 1
#define RST_WB 2 #define RST_WB 2
#define RST_ROT 3
#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */ #endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
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