Merge are.twiddle.net:/home/rth/BK/linus-2.5

into are.twiddle.net:/home/rth/BK/axp-2.5

MAINTAINERS

@@ -204,6 +204,14 @@ M:	Juergen Fischer <fischer@norbit.de>
 L:	linux-scsi@vger.kernel.org
 S:	Maintained
 
+ALPHA PORT
+P:	Richard Henderson
+M:	rth@twiddle.net
+S:	Odd Fixes for 2.4; Maintained for 2.5.
+P:	Ivan Kokshaysky
+M:	ink@jurassic.park.msu.ru
+S:	Maintained for 2.4; PCI support for 2.5.
+
 APM DRIVER
 P:	Stephen Rothwell
 M:	sfr@canb.auug.org.au

arch/alpha/kernel/Makefile

@@ -34,7 +34,7 @@ obj-y 	 += core_apecs.o core_cia.o core_irongate.o core_lca.o core_mcpcia.o \
 	    sys_alcor.o sys_cabriolet.o sys_dp264.o sys_eb64p.o sys_eiger.o \
 	    sys_jensen.o sys_miata.o sys_mikasa.o sys_nautilus.o sys_titan.o \
 	    sys_noritake.o sys_rawhide.o sys_ruffian.o sys_rx164.o \
-	    sys_sable.o sys_sio.o sys_sx164.o sys_takara.o sys_rx164.o \
+	    sys_sable.o sys_sio.o sys_sx164.o sys_takara.o \
 	    sys_wildfire.o core_wildfire.o irq_pyxis.o
 
 else

arch/alpha/kernel/err_common.c

@@ -34,12 +34,12 @@ static void el_process_subpackets(struct el_subpacket *, int);
  * Generic
  */
 void
-mchk_dump_mem(void *data, int length, char **annotation)
+mchk_dump_mem(void *data, size_t length, char **annotation)
 {
 	unsigned long *ldata = data;
-	int i;
+	size_t i;
 	
-	for(i = 0; (i * sizeof(*ldata)) < length; i++) {
+	for (i = 0; (i * sizeof(*ldata)) < length; i++) {
 		if (annotation && !annotation[i]) 
 			annotation = NULL;
 		printk("%s    %08x: %016lx    %s\n",
@@ -624,7 +624,7 @@ el_process_subpackets(struct el_subpacket *header, int packet_count)
 	subpacket = (struct el_subpacket *)
 		((unsigned long)header + header->length);
 
-	for(i = 0; subpacket && i < packet_count; i++) {
+	for (i = 0; subpacket && i < packet_count; i++) {
 		printk("%sPROCESSING SUBPACKET %d\n", err_print_prefix, i);
 		subpacket = el_process_subpacket(subpacket);
 	}
@@ -636,7 +636,7 @@ el_process_subpacket_reg(struct el_subpacket *header)
 	struct el_subpacket *next = NULL;
 	struct el_subpacket_handler *h = subpacket_handler_list;
 
-	for(; h && h->class != header->class; h = h->next);
+	for (; h && h->class != header->class; h = h->next);
 	if (h) next = h->handler(header);
 
 	return next;
@@ -673,7 +673,7 @@ el_annotate_subpacket(struct el_subpacket *header)
 	struct el_subpacket_annotation *a;
 	char **annotation = NULL;
 
-	for(a = subpacket_annotation_list; a; a = a->next) {
+	for (a = subpacket_annotation_list; a; a = a->next) {
 		if (a->class == header->class &&
 		    a->type == header->type &&
 		    a->revision == header->revision) {
@@ -700,7 +700,7 @@ cdl_process_console_data_log(int cpu, struct percpu_struct *pcpu)
 	         "*** Error(s) were logged on a previous boot\n",
 	       err_print_prefix, cpu);
 	
-	for(err = 0; header && (header->class != EL_CLASS__TERMINATION); err++)
+	for (err = 0; header && (header->class != EL_CLASS__TERMINATION); err++)
 		header = el_process_subpacket(header);
 
 	/* let the console know it's ok to clear the error(s) at restart */
@@ -715,9 +715,9 @@ void __init
 cdl_check_console_data_log(void)
 {
 	struct percpu_struct *pcpu;
-	int cpu;
+	unsigned long cpu;
 
-	for(cpu = 0; cpu < hwrpb->nr_processors; cpu++) {
+	for (cpu = 0; cpu < hwrpb->nr_processors; cpu++) {
 		pcpu = (struct percpu_struct *)
 			((unsigned long)hwrpb + hwrpb->processor_offset 
 			 + cpu * hwrpb->processor_size);
@@ -734,7 +734,7 @@ cdl_register_subpacket_annotation(struct el_subpacket_annotation *new)
 
 	if (a == NULL) subpacket_annotation_list = new;
 	else {
-		for(; a->next != NULL; a = a->next) {
+		for (; a->next != NULL; a = a->next) {
 			if ((a->class == new->class && a->type == new->type) ||
 			    a == new) {
 				printk("Attempted to re-register "
@@ -756,7 +756,7 @@ cdl_register_subpacket_handler(struct el_subpacket_handler *new)
 
 	if (h == NULL) subpacket_handler_list = new;
 	else {
-		for(; h->next != NULL; h = h->next) {
+		for (; h->next != NULL; h = h->next) {
 			if (h->class == new->class || h == new) {
 				printk("Attempted to re-register "
 				       "subpacket handler\n");

arch/alpha/kernel/err_impl.h

@@ -133,7 +133,7 @@ struct el_subpacket_handler {
  */
 extern char *err_print_prefix;
 
-extern void mchk_dump_mem(void *, int, char **);
+extern void mchk_dump_mem(void *, size_t, char **);
 extern void mchk_dump_logout_frame(struct el_common *);
 extern void ev7_register_error_handlers(void);
 extern void ev7_machine_check(u64, u64, struct pt_regs *);

arch/alpha/kernel/irq.c

@@ -252,7 +252,7 @@ parse_hex_value (const char *buffer,
 {
 	unsigned char hexnum [HEX_DIGITS];
 	unsigned long value;
-	int i;
+	unsigned long i;
 
 	if (!count)
 		return -EINVAL;

arch/alpha/kernel/osf_sys.c

@@ -103,7 +103,7 @@ struct osf_dirent {
 struct osf_dirent_callback {
 	struct osf_dirent *dirent;
 	long *basep;
-	int count;
+	unsigned int count;
 	int error;
 };
 
@@ -113,7 +113,7 @@ osf_filldir(void *__buf, const char *name, int namlen, loff_t offset,
 {
 	struct osf_dirent *dirent;
 	struct osf_dirent_callback *buf = (struct osf_dirent_callback *) __buf;
-	int reclen = ROUND_UP(NAME_OFFSET(dirent) + namlen + 1);
+	unsigned int reclen = ROUND_UP(NAME_OFFSET(dirent) + namlen + 1);
 
 	buf->error = -EINVAL;	/* only used if we fail */
 	if (reclen > buf->count)
@@ -1343,14 +1343,14 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
 
 	if (addr) {
 		addr = arch_get_unmapped_area_1 (PAGE_ALIGN(addr), len, limit);
-		if (addr != -ENOMEM)
+		if (addr != (unsigned long) -ENOMEM)
 			return addr;
 	}
 
 	/* Next, try allocating at TASK_UNMAPPED_BASE.  */
 	addr = arch_get_unmapped_area_1 (PAGE_ALIGN(TASK_UNMAPPED_BASE),
 					 len, limit);
-	if (addr != -ENOMEM)
+	if (addr != (unsigned long) -ENOMEM)
 		return addr;
 
 	/* Finally, try allocating in low memory.  */

arch/alpha/kernel/pci.c

@@ -474,5 +474,5 @@ int
 pci_controller_num(struct pci_dev *pdev)
 {
         struct pci_controller *hose = pdev->sysdata;
-	return (hose ? hose->index : -ENXIO);
+	return (hose ? (int) hose->index : -ENXIO);
 }

arch/alpha/kernel/setup.c

@@ -98,9 +98,11 @@ unsigned char aux_device_present = 0xaa;
 
 #define N(a) (sizeof(a)/sizeof(a[0]))
 
-static struct alpha_machine_vector *get_sysvec(long, long, long);
+static struct alpha_machine_vector *get_sysvec(unsigned long, unsigned long,
+					       unsigned long);
 static struct alpha_machine_vector *get_sysvec_byname(const char *);
-static void get_sysnames(long, long, long, char **, char **);
+static void get_sysnames(unsigned long, unsigned long, unsigned long,
+			 char **, char **);
 
 static char command_line[COMMAND_LINE_SIZE];
 char saved_command_line[COMMAND_LINE_SIZE];
@@ -202,7 +204,7 @@ reserve_std_resources(void)
 	};
 
 	struct resource *io = &ioport_resource;
-	long i;
+	size_t i;
 
 	if (hose_head) {
 		struct pci_controller *hose;
@@ -258,7 +260,7 @@ setup_memory(void *kernel_end)
 	unsigned long start_kernel_pfn, end_kernel_pfn;
 	unsigned long bootmap_size, bootmap_pages, bootmap_start;
 	unsigned long start, end;
-	int i;
+	unsigned long i;
 
 	/* Find free clusters, and init and free the bootmem accordingly.  */
 	memdesc = (struct memdesc_struct *)
@@ -327,7 +329,7 @@ setup_memory(void *kernel_end)
 		}
 	}
 
-	if (bootmap_start == -1) {
+	if (bootmap_start == ~0UL) {
 		max_low_pfn >>= 1;
 		goto try_again;
 	}
@@ -398,7 +400,7 @@ page_is_ram(unsigned long pfn)
 {
 	struct memclust_struct * cluster;
 	struct memdesc_struct * memdesc;
-	int i;
+	unsigned long i;
 
 	memdesc = (struct memdesc_struct *)
 		(hwrpb->mddt_offset + (unsigned long) hwrpb);
@@ -691,7 +693,7 @@ static char tsunami_names[][16] = {
 static int tsunami_indices[] = {0,1,2,3,4,5,6,7,8,9,10,11,12};
 
 static struct alpha_machine_vector * __init
-get_sysvec(long type, long variation, long cpu)
+get_sysvec(unsigned long type, unsigned long variation, unsigned long cpu)
 {
 	static struct alpha_machine_vector *systype_vecs[] __initdata =
 	{
@@ -798,10 +800,6 @@ get_sysvec(long type, long variation, long cpu)
 
 	struct alpha_machine_vector *vec;
 
-	/* Restore real CABRIO and EB66+ family names, ie EB64+ and EB66 */
-	if (type < 0)
-		type = -type;
-
 	/* Search the system tables first... */
 	vec = NULL;
 	if (type < N(systype_vecs)) {
@@ -818,7 +816,7 @@ get_sysvec(long type, long variation, long cpu)
 
 	if (!vec) {
 		/* Member ID is a bit-field. */
-		long member = (variation >> 10) & 0x3f;
+		unsigned long member = (variation >> 10) & 0x3f;
 
 		cpu &= 0xffffffff; /* make it usable */
 
@@ -917,8 +915,9 @@ get_sysvec_byname(const char *name)
 		&xlt_mv
 	};
 
-	int i, n = sizeof(all_vecs)/sizeof(*all_vecs);
-	for (i = 0; i < n; ++i) {
+	size_t i;
+
+	for (i = 0; i < N(all_vecs); ++i) {
 		struct alpha_machine_vector *mv = all_vecs[i];
 		if (strcasecmp(mv->vector_name, name) == 0)
 			return mv;
@@ -927,14 +926,10 @@ get_sysvec_byname(const char *name)
 }
 
 static void
-get_sysnames(long type, long variation, long cpu,
+get_sysnames(unsigned long type, unsigned long variation, unsigned long cpu,
 	     char **type_name, char **variation_name)
 {
-	long member;
-
-	/* Restore real CABRIO and EB66+ family names, ie EB64+ and EB66 */
-	if (type < 0)
-		type = -type;
+	unsigned long member;
 
 	/* If not in the tables, make it UNKNOWN,
 	   else set type name to family */
@@ -952,7 +947,7 @@ get_sysnames(long type, long variation, long cpu,
 		return;
 	}
 
-	/* Set variation to "0"; if variation is zero, done */
+	/* Set variation to "0"; if variation is zero, done.  */
 	*variation_name = systype_names[0];
 	if (variation == 0) {
 		return;
@@ -1042,7 +1037,8 @@ static int
 get_nr_processors(struct percpu_struct *cpubase, unsigned long num)
 {
 	struct percpu_struct *cpu;
-	int i, count = 0;
+	unsigned long i;
+	int count = 0;
 
 	for (i = 0; i < num; i++) {
 		cpu = (struct percpu_struct *)

arch/alpha/kernel/smc37c669.c

@@ -970,8 +970,8 @@ void SMC37c669_display_device_info(
 static struct DEVICE_CONFIG {
     unsigned int port1;
     unsigned int port2;
-    unsigned int irq;
-    unsigned int drq;
+    int irq;
+    int drq;
 } local_config [NUM_FUNCS];
 
 /*
@@ -1097,11 +1097,11 @@ static struct DEVICE_CONFIG *SMC37c669_get_config(
 );
 
 static int SMC37c669_xlate_irq(
-    unsigned int irq 
+    int irq 
 );
 
 static int SMC37c669_xlate_drq(
-    unsigned int drq 
+    int drq 
 );
 
 static spinlock_t smc_lock __cacheline_aligned = SPIN_LOCK_UNLOCKED;
@@ -2260,7 +2260,7 @@ static struct DEVICE_CONFIG * __init SMC37c669_get_config( unsigned int func )
 **
 **--
 */
-static int __init SMC37c669_xlate_irq ( unsigned int irq )
+static int __init SMC37c669_xlate_irq ( int irq )
 {
     int i, translated_irq = -1;
 
@@ -2312,7 +2312,7 @@ static int __init SMC37c669_xlate_irq ( unsigned int irq )
 **
 **--
 */
-static int __init SMC37c669_xlate_drq ( unsigned int drq )
+static int __init SMC37c669_xlate_drq ( int drq )
 {
     int i, translated_drq = -1;
 

arch/alpha/kernel/smp.c

@@ -499,7 +499,7 @@ void __init
 setup_smp(void)
 {
 	struct percpu_struct *cpubase, *cpu;
-	int i;
+	unsigned long i;
 
 	if (boot_cpuid != 0) {
 		printk(KERN_WARNING "SMP: Booting off cpu %d instead of 0?\n",
@@ -516,7 +516,7 @@ setup_smp(void)
 			((char*)hwrpb + hwrpb->processor_offset);
 		boot_cpu_palrev = cpubase->pal_revision;
 
-		for (i = 0; i < hwrpb->nr_processors; i++ ) {
+		for (i = 0; i < hwrpb->nr_processors; i++) {
 			cpu = (struct percpu_struct *)
 				((char *)cpubase + i*hwrpb->processor_size);
 			if ((cpu->flags & 0x1cc) == 0x1cc) {

arch/alpha/kernel/time.c

@@ -316,7 +316,7 @@ time_init(void)
 		diff = cycle_freq - est_cycle_freq;
 		if (diff < 0)
 			diff = -diff;
-		if (diff > one_percent) {
+		if ((unsigned long)diff > one_percent) {
 			cycle_freq = est_cycle_freq;
 			printk("HWRPB cycle frequency bogus.  "
 			       "Estimated %lu Hz\n", cycle_freq);

arch/alpha/lib/fpreg.c

@@ -48,6 +48,7 @@ alpha_read_fp_reg (unsigned long reg)
 	      case 29: STT(29, val); break;
 	      case 30: STT(30, val); break;
 	      case 31: STT(31, val); break;
+	      default: return 0;
 	}
 	return val;
 }
@@ -141,6 +142,7 @@ alpha_read_fp_reg_s (unsigned long reg)
 	      case 29: STS(29, val); break;
 	      case 30: STS(30, val); break;
 	      case 31: STS(31, val); break;
+	      default: return 0;
 	}
 	return val;
 }

arch/alpha/lib/io.c

@@ -414,7 +414,7 @@ void _memcpy_fromio(void * to, unsigned long from, long count)
 	/* Optimize co-aligned transfers.  Everything else gets handled
 	   a byte at a time. */
 
-	if (count >= 8 && ((long)to & 7) == (from & 7)) {
+	if (count >= 8 && ((unsigned long)to & 7) == (from & 7)) {
 		count -= 8;
 		do {
 			*(u64 *)to = __raw_readq(from);
@@ -425,7 +425,7 @@ void _memcpy_fromio(void * to, unsigned long from, long count)
 		count += 8;
 	}
 
-	if (count >= 4 && ((long)to & 3) == (from & 3)) {
+	if (count >= 4 && ((unsigned long)to & 3) == (from & 3)) {
 		count -= 4;
 		do {
 			*(u32 *)to = __raw_readl(from);
@@ -436,7 +436,7 @@ void _memcpy_fromio(void * to, unsigned long from, long count)
 		count += 4;
 	}
 		
-	if (count >= 2 && ((long)to & 1) == (from & 1)) {
+	if (count >= 2 && ((unsigned long)to & 1) == (from & 1)) {
 		count -= 2;
 		do {
 			*(u16 *)to = __raw_readw(from);
@@ -465,7 +465,7 @@ void _memcpy_toio(unsigned long to, const void * from, long count)
 	   a byte at a time. */
 	/* FIXME -- align FROM.  */
 
-	if (count >= 8 && (to & 7) == ((long)from & 7)) {
+	if (count >= 8 && (to & 7) == ((unsigned long)from & 7)) {
 		count -= 8;
 		do {
 			__raw_writeq(*(const u64 *)from, to);
@@ -476,7 +476,7 @@ void _memcpy_toio(unsigned long to, const void * from, long count)
 		count += 8;
 	}
 
-	if (count >= 4 && (to & 3) == ((long)from & 3)) {
+	if (count >= 4 && (to & 3) == ((unsigned long)from & 3)) {
 		count -= 4;
 		do {
 			__raw_writel(*(const u32 *)from, to);
@@ -487,7 +487,7 @@ void _memcpy_toio(unsigned long to, const void * from, long count)
 		count += 4;
 	}
 		
-	if (count >= 2 && (to & 1) == ((long)from & 1)) {
+	if (count >= 2 && (to & 1) == ((unsigned long)from & 1)) {
 		count -= 2;
 		do {
 			__raw_writew(*(const u16 *)from, to);

arch/alpha/mm/init.c

@@ -242,7 +242,7 @@ callback_init(void * kernel_end)
 	if (alpha_using_srm) {
 		static struct vm_struct console_remap_vm;
 		unsigned long vaddr = VMALLOC_START;
-		long i, j;
+		unsigned long i, j;
 
 		/* Set up the third level PTEs and update the virtual
 		   addresses of the CRB entries.  */

include/asm-alpha/xor.h

@@ -32,793 +32,793 @@ extern void xor_alpha_prefetch_5(unsigned long, unsigned long *,
 				 unsigned long *, unsigned long *,
 				 unsigned long *, unsigned long *);
 
-asm("
-	.text
-	.align 3
-	.ent xor_alpha_2
-xor_alpha_2:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-2:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,8($17)
-	ldq $3,8($18)
-
-	ldq $4,16($17)
-	ldq $5,16($18)
-	ldq $6,24($17)
-	ldq $7,24($18)
-
-	ldq $19,32($17)
-	ldq $20,32($18)
-	ldq $21,40($17)
-	ldq $22,40($18)
-
-	ldq $23,48($17)
-	ldq $24,48($18)
-	ldq $25,56($17)
-	xor $0,$1,$0		# 7 cycles from $1 load
-
-	ldq $27,56($18)
-	xor $2,$3,$2
-	stq $0,0($17)
-	xor $4,$5,$4
-
-	stq $2,8($17)
-	xor $6,$7,$6
-	stq $4,16($17)
-	xor $19,$20,$19
-
-	stq $6,24($17)
-	xor $21,$22,$21
-	stq $19,32($17)
-	xor $23,$24,$23
-
-	stq $21,40($17)
-	xor $25,$27,$25
-	stq $23,48($17)
-	subq $16,1,$16
-
-	stq $25,56($17)
-	addq $17,64,$17
-	addq $18,64,$18
-	bgt $16,2b
-
-	ret
-	.end xor_alpha_2
-
-	.align 3
-	.ent xor_alpha_3
-xor_alpha_3:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-3:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,8($17)
-
-	ldq $4,8($18)
-	ldq $6,16($17)
-	ldq $7,16($18)
-	ldq $21,24($17)
-
-	ldq $22,24($18)
-	ldq $24,32($17)
-	ldq $25,32($18)
-	ldq $5,8($19)
-
-	ldq $20,16($19)
-	ldq $23,24($19)
-	ldq $27,32($19)
-	nop
-
-	xor $0,$1,$1		# 8 cycles from $0 load
-	xor $3,$4,$4		# 6 cycles from $4 load
-	xor $6,$7,$7		# 6 cycles from $7 load
-	xor $21,$22,$22		# 5 cycles from $22 load
-
-	xor $1,$2,$2		# 9 cycles from $2 load
-	xor $24,$25,$25		# 5 cycles from $25 load
-	stq $2,0($17)
-	xor $4,$5,$5		# 6 cycles from $5 load
-
-	stq $5,8($17)
-	xor $7,$20,$20		# 7 cycles from $20 load
-	stq $20,16($17)
-	xor $22,$23,$23		# 7 cycles from $23 load
-
-	stq $23,24($17)
-	xor $25,$27,$27		# 7 cycles from $27 load
-	stq $27,32($17)
-	nop
-
-	ldq $0,40($17)
-	ldq $1,40($18)
-	ldq $3,48($17)
-	ldq $4,48($18)
-
-	ldq $6,56($17)
-	ldq $7,56($18)
-	ldq $2,40($19)
-	ldq $5,48($19)
-
-	ldq $20,56($19)
-	xor $0,$1,$1		# 4 cycles from $1 load
-	xor $3,$4,$4		# 5 cycles from $4 load
-	xor $6,$7,$7		# 5 cycles from $7 load
-
-	xor $1,$2,$2		# 4 cycles from $2 load
-	xor $4,$5,$5		# 5 cycles from $5 load
-	stq $2,40($17)
-	xor $7,$20,$20		# 4 cycles from $20 load
-
-	stq $5,48($17)
-	subq $16,1,$16
-	stq $20,56($17)
-	addq $19,64,$19
-
-	addq $18,64,$18
-	addq $17,64,$17
-	bgt $16,3b
-	ret
-	.end xor_alpha_3
-
-	.align 3
-	.ent xor_alpha_4
-xor_alpha_4:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-4:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,8($17)
-	ldq $5,8($18)
-	ldq $6,8($19)
-	ldq $7,8($20)
-
-	ldq $21,16($17)
-	ldq $22,16($18)
-	ldq $23,16($19)
-	ldq $24,16($20)
-
-	ldq $25,24($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $27,24($18)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,24($19)
-	xor $1,$3,$3
-	ldq $1,24($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $3,0($17)
-	xor $6,$7,$7
-	xor $21,$22,$22		# 7 cycles from $22 load
-	xor $5,$7,$7
-
-	stq $7,8($17)
-	xor $23,$24,$24		# 7 cycles from $24 load
-	ldq $2,32($17)
-	xor $22,$24,$24
-
-	ldq $3,32($18)
-	ldq $4,32($19)
-	ldq $5,32($20)
-	xor $25,$27,$27		# 8 cycles from $27 load
-
-	ldq $6,40($17)
-	ldq $7,40($18)
-	ldq $21,40($19)
-	ldq $22,40($20)
-
-	stq $24,16($17)
-	xor $0,$1,$1		# 9 cycles from $1 load
-	xor $2,$3,$3		# 5 cycles from $3 load
-	xor $27,$1,$1
-
-	stq $1,24($17)
-	xor $4,$5,$5		# 5 cycles from $5 load
-	ldq $23,48($17)
-	ldq $24,48($18)
-
-	ldq $25,48($19)
-	xor $3,$5,$5
-	ldq $27,48($20)
-	ldq $0,56($17)
-
-	ldq $1,56($18)
-	ldq $2,56($19)
-	xor $6,$7,$7		# 8 cycles from $6 load
-	ldq $3,56($20)
-
-	stq $5,32($17)
-	xor $21,$22,$22		# 8 cycles from $22 load
-	xor $7,$22,$22
-	xor $23,$24,$24		# 5 cycles from $24 load
-
-	stq $22,40($17)
-	xor $25,$27,$27		# 5 cycles from $27 load
-	xor $24,$27,$27
-	xor $0,$1,$1		# 5 cycles from $1 load
-
-	stq $27,48($17)
-	xor $2,$3,$3		# 4 cycles from $3 load
-	xor $1,$3,$3
-	subq $16,1,$16
-
-	stq $3,56($17)
-	addq $20,64,$20
-	addq $19,64,$19
-	addq $18,64,$18
-
-	addq $17,64,$17
-	bgt $16,4b
-	ret
-	.end xor_alpha_4
-
-	.align 3
-	.ent xor_alpha_5
-xor_alpha_5:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-5:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,0($21)
-	ldq $5,8($17)
-	ldq $6,8($18)
-	ldq $7,8($19)
-
-	ldq $22,8($20)
-	ldq $23,8($21)
-	ldq $24,16($17)
-	ldq $25,16($18)
-
-	ldq $27,16($19)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $28,16($20)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,16($21)
-	xor $1,$3,$3
-	ldq $1,24($17)
-	xor $3,$4,$4		# 7 cycles from $4 load
-
-	stq $4,0($17)
-	xor $5,$6,$6		# 7 cycles from $6 load
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $6,$23,$23		# 7 cycles from $23 load
-
-	ldq $2,24($18)
-	xor $22,$23,$23
-	ldq $3,24($19)
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $23,8($17)
-	xor $25,$27,$27		# 8 cycles from $27 load
-	ldq $4,24($20)
-	xor $28,$0,$0		# 7 cycles from $0 load
-
-	ldq $5,24($21)
-	xor $27,$0,$0
-	ldq $6,32($17)
-	ldq $7,32($18)
-
-	stq $0,16($17)
-	xor $1,$2,$2		# 6 cycles from $2 load
-	ldq $22,32($19)
-	xor $3,$4,$4		# 4 cycles from $4 load
-	
-	ldq $23,32($20)
-	xor $2,$4,$4
-	ldq $24,32($21)
-	ldq $25,40($17)
-
-	ldq $27,40($18)
-	ldq $28,40($19)
-	ldq $0,40($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $5,24($17)
-	xor $6,$7,$7		# 7 cycles from $7 load
-	ldq $1,40($21)
-	ldq $2,48($17)
-
-	ldq $3,48($18)
-	xor $7,$22,$22		# 7 cycles from $22 load
-	ldq $4,48($19)
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	ldq $5,48($20)
-	xor $22,$24,$24
-	ldq $6,48($21)
-	xor $25,$27,$27		# 7 cycles from $27 load
-
-	stq $24,32($17)
-	xor $27,$28,$28		# 8 cycles from $28 load
-	ldq $7,56($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-
-	ldq $22,56($18)
-	ldq $23,56($19)
-	ldq $24,56($20)
-	ldq $25,56($21)
-
-	xor $28,$1,$1
-	xor $2,$3,$3		# 9 cycles from $3 load
-	xor $3,$4,$4		# 9 cycles from $4 load
-	xor $5,$6,$6		# 8 cycles from $6 load
-
-	stq $1,40($17)
-	xor $4,$6,$6
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	stq $6,48($17)
-	xor $22,$24,$24
-	subq $16,1,$16
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $25,56($17)
-	addq $21,64,$21
-	addq $20,64,$20
-	addq $19,64,$19
-
-	addq $18,64,$18
-	addq $17,64,$17
-	bgt $16,5b
-	ret
-	.end xor_alpha_5
-
-	.align 3
-	.ent xor_alpha_prefetch_2
-xor_alpha_prefetch_2:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	.align 4
-2:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,8($17)
-	ldq $3,8($18)
-
-	ldq $4,16($17)
-	ldq $5,16($18)
-	ldq $6,24($17)
-	ldq $7,24($18)
-
-	ldq $19,32($17)
-	ldq $20,32($18)
-	ldq $21,40($17)
-	ldq $22,40($18)
-
-	ldq $23,48($17)
-	ldq $24,48($18)
-	ldq $25,56($17)
-	ldq $27,56($18)
-
-	ldq $31,256($17)
-	xor $0,$1,$0		# 8 cycles from $1 load
-	ldq $31,256($18)
-	xor $2,$3,$2
-
-	stq $0,0($17)
-	xor $4,$5,$4
-	stq $2,8($17)
-	xor $6,$7,$6
-
-	stq $4,16($17)
-	xor $19,$20,$19
-	stq $6,24($17)
-	xor $21,$22,$21
-
-	stq $19,32($17)
-	xor $23,$24,$23
-	stq $21,40($17)
-	xor $25,$27,$25
-
-	stq $23,48($17)
-	subq $16,1,$16
-	stq $25,56($17)
-	addq $17,64,$17
-
-	addq $18,64,$18
-	bgt $16,2b
-	ret
-	.end xor_alpha_prefetch_2
-
-	.align 3
-	.ent xor_alpha_prefetch_3
-xor_alpha_prefetch_3:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-	ldq $31, 0($19)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-	ldq $31, 64($19)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-	ldq $31, 128($19)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	ldq $31, 192($19)
-	.align 4
-3:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,8($17)
-
-	ldq $4,8($18)
-	ldq $6,16($17)
-	ldq $7,16($18)
-	ldq $21,24($17)
-
-	ldq $22,24($18)
-	ldq $24,32($17)
-	ldq $25,32($18)
-	ldq $5,8($19)
-
-	ldq $20,16($19)
-	ldq $23,24($19)
-	ldq $27,32($19)
-	nop
-
-	xor $0,$1,$1		# 8 cycles from $0 load
-	xor $3,$4,$4		# 7 cycles from $4 load
-	xor $6,$7,$7		# 6 cycles from $7 load
-	xor $21,$22,$22		# 5 cycles from $22 load
-
-	xor $1,$2,$2		# 9 cycles from $2 load
-	xor $24,$25,$25		# 5 cycles from $25 load
-	stq $2,0($17)
-	xor $4,$5,$5		# 6 cycles from $5 load
-
-	stq $5,8($17)
-	xor $7,$20,$20		# 7 cycles from $20 load
-	stq $20,16($17)
-	xor $22,$23,$23		# 7 cycles from $23 load
-
-	stq $23,24($17)
-	xor $25,$27,$27		# 7 cycles from $27 load
-	stq $27,32($17)
-	nop
-
-	ldq $0,40($17)
-	ldq $1,40($18)
-	ldq $3,48($17)
-	ldq $4,48($18)
-
-	ldq $6,56($17)
-	ldq $7,56($18)
-	ldq $2,40($19)
-	ldq $5,48($19)
-
-	ldq $20,56($19)
-	ldq $31,256($17)
-	ldq $31,256($18)
-	ldq $31,256($19)
-
-	xor $0,$1,$1		# 6 cycles from $1 load
-	xor $3,$4,$4		# 5 cycles from $4 load
-	xor $6,$7,$7		# 5 cycles from $7 load
-	xor $1,$2,$2		# 4 cycles from $2 load
-	
-	xor $4,$5,$5		# 5 cycles from $5 load
-	xor $7,$20,$20		# 4 cycles from $20 load
-	stq $2,40($17)
-	subq $16,1,$16
-
-	stq $5,48($17)
-	addq $19,64,$19
-	stq $20,56($17)
-	addq $18,64,$18
-
-	addq $17,64,$17
-	bgt $16,3b
-	ret
-	.end xor_alpha_prefetch_3
-
-	.align 3
-	.ent xor_alpha_prefetch_4
-xor_alpha_prefetch_4:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-	ldq $31, 0($19)
-	ldq $31, 0($20)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-	ldq $31, 64($19)
-	ldq $31, 64($20)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-	ldq $31, 128($19)
-	ldq $31, 128($20)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	ldq $31, 192($19)
-	ldq $31, 192($20)
-	.align 4
-4:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,8($17)
-	ldq $5,8($18)
-	ldq $6,8($19)
-	ldq $7,8($20)
-
-	ldq $21,16($17)
-	ldq $22,16($18)
-	ldq $23,16($19)
-	ldq $24,16($20)
-
-	ldq $25,24($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $27,24($18)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,24($19)
-	xor $1,$3,$3
-	ldq $1,24($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $3,0($17)
-	xor $6,$7,$7
-	xor $21,$22,$22		# 7 cycles from $22 load
-	xor $5,$7,$7
-
-	stq $7,8($17)
-	xor $23,$24,$24		# 7 cycles from $24 load
-	ldq $2,32($17)
-	xor $22,$24,$24
-
-	ldq $3,32($18)
-	ldq $4,32($19)
-	ldq $5,32($20)
-	xor $25,$27,$27		# 8 cycles from $27 load
-
-	ldq $6,40($17)
-	ldq $7,40($18)
-	ldq $21,40($19)
-	ldq $22,40($20)
-
-	stq $24,16($17)
-	xor $0,$1,$1		# 9 cycles from $1 load
-	xor $2,$3,$3		# 5 cycles from $3 load
-	xor $27,$1,$1
-
-	stq $1,24($17)
-	xor $4,$5,$5		# 5 cycles from $5 load
-	ldq $23,48($17)
-	xor $3,$5,$5
-
-	ldq $24,48($18)
-	ldq $25,48($19)
-	ldq $27,48($20)
-	ldq $0,56($17)
-
-	ldq $1,56($18)
-	ldq $2,56($19)
-	ldq $3,56($20)
-	xor $6,$7,$7		# 8 cycles from $6 load
-
-	ldq $31,256($17)
-	xor $21,$22,$22		# 8 cycles from $22 load
-	ldq $31,256($18)
-	xor $7,$22,$22
-
-	ldq $31,256($19)
-	xor $23,$24,$24		# 6 cycles from $24 load
-	ldq $31,256($20)
-	xor $25,$27,$27		# 6 cycles from $27 load
-
-	stq $5,32($17)
-	xor $24,$27,$27
-	xor $0,$1,$1		# 7 cycles from $1 load
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	stq $22,40($17)
-	xor $1,$3,$3
-	stq $27,48($17)
-	subq $16,1,$16
-
-	stq $3,56($17)
-	addq $20,64,$20
-	addq $19,64,$19
-	addq $18,64,$18
-
-	addq $17,64,$17
-	bgt $16,4b
-	ret
-	.end xor_alpha_prefetch_4
-
-	.align 3
-	.ent xor_alpha_prefetch_5
-xor_alpha_prefetch_5:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-	ldq $31, 0($19)
-	ldq $31, 0($20)
-	ldq $31, 0($21)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-	ldq $31, 64($19)
-	ldq $31, 64($20)
-	ldq $31, 64($21)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-	ldq $31, 128($19)
-	ldq $31, 128($20)
-	ldq $31, 128($21)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	ldq $31, 192($19)
-	ldq $31, 192($20)
-	ldq $31, 192($21)
-	.align 4
-5:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,0($21)
-	ldq $5,8($17)
-	ldq $6,8($18)
-	ldq $7,8($19)
-
-	ldq $22,8($20)
-	ldq $23,8($21)
-	ldq $24,16($17)
-	ldq $25,16($18)
-
-	ldq $27,16($19)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $28,16($20)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,16($21)
-	xor $1,$3,$3
-	ldq $1,24($17)
-	xor $3,$4,$4		# 7 cycles from $4 load
-
-	stq $4,0($17)
-	xor $5,$6,$6		# 7 cycles from $6 load
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $6,$23,$23		# 7 cycles from $23 load
-
-	ldq $2,24($18)
-	xor $22,$23,$23
-	ldq $3,24($19)
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $23,8($17)
-	xor $25,$27,$27		# 8 cycles from $27 load
-	ldq $4,24($20)
-	xor $28,$0,$0		# 7 cycles from $0 load
-
-	ldq $5,24($21)
-	xor $27,$0,$0
-	ldq $6,32($17)
-	ldq $7,32($18)
-
-	stq $0,16($17)
-	xor $1,$2,$2		# 6 cycles from $2 load
-	ldq $22,32($19)
-	xor $3,$4,$4		# 4 cycles from $4 load
-	
-	ldq $23,32($20)
-	xor $2,$4,$4
-	ldq $24,32($21)
-	ldq $25,40($17)
-
-	ldq $27,40($18)
-	ldq $28,40($19)
-	ldq $0,40($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $5,24($17)
-	xor $6,$7,$7		# 7 cycles from $7 load
-	ldq $1,40($21)
-	ldq $2,48($17)
-
-	ldq $3,48($18)
-	xor $7,$22,$22		# 7 cycles from $22 load
-	ldq $4,48($19)
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	ldq $5,48($20)
-	xor $22,$24,$24
-	ldq $6,48($21)
-	xor $25,$27,$27		# 7 cycles from $27 load
-
-	stq $24,32($17)
-	xor $27,$28,$28		# 8 cycles from $28 load
-	ldq $7,56($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-
-	ldq $22,56($18)
-	ldq $23,56($19)
-	ldq $24,56($20)
-	ldq $25,56($21)
-
-	ldq $31,256($17)
-	xor $28,$1,$1
-	ldq $31,256($18)
-	xor $2,$3,$3		# 9 cycles from $3 load
-
-	ldq $31,256($19)
-	xor $3,$4,$4		# 9 cycles from $4 load
-	ldq $31,256($20)
-	xor $5,$6,$6		# 8 cycles from $6 load
-
-	stq $1,40($17)
-	xor $4,$6,$6
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	stq $6,48($17)
-	xor $22,$24,$24
-	ldq $31,256($21)
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $25,56($17)
-	subq $16,1,$16
-	addq $21,64,$21
-	addq $20,64,$20
-
-	addq $19,64,$19
-	addq $18,64,$18
-	addq $17,64,$17
-	bgt $16,5b
-
-	ret
-	.end xor_alpha_prefetch_5
+asm("								\n\
+	.text							\n\
+	.align 3						\n\
+	.ent xor_alpha_2					\n\
+xor_alpha_2:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+2:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,8($17)						\n\
+	ldq $3,8($18)						\n\
+								\n\
+	ldq $4,16($17)						\n\
+	ldq $5,16($18)						\n\
+	ldq $6,24($17)						\n\
+	ldq $7,24($18)						\n\
+								\n\
+	ldq $19,32($17)						\n\
+	ldq $20,32($18)						\n\
+	ldq $21,40($17)						\n\
+	ldq $22,40($18)						\n\
+								\n\
+	ldq $23,48($17)						\n\
+	ldq $24,48($18)						\n\
+	ldq $25,56($17)						\n\
+	xor $0,$1,$0		# 7 cycles from $1 load		\n\
+								\n\
+	ldq $27,56($18)						\n\
+	xor $2,$3,$2						\n\
+	stq $0,0($17)						\n\
+	xor $4,$5,$4						\n\
+								\n\
+	stq $2,8($17)						\n\
+	xor $6,$7,$6						\n\
+	stq $4,16($17)						\n\
+	xor $19,$20,$19						\n\
+								\n\
+	stq $6,24($17)						\n\
+	xor $21,$22,$21						\n\
+	stq $19,32($17)						\n\
+	xor $23,$24,$23						\n\
+								\n\
+	stq $21,40($17)						\n\
+	xor $25,$27,$25						\n\
+	stq $23,48($17)						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $25,56($17)						\n\
+	addq $17,64,$17						\n\
+	addq $18,64,$18						\n\
+	bgt $16,2b						\n\
+								\n\
+	ret							\n\
+	.end xor_alpha_2					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_3					\n\
+xor_alpha_3:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+3:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,8($17)						\n\
+								\n\
+	ldq $4,8($18)						\n\
+	ldq $6,16($17)						\n\
+	ldq $7,16($18)						\n\
+	ldq $21,24($17)						\n\
+								\n\
+	ldq $22,24($18)						\n\
+	ldq $24,32($17)						\n\
+	ldq $25,32($18)						\n\
+	ldq $5,8($19)						\n\
+								\n\
+	ldq $20,16($19)						\n\
+	ldq $23,24($19)						\n\
+	ldq $27,32($19)						\n\
+	nop							\n\
+								\n\
+	xor $0,$1,$1		# 8 cycles from $0 load		\n\
+	xor $3,$4,$4		# 6 cycles from $4 load		\n\
+	xor $6,$7,$7		# 6 cycles from $7 load		\n\
+	xor $21,$22,$22		# 5 cycles from $22 load	\n\
+								\n\
+	xor $1,$2,$2		# 9 cycles from $2 load		\n\
+	xor $24,$25,$25		# 5 cycles from $25 load	\n\
+	stq $2,0($17)						\n\
+	xor $4,$5,$5		# 6 cycles from $5 load		\n\
+								\n\
+	stq $5,8($17)						\n\
+	xor $7,$20,$20		# 7 cycles from $20 load	\n\
+	stq $20,16($17)						\n\
+	xor $22,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	stq $23,24($17)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+	stq $27,32($17)						\n\
+	nop							\n\
+								\n\
+	ldq $0,40($17)						\n\
+	ldq $1,40($18)						\n\
+	ldq $3,48($17)						\n\
+	ldq $4,48($18)						\n\
+								\n\
+	ldq $6,56($17)						\n\
+	ldq $7,56($18)						\n\
+	ldq $2,40($19)						\n\
+	ldq $5,48($19)						\n\
+								\n\
+	ldq $20,56($19)						\n\
+	xor $0,$1,$1		# 4 cycles from $1 load		\n\
+	xor $3,$4,$4		# 5 cycles from $4 load		\n\
+	xor $6,$7,$7		# 5 cycles from $7 load		\n\
+								\n\
+	xor $1,$2,$2		# 4 cycles from $2 load		\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	stq $2,40($17)						\n\
+	xor $7,$20,$20		# 4 cycles from $20 load	\n\
+								\n\
+	stq $5,48($17)						\n\
+	subq $16,1,$16						\n\
+	stq $20,56($17)						\n\
+	addq $19,64,$19						\n\
+								\n\
+	addq $18,64,$18						\n\
+	addq $17,64,$17						\n\
+	bgt $16,3b						\n\
+	ret							\n\
+	.end xor_alpha_3					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_4					\n\
+xor_alpha_4:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+4:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,8($17)						\n\
+	ldq $5,8($18)						\n\
+	ldq $6,8($19)						\n\
+	ldq $7,8($20)						\n\
+								\n\
+	ldq $21,16($17)						\n\
+	ldq $22,16($18)						\n\
+	ldq $23,16($19)						\n\
+	ldq $24,16($20)						\n\
+								\n\
+	ldq $25,24($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $27,24($18)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,24($19)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $3,0($17)						\n\
+	xor $6,$7,$7						\n\
+	xor $21,$22,$22		# 7 cycles from $22 load	\n\
+	xor $5,$7,$7						\n\
+								\n\
+	stq $7,8($17)						\n\
+	xor $23,$24,$24		# 7 cycles from $24 load	\n\
+	ldq $2,32($17)						\n\
+	xor $22,$24,$24						\n\
+								\n\
+	ldq $3,32($18)						\n\
+	ldq $4,32($19)						\n\
+	ldq $5,32($20)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+								\n\
+	ldq $6,40($17)						\n\
+	ldq $7,40($18)						\n\
+	ldq $21,40($19)						\n\
+	ldq $22,40($20)						\n\
+								\n\
+	stq $24,16($17)						\n\
+	xor $0,$1,$1		# 9 cycles from $1 load		\n\
+	xor $2,$3,$3		# 5 cycles from $3 load		\n\
+	xor $27,$1,$1						\n\
+								\n\
+	stq $1,24($17)						\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	ldq $23,48($17)						\n\
+	ldq $24,48($18)						\n\
+								\n\
+	ldq $25,48($19)						\n\
+	xor $3,$5,$5						\n\
+	ldq $27,48($20)						\n\
+	ldq $0,56($17)						\n\
+								\n\
+	ldq $1,56($18)						\n\
+	ldq $2,56($19)						\n\
+	xor $6,$7,$7		# 8 cycles from $6 load		\n\
+	ldq $3,56($20)						\n\
+								\n\
+	stq $5,32($17)						\n\
+	xor $21,$22,$22		# 8 cycles from $22 load	\n\
+	xor $7,$22,$22						\n\
+	xor $23,$24,$24		# 5 cycles from $24 load	\n\
+								\n\
+	stq $22,40($17)						\n\
+	xor $25,$27,$27		# 5 cycles from $27 load	\n\
+	xor $24,$27,$27						\n\
+	xor $0,$1,$1		# 5 cycles from $1 load		\n\
+								\n\
+	stq $27,48($17)						\n\
+	xor $2,$3,$3		# 4 cycles from $3 load		\n\
+	xor $1,$3,$3						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $3,56($17)						\n\
+	addq $20,64,$20						\n\
+	addq $19,64,$19						\n\
+	addq $18,64,$18						\n\
+								\n\
+	addq $17,64,$17						\n\
+	bgt $16,4b						\n\
+	ret							\n\
+	.end xor_alpha_4					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_5					\n\
+xor_alpha_5:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+5:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,0($21)						\n\
+	ldq $5,8($17)						\n\
+	ldq $6,8($18)						\n\
+	ldq $7,8($19)						\n\
+								\n\
+	ldq $22,8($20)						\n\
+	ldq $23,8($21)						\n\
+	ldq $24,16($17)						\n\
+	ldq $25,16($18)						\n\
+								\n\
+	ldq $27,16($19)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $28,16($20)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,16($21)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($17)						\n\
+	xor $3,$4,$4		# 7 cycles from $4 load		\n\
+								\n\
+	stq $4,0($17)						\n\
+	xor $5,$6,$6		# 7 cycles from $6 load		\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $6,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	ldq $2,24($18)						\n\
+	xor $22,$23,$23						\n\
+	ldq $3,24($19)						\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $23,8($17)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+	ldq $4,24($20)						\n\
+	xor $28,$0,$0		# 7 cycles from $0 load		\n\
+								\n\
+	ldq $5,24($21)						\n\
+	xor $27,$0,$0						\n\
+	ldq $6,32($17)						\n\
+	ldq $7,32($18)						\n\
+								\n\
+	stq $0,16($17)						\n\
+	xor $1,$2,$2		# 6 cycles from $2 load		\n\
+	ldq $22,32($19)						\n\
+	xor $3,$4,$4		# 4 cycles from $4 load		\n\
+								\n\
+	ldq $23,32($20)						\n\
+	xor $2,$4,$4						\n\
+	ldq $24,32($21)						\n\
+	ldq $25,40($17)						\n\
+								\n\
+	ldq $27,40($18)						\n\
+	ldq $28,40($19)						\n\
+	ldq $0,40($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $5,24($17)						\n\
+	xor $6,$7,$7		# 7 cycles from $7 load		\n\
+	ldq $1,40($21)						\n\
+	ldq $2,48($17)						\n\
+								\n\
+	ldq $3,48($18)						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	ldq $4,48($19)						\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	ldq $5,48($20)						\n\
+	xor $22,$24,$24						\n\
+	ldq $6,48($21)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+								\n\
+	stq $24,32($17)						\n\
+	xor $27,$28,$28		# 8 cycles from $28 load	\n\
+	ldq $7,56($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+								\n\
+	ldq $22,56($18)						\n\
+	ldq $23,56($19)						\n\
+	ldq $24,56($20)						\n\
+	ldq $25,56($21)						\n\
+								\n\
+	xor $28,$1,$1						\n\
+	xor $2,$3,$3		# 9 cycles from $3 load		\n\
+	xor $3,$4,$4		# 9 cycles from $4 load		\n\
+	xor $5,$6,$6		# 8 cycles from $6 load		\n\
+								\n\
+	stq $1,40($17)						\n\
+	xor $4,$6,$6						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	stq $6,48($17)						\n\
+	xor $22,$24,$24						\n\
+	subq $16,1,$16						\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $25,56($17)						\n\
+	addq $21,64,$21						\n\
+	addq $20,64,$20						\n\
+	addq $19,64,$19						\n\
+								\n\
+	addq $18,64,$18						\n\
+	addq $17,64,$17						\n\
+	bgt $16,5b						\n\
+	ret							\n\
+	.end xor_alpha_5					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_2				\n\
+xor_alpha_prefetch_2:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	.align 4						\n\
+2:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,8($17)						\n\
+	ldq $3,8($18)						\n\
+								\n\
+	ldq $4,16($17)						\n\
+	ldq $5,16($18)						\n\
+	ldq $6,24($17)						\n\
+	ldq $7,24($18)						\n\
+								\n\
+	ldq $19,32($17)						\n\
+	ldq $20,32($18)						\n\
+	ldq $21,40($17)						\n\
+	ldq $22,40($18)						\n\
+								\n\
+	ldq $23,48($17)						\n\
+	ldq $24,48($18)						\n\
+	ldq $25,56($17)						\n\
+	ldq $27,56($18)						\n\
+								\n\
+	ldq $31,256($17)					\n\
+	xor $0,$1,$0		# 8 cycles from $1 load		\n\
+	ldq $31,256($18)					\n\
+	xor $2,$3,$2						\n\
+								\n\
+	stq $0,0($17)						\n\
+	xor $4,$5,$4						\n\
+	stq $2,8($17)						\n\
+	xor $6,$7,$6						\n\
+								\n\
+	stq $4,16($17)						\n\
+	xor $19,$20,$19						\n\
+	stq $6,24($17)						\n\
+	xor $21,$22,$21						\n\
+								\n\
+	stq $19,32($17)						\n\
+	xor $23,$24,$23						\n\
+	stq $21,40($17)						\n\
+	xor $25,$27,$25						\n\
+								\n\
+	stq $23,48($17)						\n\
+	subq $16,1,$16						\n\
+	stq $25,56($17)						\n\
+	addq $17,64,$17						\n\
+								\n\
+	addq $18,64,$18						\n\
+	bgt $16,2b						\n\
+	ret							\n\
+	.end xor_alpha_prefetch_2				\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_3				\n\
+xor_alpha_prefetch_3:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+	ldq $31, 0($19)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+	ldq $31, 64($19)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+	ldq $31, 128($19)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	ldq $31, 192($19)					\n\
+	.align 4						\n\
+3:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,8($17)						\n\
+								\n\
+	ldq $4,8($18)						\n\
+	ldq $6,16($17)						\n\
+	ldq $7,16($18)						\n\
+	ldq $21,24($17)						\n\
+								\n\
+	ldq $22,24($18)						\n\
+	ldq $24,32($17)						\n\
+	ldq $25,32($18)						\n\
+	ldq $5,8($19)						\n\
+								\n\
+	ldq $20,16($19)						\n\
+	ldq $23,24($19)						\n\
+	ldq $27,32($19)						\n\
+	nop							\n\
+								\n\
+	xor $0,$1,$1		# 8 cycles from $0 load		\n\
+	xor $3,$4,$4		# 7 cycles from $4 load		\n\
+	xor $6,$7,$7		# 6 cycles from $7 load		\n\
+	xor $21,$22,$22		# 5 cycles from $22 load	\n\
+								\n\
+	xor $1,$2,$2		# 9 cycles from $2 load		\n\
+	xor $24,$25,$25		# 5 cycles from $25 load	\n\
+	stq $2,0($17)						\n\
+	xor $4,$5,$5		# 6 cycles from $5 load		\n\
+								\n\
+	stq $5,8($17)						\n\
+	xor $7,$20,$20		# 7 cycles from $20 load	\n\
+	stq $20,16($17)						\n\
+	xor $22,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	stq $23,24($17)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+	stq $27,32($17)						\n\
+	nop							\n\
+								\n\
+	ldq $0,40($17)						\n\
+	ldq $1,40($18)						\n\
+	ldq $3,48($17)						\n\
+	ldq $4,48($18)						\n\
+								\n\
+	ldq $6,56($17)						\n\
+	ldq $7,56($18)						\n\
+	ldq $2,40($19)						\n\
+	ldq $5,48($19)						\n\
+								\n\
+	ldq $20,56($19)						\n\
+	ldq $31,256($17)					\n\
+	ldq $31,256($18)					\n\
+	ldq $31,256($19)					\n\
+								\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	xor $3,$4,$4		# 5 cycles from $4 load		\n\
+	xor $6,$7,$7		# 5 cycles from $7 load		\n\
+	xor $1,$2,$2		# 4 cycles from $2 load		\n\
+								\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	xor $7,$20,$20		# 4 cycles from $20 load	\n\
+	stq $2,40($17)						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $5,48($17)						\n\
+	addq $19,64,$19						\n\
+	stq $20,56($17)						\n\
+	addq $18,64,$18						\n\
+								\n\
+	addq $17,64,$17						\n\
+	bgt $16,3b						\n\
+	ret							\n\
+	.end xor_alpha_prefetch_3				\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_4				\n\
+xor_alpha_prefetch_4:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+	ldq $31, 0($19)						\n\
+	ldq $31, 0($20)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+	ldq $31, 64($19)					\n\
+	ldq $31, 64($20)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+	ldq $31, 128($19)					\n\
+	ldq $31, 128($20)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	ldq $31, 192($19)					\n\
+	ldq $31, 192($20)					\n\
+	.align 4						\n\
+4:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,8($17)						\n\
+	ldq $5,8($18)						\n\
+	ldq $6,8($19)						\n\
+	ldq $7,8($20)						\n\
+								\n\
+	ldq $21,16($17)						\n\
+	ldq $22,16($18)						\n\
+	ldq $23,16($19)						\n\
+	ldq $24,16($20)						\n\
+								\n\
+	ldq $25,24($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $27,24($18)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,24($19)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $3,0($17)						\n\
+	xor $6,$7,$7						\n\
+	xor $21,$22,$22		# 7 cycles from $22 load	\n\
+	xor $5,$7,$7						\n\
+								\n\
+	stq $7,8($17)						\n\
+	xor $23,$24,$24		# 7 cycles from $24 load	\n\
+	ldq $2,32($17)						\n\
+	xor $22,$24,$24						\n\
+								\n\
+	ldq $3,32($18)						\n\
+	ldq $4,32($19)						\n\
+	ldq $5,32($20)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+								\n\
+	ldq $6,40($17)						\n\
+	ldq $7,40($18)						\n\
+	ldq $21,40($19)						\n\
+	ldq $22,40($20)						\n\
+								\n\
+	stq $24,16($17)						\n\
+	xor $0,$1,$1		# 9 cycles from $1 load		\n\
+	xor $2,$3,$3		# 5 cycles from $3 load		\n\
+	xor $27,$1,$1						\n\
+								\n\
+	stq $1,24($17)						\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	ldq $23,48($17)						\n\
+	xor $3,$5,$5						\n\
+								\n\
+	ldq $24,48($18)						\n\
+	ldq $25,48($19)						\n\
+	ldq $27,48($20)						\n\
+	ldq $0,56($17)						\n\
+								\n\
+	ldq $1,56($18)						\n\
+	ldq $2,56($19)						\n\
+	ldq $3,56($20)						\n\
+	xor $6,$7,$7		# 8 cycles from $6 load		\n\
+								\n\
+	ldq $31,256($17)					\n\
+	xor $21,$22,$22		# 8 cycles from $22 load	\n\
+	ldq $31,256($18)					\n\
+	xor $7,$22,$22						\n\
+								\n\
+	ldq $31,256($19)					\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+	ldq $31,256($20)					\n\
+	xor $25,$27,$27		# 6 cycles from $27 load	\n\
+								\n\
+	stq $5,32($17)						\n\
+	xor $24,$27,$27						\n\
+	xor $0,$1,$1		# 7 cycles from $1 load		\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	stq $22,40($17)						\n\
+	xor $1,$3,$3						\n\
+	stq $27,48($17)						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $3,56($17)						\n\
+	addq $20,64,$20						\n\
+	addq $19,64,$19						\n\
+	addq $18,64,$18						\n\
+								\n\
+	addq $17,64,$17						\n\
+	bgt $16,4b						\n\
+	ret							\n\
+	.end xor_alpha_prefetch_4				\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_5				\n\
+xor_alpha_prefetch_5:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+	ldq $31, 0($19)						\n\
+	ldq $31, 0($20)						\n\
+	ldq $31, 0($21)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+	ldq $31, 64($19)					\n\
+	ldq $31, 64($20)					\n\
+	ldq $31, 64($21)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+	ldq $31, 128($19)					\n\
+	ldq $31, 128($20)					\n\
+	ldq $31, 128($21)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	ldq $31, 192($19)					\n\
+	ldq $31, 192($20)					\n\
+	ldq $31, 192($21)					\n\
+	.align 4						\n\
+5:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,0($21)						\n\
+	ldq $5,8($17)						\n\
+	ldq $6,8($18)						\n\
+	ldq $7,8($19)						\n\
+								\n\
+	ldq $22,8($20)						\n\
+	ldq $23,8($21)						\n\
+	ldq $24,16($17)						\n\
+	ldq $25,16($18)						\n\
+								\n\
+	ldq $27,16($19)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $28,16($20)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,16($21)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($17)						\n\
+	xor $3,$4,$4		# 7 cycles from $4 load		\n\
+								\n\
+	stq $4,0($17)						\n\
+	xor $5,$6,$6		# 7 cycles from $6 load		\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $6,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	ldq $2,24($18)						\n\
+	xor $22,$23,$23						\n\
+	ldq $3,24($19)						\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $23,8($17)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+	ldq $4,24($20)						\n\
+	xor $28,$0,$0		# 7 cycles from $0 load		\n\
+								\n\
+	ldq $5,24($21)						\n\
+	xor $27,$0,$0						\n\
+	ldq $6,32($17)						\n\
+	ldq $7,32($18)						\n\
+								\n\
+	stq $0,16($17)						\n\
+	xor $1,$2,$2		# 6 cycles from $2 load		\n\
+	ldq $22,32($19)						\n\
+	xor $3,$4,$4		# 4 cycles from $4 load		\n\
+								\n\
+	ldq $23,32($20)						\n\
+	xor $2,$4,$4						\n\
+	ldq $24,32($21)						\n\
+	ldq $25,40($17)						\n\
+								\n\
+	ldq $27,40($18)						\n\
+	ldq $28,40($19)						\n\
+	ldq $0,40($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $5,24($17)						\n\
+	xor $6,$7,$7		# 7 cycles from $7 load		\n\
+	ldq $1,40($21)						\n\
+	ldq $2,48($17)						\n\
+								\n\
+	ldq $3,48($18)						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	ldq $4,48($19)						\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	ldq $5,48($20)						\n\
+	xor $22,$24,$24						\n\
+	ldq $6,48($21)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+								\n\
+	stq $24,32($17)						\n\
+	xor $27,$28,$28		# 8 cycles from $28 load	\n\
+	ldq $7,56($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+								\n\
+	ldq $22,56($18)						\n\
+	ldq $23,56($19)						\n\
+	ldq $24,56($20)						\n\
+	ldq $25,56($21)						\n\
+								\n\
+	ldq $31,256($17)					\n\
+	xor $28,$1,$1						\n\
+	ldq $31,256($18)					\n\
+	xor $2,$3,$3		# 9 cycles from $3 load		\n\
+								\n\
+	ldq $31,256($19)					\n\
+	xor $3,$4,$4		# 9 cycles from $4 load		\n\
+	ldq $31,256($20)					\n\
+	xor $5,$6,$6		# 8 cycles from $6 load		\n\
+								\n\
+	stq $1,40($17)						\n\
+	xor $4,$6,$6						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	stq $6,48($17)						\n\
+	xor $22,$24,$24						\n\
+	ldq $31,256($21)					\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $25,56($17)						\n\
+	subq $16,1,$16						\n\
+	addq $21,64,$21						\n\
+	addq $20,64,$20						\n\
+								\n\
+	addq $19,64,$19						\n\
+	addq $18,64,$18						\n\
+	addq $17,64,$17						\n\
+	bgt $16,5b						\n\
+								\n\
+	ret							\n\
+	.end xor_alpha_prefetch_5				\n\
 ");
 
 static struct xor_block_template xor_block_alpha = {