Commit bae1f0b8 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher

drm/amd/display: Add z10 restore checks for DC interfaces

DMCUB has a deferred z10 restore process that needs signalling from
driver to occur. This needs to be done on any interface that programs
the hardware state or sequences where we expect to have the same
hardware state as before.
Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 64b1d0e8
...@@ -1482,6 +1482,13 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context) ...@@ -1482,6 +1482,13 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
return stream_mask; return stream_mask;
} }
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
void dc_z10_restore(struct dc *dc)
{
if (dc->hwss.z10_restore)
dc->hwss.z10_restore(dc);
}
#endif
/* /*
* Applies given context to HW and copy it into current context. * Applies given context to HW and copy it into current context.
* It's up to the user to release the src context afterwards. * It's up to the user to release the src context afterwards.
...@@ -1495,6 +1502,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c ...@@ -1495,6 +1502,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_DCN)
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
dc_z10_restore(dc);
#endif
dc_allow_idle_optimizations(dc, false); dc_allow_idle_optimizations(dc, false);
#endif #endif
...@@ -2569,6 +2579,10 @@ static void commit_planes_for_stream(struct dc *dc, ...@@ -2569,6 +2579,10 @@ static void commit_planes_for_stream(struct dc *dc,
int i, j; int i, j;
struct pipe_ctx *top_pipe_to_program = NULL; struct pipe_ctx *top_pipe_to_program = NULL;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
dc_z10_restore(dc);
#endif
if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) { if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
/* Optimize seamless boot flag keeps clocks and watermarks high until /* Optimize seamless boot flag keeps clocks and watermarks high until
* first flip. After first flip, optimization is required to lower * first flip. After first flip, optimization is required to lower
...@@ -3024,6 +3038,9 @@ void dc_set_power_state( ...@@ -3024,6 +3038,9 @@ void dc_set_power_state(
case DC_ACPI_CM_POWER_STATE_D0: case DC_ACPI_CM_POWER_STATE_D0:
dc_resource_state_construct(dc, dc->current_state); dc_resource_state_construct(dc, dc->current_state);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
dc_z10_restore(dc);
#endif
if (dc->ctx->dmub_srv) if (dc->ctx->dmub_srv)
dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv); dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
......
...@@ -2706,6 +2706,10 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, ...@@ -2706,6 +2706,10 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
return false; return false;
link->psr_settings.psr_allow_active = allow_active; link->psr_settings.psr_allow_active = allow_active;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
if (!allow_active)
dc_z10_restore(dc);
#endif
if (psr != NULL && link->psr_settings.psr_feature_enabled) { if (psr != NULL && link->psr_settings.psr_feature_enabled) {
if (force_static && psr->funcs->psr_force_static) if (force_static && psr->funcs->psr_force_static)
......
...@@ -294,6 +294,9 @@ bool dc_stream_set_cursor_attributes( ...@@ -294,6 +294,9 @@ bool dc_stream_set_cursor_attributes(
stream->cursor_attributes = *attributes; stream->cursor_attributes = *attributes;
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_DCN)
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
dc_z10_restore(dc);
#endif
/* disable idle optimizations while updating cursor */ /* disable idle optimizations while updating cursor */
if (dc->idle_optimizations_allowed) { if (dc->idle_optimizations_allowed) {
dc_allow_idle_optimizations(dc, false); dc_allow_idle_optimizations(dc, false);
...@@ -355,6 +358,9 @@ bool dc_stream_set_cursor_position( ...@@ -355,6 +358,9 @@ bool dc_stream_set_cursor_position(
dc = stream->ctx->dc; dc = stream->ctx->dc;
res_ctx = &dc->current_state->res_ctx; res_ctx = &dc->current_state->res_ctx;
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_DCN)
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
dc_z10_restore(dc);
#endif
/* disable idle optimizations if enabling cursor */ /* disable idle optimizations if enabling cursor */
if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) { if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
......
...@@ -1326,6 +1326,9 @@ void dc_hardware_release(struct dc *dc); ...@@ -1326,6 +1326,9 @@ void dc_hardware_release(struct dc *dc);
#endif #endif
bool dc_set_psr_allow_active(struct dc *dc, bool enable); bool dc_set_psr_allow_active(struct dc *dc, bool enable);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
void dc_z10_restore(struct dc *dc);
#endif
bool dc_enable_dmub_notifications(struct dc *dc); bool dc_enable_dmub_notifications(struct dc *dc);
......
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