Skip to content

L
linux
Commit bd485d27 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Merge tag 'rproc-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux 

Pull remoteproc updates from Bjorn Andersson:
 "The remoteproc repo is moved to a new path on git.kernel.org, to allow
  Mathieu push access to the branches.

  Support for the Mediatek MT8195 SCP was added, the related DeviceTree
  binding was converted to YAML and MT8192 SCP was documented as well.

  Amlogic Meson6, Meson8, Meson8b and Meson8m2 has an ARC core to aid in
  resuming the system after suspend, a new remoteproc driver for booting
  this core is introduced.

  A new driver to support the DSP processor found on NXP i.MX8QM,
  i.MX8QXP, i.MX8MP and i.MX8ULP is added.

  The Qualcomm modem and TrustZone based remoteproc drivers gains
  support for the modem in SC7280 and MSM8996 gains support for a
  missing power-domain.

  Throughout the Qualcomm drivers, the support for informing the
  always-on power coprocessor about the state of each remoteproc is
  reworked to avoid complications related to our use of genpd and the
  system suspend state.

  Lastly a number of small fixes are found throughout the drivers and
  framework"

* tag 'rproc-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (39 commits)
  remoteproc: Remove vdev_to_rvdev and vdev_to_rproc from remoteproc API
  remoteproc: omap_remoteproc: simplify getting .driver_data
  remoteproc: qcom_q6v5_mss: Use devm_platform_ioremap_resource_byname() to simplify code
  remoteproc: Fix a memory leak in an error handling path in 'rproc_handle_vdev()'
  remoteproc: Fix spelling mistake "atleast" -> "at least"
  remoteproc: imx_dsp_rproc: mark PM functions as __maybe_unused
  remoteproc: imx_dsp_rproc: Correct the comment style of copyright
  dt-bindings: dsp: fsl: Update binding document for remote proc driver
  remoteproc: imx_dsp_rproc: Add remoteproc driver for DSP on i.MX
  remoteproc: imx_rproc: Add IMX_RPROC_SCU_API method
  remoteproc: imx_rproc: Move common structure to header file
  rpmsg: char: Remove useless include
  remoteproc: meson-mx-ao-arc: fix a bit test
  remoteproc: mss: q6v5-mss: Add modem support on SC7280
  dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding
  remoteproc: qcom: pas: Add SC7280 Modem support
  dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support
  remoteproc: qcom: pas: Use the same init resources for MSM8996 and MSM8998
  MAINTAINERS: Update remoteproc repo url
  dt-bindings: remoteproc: k3-dsp: Cleanup SoC compatible from DT example
  ...
parents becc1fb4 99555489
Hide whitespace changes
Inline Side-by-side
Showing with 2377 additions and 303 deletions
Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
View file @ bd485d27
......@@ -8,6 +8,7 @@ title: NXP i.MX8 DSP core
maintainers:
- Daniel Baluta <daniel.baluta@nxp.com>
- Shengjiu Wang <shengjiu.wang@nxp.com>
description: |
Some boards from i.MX8 family contain a DSP core used for
......@@ -19,6 +20,10 @@ properties:
- fsl,imx8qxp-dsp
- fsl,imx8qm-dsp
- fsl,imx8mp-dsp
- fsl,imx8qxp-hifi4
- fsl,imx8qm-hifi4
- fsl,imx8mp-hifi4
- fsl,imx8ulp-hifi4
reg:
maxItems: 1
......@@ -28,37 +33,53 @@ properties:
- description: ipg clock
- description: ocram clock
- description: core clock
- description: debug interface clock
- description: message unit clock
minItems: 3
clock-names:
items:
- const: ipg
- const: ocram
- const: core
- const: debug
- const: mu
minItems: 3
power-domains:
description:
List of phandle and PM domain specifier as documented in
Documentation/devicetree/bindings/power/power_domain.txt
minItems: 1
maxItems: 4
mboxes:
description:
List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB
(see mailbox/fsl,mu.txt)
minItems: 3
maxItems: 4
mbox-names:
items:
- const: txdb0
- const: txdb1
- const: rxdb0
- const: rxdb1
minItems: 3
maxItems: 4
memory-region:
description:
phandle to a node describing reserved memory (System RAM memory)
used by DSP (see bindings/reserved-memory/reserved-memory.txt)
maxItems: 1
minItems: 1
maxItems: 4
firmware-name:
description: |
Default name of the firmware to load to the remote processor.
fsl,dsp-ctrl:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to syscon block which provide access for processor enablement
required:
- compatible
......@@ -70,6 +91,58 @@ required:
- mbox-names
- memory-region
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-dsp
- fsl,imx8qm-dsp
- fsl,imx8qxp-hifi4
- fsl,imx8qm-hifi4
then:
properties:
power-domains:
minItems: 4
else:
properties:
power-domains:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-hifi4
- fsl,imx8qm-hifi4
- fsl,imx8mp-hifi4
- fsl,imx8ulp-hifi4
then:
properties:
memory-region:
minItems: 4
mboxes:
maxItems: 3
mbox-names:
items:
- const: tx
- const: rx
- const: rxdb
else:
properties:
memory-region:
maxItems: 1
mboxes:
minItems: 4
mbox-names:
items:
- const: txdb0
- const: txdb1
- const: rxdb0
- const: rxdb1
additionalProperties: false
examples:
......@@ -91,3 +164,41 @@ examples:
mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
memory-region = <&dsp_reserved>;
};
- |
#include <dt-bindings/clock/imx8mp-clock.h>
dsp_reserved: dsp@92400000 {
reg = <0x92400000 0x1000000>;
no-map;
};
dsp_vdev0vring0: vdev0vring0@942f0000 {
reg = <0x942f0000 0x8000>;
no-map;
};
dsp_vdev0vring1: vdev0vring1@942f8000 {
reg = <0x942f8000 0x8000>;
no-map;
};
dsp_vdev0buffer: vdev0buffer@94300000 {
compatible = "shared-dma-pool";
reg = <0x94300000 0x100000>;
no-map;
};
dsp: dsp@3b6e8000 {
compatible = "fsl,imx8mp-hifi4";
reg = <0x3b6e8000 0x88000>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;
clock-names = "ipg", "ocram", "core", "debug";
firmware-name = "imx/dsp/hifi4.bin";
power-domains = <&audiomix_pd>;
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu2 0 0>,
<&mu2 1 0>,
<&mu2 3 0>;
memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
<&dsp_vdev0vring1>, <&dsp_reserved>;
fsl,dsp-ctrl = <&audio_blk_ctrl>;
};
Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml 0 → 100644
View file @ bd485d27
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/remoteproc/amlogic,meson-mx-ao-arc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson AO ARC Remote Processor bindings
description:
Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC core
controller for always-on operations, typically used for managing
system suspend. Meson6 and older use a ARC core based on the ARCv1
ISA, while Meson8, Meson8b and Meson8m2 use an ARC EM4 (ARCv2 ISA)
core.
maintainers:
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
properties:
compatible:
items:
- enum:
- amlogic,meson8-ao-arc
- amlogic,meson8b-ao-arc
- const: amlogic,meson-mx-ao-arc
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description:
The name of the firmware which should be loaded for this remote
processor.
reg:
description:
Address ranges of the remap and CPU control addresses for the
remote processor.
minItems: 2
reg-names:
items:
- const: remap
- const: cpu
resets:
minItems: 1
clocks:
minItems: 1
sram:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandles to a reserved SRAM region which is used as the memory of
the ARC core. The region should be defined as child nodes of the
AHB SRAM node as per the generic bindings in
Documentation/devicetree/bindings/sram/sram.yaml
amlogic,secbus2:
$ref: /schemas/types.yaml#/definitions/phandle
description:
A phandle to the SECBUS2 region which contains some configuration
bits of this remote processor
required:
- compatible
- reg
- reg-names
- resets
- clocks
- sram
- amlogic,secbus2
additionalProperties: false
examples:
- |
remoteproc@1c {
compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
reg = <0x1c 0x8>, <0x38 0x8>;
reg-names = "remap", "cpu";
resets = <&media_cpu_reset>;
clocks = <&media_cpu_clock>;
sram = <&ahb_sram_ao_arc>;
amlogic,secbus2 = <&secbus2>;
};
...
Documentation/devicetree/bindings/remoteproc/mtk,scp.txt deleted 100644 → 0
View file @ becc1fb4
Mediatek SCP Bindings
----------------------------------------
This binding provides support for ARM Cortex M4 Co-processor found on some
Mediatek SoCs.
Required properties:
- compatible Should be "mediatek,mt8183-scp"
- reg Should contain the address ranges for memory regions:
SRAM, CFG, and L1TCM.
- reg-names Contains the corresponding names for the memory regions:
"sram", "cfg", and "l1tcm".
- clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
- clock-names Contains the corresponding name for the clock. This
should be named "main".
Subnodes
--------
Subnodes of the SCP represent rpmsg devices. The names of the devices are not
important. The properties of these nodes are defined by the individual bindings
for the rpmsg devices - but must contain the following property:
- mtk,rpmsg-name Contains the name for the rpmsg device. Used to match
the subnode to rpmsg device announced by SCP.
Example:
scp: scp@10500000 {
compatible = "mediatek,mt8183-scp";
reg = <0 0x10500000 0 0x80000>,
<0 0x105c0000 0 0x5000>;
reg-names = "sram", "cfg";
clocks = <&infracfg CLK_INFRA_SCPSYS>;
clock-names = "main";
};
Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml 0 → 100644
View file @ bd485d27
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/mtk,scp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek SCP Bindings
maintainers:
- Tinghan Shen <tinghan.shen@mediatek.com>
description:
This binding provides support for ARM Cortex M4 Co-processor found on some
Mediatek SoCs.
properties:
compatible:
enum:
- mediatek,mt8183-scp
- mediatek,mt8192-scp
- mediatek,mt8195-scp
reg:
description:
Should contain the address ranges for memory regions SRAM, CFG, and
L1TCM.
maxItems: 3
reg-names:
items:
- const: sram
- const: cfg
- const: l1tcm
clocks:
description:
Clock for co-processor (see ../clock/clock-bindings.txt).
Required by mt8183 and mt8192.
maxItems: 1
clock-names:
const: main
required:
- compatible
- reg
- reg-names
if:
properties:
compatible:
enum:
- mediatek,mt8183-scp
- mediatek,mt8192-scp
then:
required:
- clocks
- clock-names
additionalProperties:
type: object
description:
Subnodes of the SCP represent rpmsg devices. The names of the devices
are not important. The properties of these nodes are defined by the
individual bindings for the rpmsg devices.
properties:
mediatek,rpmsg-name:
$ref: /schemas/types.yaml#/definitions/string-array
description:
Contains the name for the rpmsg device. Used to match
the subnode to rpmsg device announced by SCP.
required:
- mediatek,rpmsg-name
examples:
- |
#include <dt-bindings/clock/mt8183-clk.h>
scp@10500000 {
compatible = "mediatek,mt8183-scp";
reg = <0x10500000 0x80000>,
<0x10700000 0x8000>,
<0x10720000 0xe0000>;
reg-names = "sram", "cfg", "l1tcm";
clocks = <&infracfg CLK_INFRA_SCPSYS>;
clock-names = "main";
cros_ec {
mediatek,rpmsg-name = "cros-ec-rpmsg";
};
};
Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
View file @ bd485d27
......@@ -25,6 +25,7 @@ properties:
- qcom,qcs404-cdsp-pas
- qcom,qcs404-wcss-pas
- qcom,sc7180-mpss-pas
- qcom,sc7280-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
......@@ -93,6 +94,10 @@ properties:
maxItems: 1
description: Reference to the reserved-memory for the Hexagon core
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
......@@ -147,6 +152,7 @@ allOf:
- qcom,msm8998-adsp-pas
- qcom,qcs404-adsp-pas
- qcom,qcs404-wcss-pas
- qcom,sc7280-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
......@@ -292,6 +298,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mpss-pas
- qcom,sc7280-mpss-pas
- qcom,sc8180x-mpss-pas
- qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
......@@ -369,13 +376,11 @@ allOf:
properties:
power-domains:
items:
- description: Load State power domain
- description: CX power domain
- description: MX power domain
- description: MSS power domain
power-domain-names:
items:
- const: load_state
- const: cx
- const: mx
- const: mss
......@@ -391,39 +396,17 @@ allOf:
properties:
power-domains:
items:
- description: Load State power domain
- description: CX power domain
power-domain-names:
items:
- const: load_state
- const: cx
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7280-mpss-pas
- qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas
then:
properties:
power-domains:
items:
- description: Load State power domain
- description: CX power domain
- description: MSS power domain
power-domain-names:
items:
- const: load_state
- const: cx
- const: mss
- if:
properties:
compatible:
contains:
enum:
- qcom,sdx55-mpss-pas
then:
properties:
power-domains:
......@@ -451,12 +434,10 @@ allOf:
properties:
power-domains:
items:
- description: Load State power domain
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- const: load_state
- const: lcx
- const: lmx
......@@ -470,12 +451,10 @@ allOf:
properties:
power-domains:
items:
- description: Load State power domain
- description: CX power domain
- description: MXC power domain
power-domain-names:
items:
- const: load_state
- const: cx
- const: mxc
......@@ -500,6 +479,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mpss-pas
- qcom,sc7280-mpss-pas
then:
properties:
resets:
......@@ -511,6 +491,25 @@ allOf:
- const: mss_restart
- const: pdc_reset
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8974-adsp-pil
- qcom,msm8996-adsp-pil
- qcom,msm8996-slpi-pil
- qcom,msm8998-adsp-pas
- qcom,msm8998-slpi-pas
- qcom,qcs404-adsp-pas
- qcom,qcs404-cdsp-pas
- qcom,qcs404-wcss-pas
- qcom,sdm660-adsp-pas
- qcom,sdx55-mpss-pas
then:
properties:
qcom,qmp: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
......
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
View file @ bd485d27
......@@ -15,6 +15,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8996-mss-pil"
"qcom,msm8998-mss-pil"
"qcom,sc7180-mss-pil"
"qcom,sc7280-mss-pil"
"qcom,sdm845-mss-pil"
- reg:
......@@ -47,6 +48,7 @@ on the Qualcomm Hexagon core.
qcom,msm8996-mss-pil:
qcom,msm8998-mss-pil:
qcom,sc7180-mss-pil:
qcom,sc7280-mss-pil:
qcom,sdm845-mss-pil:
must be "wdog", "fatal", "ready", "handover", "stop-ack",
"shutdown-ack"
......@@ -87,6 +89,8 @@ on the Qualcomm Hexagon core.
qcom,sc7180-mss-pil:
must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi",
"nav"
qcom,sc7280-mss-pil:
must be "iface", "xo", "snoc_axi", "offline", "pka"
qcom,sdm845-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng"
......@@ -98,7 +102,7 @@ on the Qualcomm Hexagon core.
reference to the list of 3 reset-controllers for the
wcss sub-system
reference to the list of 2 reset-controllers for the modem
sub-system on SC7180, SDM845 SoCs
sub-system on SC7180, SC7280, SDM845 SoCs
- reset-names:
Usage: required
......@@ -107,7 +111,7 @@ on the Qualcomm Hexagon core.
must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss sub-system
must be "mss_restart", "pdc_reset" for the modem
sub-system on SC7180, SDM845 SoCs
sub-system on SC7180, SC7280, SDM845 SoCs
For devices where the mba and mpss sub-nodes are not specified, mba/mpss region
should be referenced as follows:
......@@ -173,8 +177,16 @@ For the compatible string below the following supplies are required:
qcom,msm8998-mss-pil:
must be "cx", "mx"
qcom,sc7180-mss-pil:
must be "cx", "mx", "mss"
qcom,sc7280-mss-pil:
must be "cx", "mss"
qcom,sdm845-mss-pil:
must be "cx", "mx", "mss", "load_state"
must be "cx", "mx", "mss"
- qcom,qmp:
Usage: optional
Value type: <phandle>
Definition: reference to the AOSS side-channel message RAM.
- qcom,smem-states:
Usage: required
......@@ -193,6 +205,9 @@ For the compatible string below the following supplies are required:
Definition: a phandle reference to a syscon representing TCSR followed
by the three offsets within syscon for q6, modem and nc
halt registers.
a phandle reference to a syscon representing TCSR followed
by the four offsets within syscon for q6, modem, nc and vq6
halt registers on SC7280 SoCs.
For the compatible strings below the following phandle references are required:
"qcom,sc7180-mss-pil"
......@@ -203,6 +218,24 @@ For the compatible strings below the following phandle references are required:
by the offset within syscon for conn_box_spare0 register
used by the modem sub-system running on SC7180 SoC.
For the compatible strings below the following phandle references are required:
"qcom,sc7280-mss-pil"
- qcom,ext-regs:
Usage: required
Value type: <prop-encoded-array>
Definition: two phandle references to syscons representing TCSR_REG and
TCSR register space followed by the two offsets within the syscon
to force_clk_en/rscc_disable and axim1_clk_off/crypto_clk_off
registers respectively.
- qcom,qaccept-regs:
Usage: required
Value type: <prop-encoded-array>
Definition: a phandle reference to a syscon representing TCSR followed
by the three offsets within syscon for mdm, cx and axi
qaccept registers used by the modem sub-system running on
SC7280 SoC.
The Hexagon node must contain iommus property as described in ../iommu/iommu.txt
on platforms which do not have TrustZone.
......
Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml
View file @ bd485d27
......@@ -133,9 +133,7 @@ unevaluatedProperties: false
examples:
- |
/ {
model = "Texas Instruments K3 J721E SoC";
compatible = "ti,j721e";
soc {
#address-cells = <2>;
#size-cells = <2>;
......
Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml
View file @ bd485d27
......@@ -230,9 +230,7 @@ additionalProperties: false
examples:
- |
/ {
model = "Texas Instruments K3 AM654 SoC";
compatible = "ti,am654-evm", "ti,am654";
soc {
#address-cells = <2>;
#size-cells = <2>;
......
MAINTAINERS
View file @ bd485d27
......@@ -16162,7 +16162,7 @@ M: Bjorn Andersson <bjorn.andersson@linaro.org>
M: Mathieu Poirier <mathieu.poirier@linaro.org>
L: linux-remoteproc@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git rproc-next
T: git https://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux.git rproc-next
F: Documentation/ABI/testing/sysfs-class-remoteproc
F: Documentation/devicetree/bindings/remoteproc/
F: Documentation/staging/remoteproc.rst
......@@ -16176,7 +16176,7 @@ M: Bjorn Andersson <bjorn.andersson@linaro.org>
M: Mathieu Poirier <mathieu.poirier@linaro.org>
L: linux-remoteproc@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git rpmsg-next
T: git https://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux.git rpmsg-next
F: Documentation/ABI/testing/sysfs-bus-rpmsg
F: Documentation/staging/rpmsg.rst
F: drivers/rpmsg/
......
drivers/remoteproc/Kconfig
View file @ bd485d27
......@@ -34,6 +34,17 @@ config IMX_REMOTEPROC
It's safe to say N here.
config IMX_DSP_REMOTEPROC
tristate "i.MX DSP remoteproc support"
depends on ARCH_MXC
depends on HAVE_ARM_SMCCC
select MAILBOX
help
Say y here to support iMX's DSP remote processors via the remote
processor framework.
It's safe to say N here.
config INGENIC_VPU_RPROC
tristate "Ingenic JZ47xx VPU remoteproc support"
depends on MIPS || COMPILE_TEST
......@@ -127,6 +138,17 @@ config KEYSTONE_REMOTEPROC
It's safe to say N here if you're not interested in the Keystone
DSPs or just want to use a bare minimum kernel.
config MESON_MX_AO_ARC_REMOTEPROC
tristate "Amlogic Meson6/8/8b/8m2 AO ARC remote processor support"
depends on HAS_IOMEM
depends on (ARM && ARCH_MESON) || COMPILE_TEST
select GENERIC_ALLOCATOR
help
Say m or y here to have support for the AO ARC remote processor
on Amlogic Meson6/Meson8/Meson8b/Meson8m2 SoCs. This is
typically used for system suspend.
If unsure say N.
config PRU_REMOTEPROC
tristate "TI PRU remoteproc support"
depends on TI_PRUSS
......@@ -154,7 +176,7 @@ config QCOM_Q6V5_ADSP
tristate "Qualcomm Technology Inc ADSP Peripheral Image Loader"
depends on OF && ARCH_QCOM
depends on QCOM_SMEM
depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
......@@ -173,7 +195,7 @@ config QCOM_Q6V5_MSS
tristate "Qualcomm Hexagon V5 self-authenticating modem subsystem support"
depends on OF && ARCH_QCOM
depends on QCOM_SMEM
depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
......@@ -192,7 +214,7 @@ config QCOM_Q6V5_PAS
tristate "Qualcomm Hexagon v5 Peripheral Authentication Service support"
depends on OF && ARCH_QCOM
depends on QCOM_SMEM
depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
......@@ -213,7 +235,7 @@ config QCOM_Q6V5_WCSS
tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
depends on OF && ARCH_QCOM
depends on QCOM_SMEM
depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
......@@ -246,7 +268,7 @@ config QCOM_SYSMON
config QCOM_WCNSS_PIL
tristate "Qualcomm WCNSS Peripheral Image Loader"
depends on OF && ARCH_QCOM
depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SMEM
depends on QCOM_SYSMON || QCOM_SYSMON=n
......
drivers/remoteproc/Makefile
View file @ bd485d27
......@@ -12,12 +12,14 @@ remoteproc-y += remoteproc_virtio.o
remoteproc-y += remoteproc_elf_loader.o
obj-$(CONFIG_REMOTEPROC_CDEV) += remoteproc_cdev.o
obj-$(CONFIG_IMX_REMOTEPROC) += imx_rproc.o
obj-$(CONFIG_IMX_DSP_REMOTEPROC) += imx_dsp_rproc.o
obj-$(CONFIG_INGENIC_VPU_RPROC) += ingenic_rproc.o
obj-$(CONFIG_MTK_SCP) += mtk_scp.o mtk_scp_ipi.o
obj-$(CONFIG_OMAP_REMOTEPROC) += omap_remoteproc.o
obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o
obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o
obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o
obj-$(CONFIG_MESON_MX_AO_ARC_REMOTEPROC)+= meson_mx_ao_arc.o
obj-$(CONFIG_PRU_REMOTEPROC) += pru_rproc.o
obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o
obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o
......
drivers/remoteproc/imx_dsp_rproc.c 0 → 100644
View file @ bd485d27
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright 2021 NXP */
#include <dt-bindings/firmware/imx/rsrc.h>
#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/firmware.h>
#include <linux/firmware/imx/sci.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mailbox_client.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_reserved_mem.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/remoteproc.h>
#include <linux/slab.h>
#include "imx_rproc.h"
#include "remoteproc_elf_helpers.h"
#include "remoteproc_internal.h"
#define DSP_RPROC_CLK_MAX 5
#define REMOTE_IS_READY BIT(0)
#define REMOTE_READY_WAIT_MAX_RETRIES 500
/* att flags */
/* DSP own area */
#define ATT_OWN BIT(31)
/* DSP instruction area */
#define ATT_IRAM BIT(30)
/* Definitions for i.MX8MP */
/* DAP registers */
#define IMX8M_DAP_DEBUG 0x28800000
#define IMX8M_DAP_DEBUG_SIZE (64 * 1024)
#define IMX8M_DAP_PWRCTL (0x4000 + 0x3020)
#define IMX8M_PWRCTL_CORERESET BIT(16)
/* DSP audio mix registers */
#define IMX8M_AudioDSP_REG0 0x100
#define IMX8M_AudioDSP_REG1 0x104
#define IMX8M_AudioDSP_REG2 0x108
#define IMX8M_AudioDSP_REG3 0x10c
#define IMX8M_AudioDSP_REG2_RUNSTALL BIT(5)
#define IMX8M_AudioDSP_REG2_PWAITMODE BIT(1)
/* Definitions for i.MX8ULP */
#define IMX8ULP_SIM_LPAV_REG_SYSCTRL0 0x8
#define IMX8ULP_SYSCTRL0_DSP_DBG_RST BIT(25)
#define IMX8ULP_SYSCTRL0_DSP_PLAT_CLK_EN BIT(19)
#define IMX8ULP_SYSCTRL0_DSP_PBCLK_EN BIT(18)
#define IMX8ULP_SYSCTRL0_DSP_CLK_EN BIT(17)
#define IMX8ULP_SYSCTRL0_DSP_RST BIT(16)
#define IMX8ULP_SYSCTRL0_DSP_OCD_HALT BIT(14)
#define IMX8ULP_SYSCTRL0_DSP_STALL BIT(13)
#define IMX8ULP_SIP_HIFI_XRDC 0xc200000e
/*
* enum - Predefined Mailbox Messages
*
* @RP_MBOX_SUSPEND_SYSTEM: system suspend request for the remote processor
*
* @RP_MBOX_SUSPEND_ACK: successful response from remote processor for a
* suspend request
*
* @RP_MBOX_RESUME_SYSTEM: system resume request for the remote processor
*
* @RP_MBOX_RESUME_ACK: successful response from remote processor for a
* resume request
*/
enum imx_dsp_rp_mbox_messages {
RP_MBOX_SUSPEND_SYSTEM = 0xFF11,
RP_MBOX_SUSPEND_ACK = 0xFF12,
RP_MBOX_RESUME_SYSTEM = 0xFF13,
RP_MBOX_RESUME_ACK = 0xFF14,
};
/**
* struct imx_dsp_rproc - DSP remote processor state
* @regmap: regmap handler
* @rproc: rproc handler
* @dsp_dcfg: device configuration pointer
* @clks: clocks needed by this device
* @cl: mailbox client to request the mailbox channel
* @cl_rxdb: mailbox client to request the mailbox channel for doorbell
* @tx_ch: mailbox tx channel handle
* @rx_ch: mailbox rx channel handle
* @rxdb_ch: mailbox rx doorbell channel handle
* @pd_dev: power domain device
* @pd_dev_link: power domain device link
* @ipc_handle: System Control Unit ipc handle
* @rproc_work: work for processing virtio interrupts
* @pm_comp: completion primitive to sync for suspend response
* @num_domains: power domain number
* @flags: control flags
*/
struct imx_dsp_rproc {
struct regmap *regmap;
struct rproc *rproc;
const struct imx_dsp_rproc_dcfg *dsp_dcfg;
struct clk_bulk_data clks[DSP_RPROC_CLK_MAX];
struct mbox_client cl;
struct mbox_client cl_rxdb;
struct mbox_chan *tx_ch;
struct mbox_chan *rx_ch;
struct mbox_chan *rxdb_ch;
struct device **pd_dev;
struct device_link **pd_dev_link;
struct imx_sc_ipc *ipc_handle;
struct work_struct rproc_work;
struct completion pm_comp;
int num_domains;
u32 flags;
};
/**
* struct imx_dsp_rproc_dcfg - DSP remote processor configuration
* @dcfg: imx_rproc_dcfg handler
* @reset: reset callback function
*/
struct imx_dsp_rproc_dcfg {
const struct imx_rproc_dcfg *dcfg;
int (*reset)(struct imx_dsp_rproc *priv);
};
static const struct imx_rproc_att imx_dsp_rproc_att_imx8qm[] = {
/* dev addr , sys addr , size , flags */
{ 0x596e8000, 0x556e8000, 0x00008000, ATT_OWN },
{ 0x596f0000, 0x556f0000, 0x00008000, ATT_OWN },
{ 0x596f8000, 0x556f8000, 0x00000800, ATT_OWN | ATT_IRAM},
{ 0x55700000, 0x55700000, 0x00070000, ATT_OWN },
/* DDR (Data) */
{ 0x80000000, 0x80000000, 0x60000000, 0},
};
static const struct imx_rproc_att imx_dsp_rproc_att_imx8qxp[] = {
/* dev addr , sys addr , size , flags */
{ 0x596e8000, 0x596e8000, 0x00008000, ATT_OWN },
{ 0x596f0000, 0x596f0000, 0x00008000, ATT_OWN },
{ 0x596f8000, 0x596f8000, 0x00000800, ATT_OWN | ATT_IRAM},
{ 0x59700000, 0x59700000, 0x00070000, ATT_OWN },
/* DDR (Data) */
{ 0x80000000, 0x80000000, 0x60000000, 0},
};
static const struct imx_rproc_att imx_dsp_rproc_att_imx8mp[] = {
/* dev addr , sys addr , size , flags */
{ 0x3b6e8000, 0x3b6e8000, 0x00008000, ATT_OWN },
{ 0x3b6f0000, 0x3b6f0000, 0x00008000, ATT_OWN },
{ 0x3b6f8000, 0x3b6f8000, 0x00000800, ATT_OWN | ATT_IRAM},
{ 0x3b700000, 0x3b700000, 0x00040000, ATT_OWN },
/* DDR (Data) */
{ 0x40000000, 0x40000000, 0x80000000, 0},
};
static const struct imx_rproc_att imx_dsp_rproc_att_imx8ulp[] = {
/* dev addr , sys addr , size , flags */
{ 0x21170000, 0x21170000, 0x00010000, ATT_OWN | ATT_IRAM},
{ 0x21180000, 0x21180000, 0x00010000, ATT_OWN },
/* DDR (Data) */
{ 0x0c000000, 0x80000000, 0x10000000, 0},
{ 0x30000000, 0x90000000, 0x10000000, 0},
};
/* Reset function for DSP on i.MX8MP */
static int imx8mp_dsp_reset(struct imx_dsp_rproc *priv)
{
void __iomem *dap = ioremap_wc(IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE);
int pwrctl;
/* Put DSP into reset and stall */
pwrctl = readl(dap + IMX8M_DAP_PWRCTL);
pwrctl |= IMX8M_PWRCTL_CORERESET;
writel(pwrctl, dap + IMX8M_DAP_PWRCTL);
/* Keep reset asserted for 10 cycles */
usleep_range(1, 2);
regmap_update_bits(priv->regmap, IMX8M_AudioDSP_REG2,
IMX8M_AudioDSP_REG2_RUNSTALL,
IMX8M_AudioDSP_REG2_RUNSTALL);
/* Take the DSP out of reset and keep stalled for FW loading */
pwrctl = readl(dap + IMX8M_DAP_PWRCTL);
pwrctl &= ~IMX8M_PWRCTL_CORERESET;
writel(pwrctl, dap + IMX8M_DAP_PWRCTL);
iounmap(dap);
return 0;
}
/* Reset function for DSP on i.MX8ULP */
static int imx8ulp_dsp_reset(struct imx_dsp_rproc *priv)
{
struct arm_smccc_res res;
/* Put DSP into reset and stall */
regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
IMX8ULP_SYSCTRL0_DSP_RST, IMX8ULP_SYSCTRL0_DSP_RST);
regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
IMX8ULP_SYSCTRL0_DSP_STALL,
IMX8ULP_SYSCTRL0_DSP_STALL);
/* Configure resources of DSP through TFA */
arm_smccc_smc(IMX8ULP_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &res);
/* Take the DSP out of reset and keep stalled for FW loading */
regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
IMX8ULP_SYSCTRL0_DSP_RST, 0);
regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
IMX8ULP_SYSCTRL0_DSP_DBG_RST, 0);
return 0;
}
/* Specific configuration for i.MX8MP */
static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8mp = {
.src_reg = IMX8M_AudioDSP_REG2,
.src_mask = IMX8M_AudioDSP_REG2_RUNSTALL,
.src_start = 0,
.src_stop = IMX8M_AudioDSP_REG2_RUNSTALL,
.att = imx_dsp_rproc_att_imx8mp,
.att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8mp),
.method = IMX_RPROC_MMIO,
};
static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8mp = {
.dcfg = &dsp_rproc_cfg_imx8mp,
.reset = imx8mp_dsp_reset,
};
/* Specific configuration for i.MX8ULP */
static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8ulp = {
.src_reg = IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
.src_mask = IMX8ULP_SYSCTRL0_DSP_STALL,
.src_start = 0,
.src_stop = IMX8ULP_SYSCTRL0_DSP_STALL,
.att = imx_dsp_rproc_att_imx8ulp,
.att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8ulp),
.method = IMX_RPROC_MMIO,
};
static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8ulp = {
.dcfg = &dsp_rproc_cfg_imx8ulp,
.reset = imx8ulp_dsp_reset,
};
/* Specific configuration for i.MX8QXP */
static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qxp = {
.att = imx_dsp_rproc_att_imx8qxp,
.att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qxp),
.method = IMX_RPROC_SCU_API,
};
static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qxp = {
.dcfg = &dsp_rproc_cfg_imx8qxp,
};
/* Specific configuration for i.MX8QM */
static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qm = {
.att = imx_dsp_rproc_att_imx8qm,
.att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qm),
.method = IMX_RPROC_SCU_API,
};
static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qm = {
.dcfg = &dsp_rproc_cfg_imx8qm,
};
static int imx_dsp_rproc_ready(struct rproc *rproc)
{
struct imx_dsp_rproc *priv = rproc->priv;
int i;
if (!priv->rxdb_ch)
return 0;
for (i = 0; i < REMOTE_READY_WAIT_MAX_RETRIES; i++) {
if (priv->flags & REMOTE_IS_READY)
return 0;
usleep_range(100, 200);
}
return -ETIMEDOUT;
}
/*
* Start function for rproc_ops
*
* There is a handshake for start procedure: when DSP starts, it
* will send a doorbell message to this driver, then the
* REMOTE_IS_READY flags is set, then driver will kick
* a message to DSP.
*/
static int imx_dsp_rproc_start(struct rproc *rproc)
{
struct imx_dsp_rproc *priv = rproc->priv;
const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
struct device *dev = rproc->dev.parent;
int ret;
switch (dcfg->method) {
case IMX_RPROC_MMIO:
ret = regmap_update_bits(priv->regmap,
dcfg->src_reg,
dcfg->src_mask,
dcfg->src_start);
break;
case IMX_RPROC_SCU_API:
ret = imx_sc_pm_cpu_start(priv->ipc_handle,
IMX_SC_R_DSP,
true,
rproc->bootaddr);
break;
default:
return -EOPNOTSUPP;
}
if (ret)
dev_err(dev, "Failed to enable remote core!\n");
else
ret = imx_dsp_rproc_ready(rproc);
return ret;
}
/*
* Stop function for rproc_ops
* It clears the REMOTE_IS_READY flags
*/
static int imx_dsp_rproc_stop(struct rproc *rproc)
{
struct imx_dsp_rproc *priv = rproc->priv;
const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
struct device *dev = rproc->dev.parent;
int ret = 0;
/* Make sure work is finished */
flush_work(&priv->rproc_work);
if (rproc->state == RPROC_CRASHED) {
priv->flags &= ~REMOTE_IS_READY;
return 0;
}
switch (dcfg->method) {
case IMX_RPROC_MMIO:
ret = regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask,
dcfg->src_stop);
break;
case IMX_RPROC_SCU_API:
ret = imx_sc_pm_cpu_start(priv->ipc_handle,
IMX_SC_R_DSP,
false,
rproc->bootaddr);
break;
default:
return -EOPNOTSUPP;
}
if (ret)
dev_err(dev, "Failed to stop remote core\n");
else
priv->flags &= ~REMOTE_IS_READY;
return ret;
}
/**
* imx_dsp_rproc_sys_to_da() - internal memory translation helper
* @priv: private data pointer
* @sys: system address (DDR address)
* @len: length of the memory buffer
* @da: device address to translate
*
* Convert system address (DDR address) to device address (DSP)
* for there may be memory remap for device.
*/
static int imx_dsp_rproc_sys_to_da(struct imx_dsp_rproc *priv, u64 sys,
size_t len, u64 *da)
{
const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
int i;
/* Parse address translation table */
for (i = 0; i < dcfg->att_size; i++) {
const struct imx_rproc_att *att = &dcfg->att[i];
if (sys >= att->sa && sys + len <= att->sa + att->size) {
unsigned int offset = sys - att->sa;
*da = att->da + offset;
return 0;
}
}
return -ENOENT;
}
/* Main virtqueue message work function
*
* This function is executed upon scheduling of the i.MX DSP remoteproc
* driver's workqueue. The workqueue is scheduled by the mailbox rx
* handler.
*
* This work function processes both the Tx and Rx virtqueue indices on
* every invocation. The rproc_vq_interrupt function can detect if there
* are new unprocessed messages or not (returns IRQ_NONE vs IRQ_HANDLED),
* but there is no need to check for these return values. The index 0
* triggering will process all pending Rx buffers, and the index 1 triggering
* will process all newly available Tx buffers and will wakeup any potentially
* blocked senders.
*
* NOTE:
* The current logic is based on an inherent design assumption of supporting
* only 2 vrings, but this can be changed if needed.
*/
static void imx_dsp_rproc_vq_work(struct work_struct *work)
{
struct imx_dsp_rproc *priv = container_of(work, struct imx_dsp_rproc,
rproc_work);
rproc_vq_interrupt(priv->rproc, 0);
rproc_vq_interrupt(priv->rproc, 1);
}
/**
* imx_dsp_rproc_rx_tx_callback() - inbound mailbox message handler
* @cl: mailbox client pointer used for requesting the mailbox channel
* @data: mailbox payload
*
* This handler is invoked by mailbox driver whenever a mailbox
* message is received. Usually, the SUSPEND and RESUME related messages
* are handled in this function, other messages are handled by remoteproc core
*/
static void imx_dsp_rproc_rx_tx_callback(struct mbox_client *cl, void *data)
{
struct rproc *rproc = dev_get_drvdata(cl->dev);
struct imx_dsp_rproc *priv = rproc->priv;
struct device *dev = rproc->dev.parent;
u32 message = (u32)(*(u32 *)data);
dev_dbg(dev, "mbox msg: 0x%x\n", message);
switch (message) {
case RP_MBOX_SUSPEND_ACK:
complete(&priv->pm_comp);
break;
case RP_MBOX_RESUME_ACK:
complete(&priv->pm_comp);
break;
default:
schedule_work(&priv->rproc_work);
break;
}
}
/**
* imx_dsp_rproc_rxdb_callback() - inbound mailbox message handler
* @cl: mailbox client pointer used for requesting the mailbox channel
* @data: mailbox payload
*
* For doorbell, there is no message specified, just set REMOTE_IS_READY
* flag.
*/
static void imx_dsp_rproc_rxdb_callback(struct mbox_client *cl, void *data)
{
struct rproc *rproc = dev_get_drvdata(cl->dev);
struct imx_dsp_rproc *priv = rproc->priv;
/* Remote is ready after firmware is loaded and running */
priv->flags |= REMOTE_IS_READY;
}
/**
* imx_dsp_rproc_mbox_init() - request mailbox channels
* @priv: private data pointer
*
* Request three mailbox channels (tx, rx, rxdb).
*/
static int imx_dsp_rproc_mbox_init(struct imx_dsp_rproc *priv)
{
struct device *dev = priv->rproc->dev.parent;
struct mbox_client *cl;
int ret;
if (!of_get_property(dev->of_node, "mbox-names", NULL))
return 0;
cl = &priv->cl;
cl->dev = dev;
cl->tx_block = true;
cl->tx_tout = 100;
cl->knows_txdone = false;
cl->rx_callback = imx_dsp_rproc_rx_tx_callback;
/* Channel for sending message */
priv->tx_ch = mbox_request_channel_byname(cl, "tx");
if (IS_ERR(priv->tx_ch)) {
ret = PTR_ERR(priv->tx_ch);
dev_dbg(cl->dev, "failed to request tx mailbox channel: %d\n",
ret);
goto err_out;
}
/* Channel for receiving message */
priv->rx_ch = mbox_request_channel_byname(cl, "rx");
if (IS_ERR(priv->rx_ch)) {
ret = PTR_ERR(priv->rx_ch);
dev_dbg(cl->dev, "failed to request rx mailbox channel: %d\n",
ret);
goto err_out;
}
cl = &priv->cl_rxdb;
cl->dev = dev;
cl->rx_callback = imx_dsp_rproc_rxdb_callback;
/*
* RX door bell is used to receive the ready signal from remote
* after firmware loaded.
*/
priv->rxdb_ch = mbox_request_channel_byname(cl, "rxdb");
if (IS_ERR(priv->rxdb_ch)) {
ret = PTR_ERR(priv->rxdb_ch);
dev_dbg(cl->dev, "failed to request mbox chan rxdb, ret %d\n",
ret);
goto err_out;
}
return 0;
err_out:
if (!IS_ERR(priv->tx_ch))
mbox_free_channel(priv->tx_ch);
if (!IS_ERR(priv->rx_ch))
mbox_free_channel(priv->rx_ch);
if (!IS_ERR(priv->rxdb_ch))
mbox_free_channel(priv->rxdb_ch);
return ret;
}
static void imx_dsp_rproc_free_mbox(struct imx_dsp_rproc *priv)
{
mbox_free_channel(priv->tx_ch);
mbox_free_channel(priv->rx_ch);
mbox_free_channel(priv->rxdb_ch);
}
/**
* imx_dsp_rproc_add_carveout() - request mailbox channels
* @priv: private data pointer
*
* This function registers specified memory entry in @rproc carveouts list
* The carveouts can help to mapping the memory address for DSP.
*/
static int imx_dsp_rproc_add_carveout(struct imx_dsp_rproc *priv)
{
const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
struct rproc *rproc = priv->rproc;
struct device *dev = rproc->dev.parent;
struct device_node *np = dev->of_node;
struct of_phandle_iterator it;
struct rproc_mem_entry *mem;
struct reserved_mem *rmem;
void __iomem *cpu_addr;
int a;
u64 da;
/* Remap required addresses */
for (a = 0; a < dcfg->att_size; a++) {
const struct imx_rproc_att *att = &dcfg->att[a];
if (!(att->flags & ATT_OWN))
continue;
if (imx_dsp_rproc_sys_to_da(priv, att->sa, att->size, &da))
return -EINVAL;
cpu_addr = devm_ioremap_wc(dev, att->sa, att->size);
if (!cpu_addr) {
dev_err(dev, "failed to map memory %p\n", &att->sa);
return -ENOMEM;
}
/* Register memory region */
mem = rproc_mem_entry_init(dev, cpu_addr, (dma_addr_t)att->sa,
att->size, da, NULL, NULL, "dsp_mem");
if (mem)
rproc_coredump_add_segment(rproc, da, att->size);
else
return -ENOMEM;
rproc_add_carveout(rproc, mem);
}
of_phandle_iterator_init(&it, np, "memory-region", NULL, 0);
while (of_phandle_iterator_next(&it) == 0) {
/*
* Ignore the first memory region which will be used vdev buffer.
* No need to do extra handlings, rproc_add_virtio_dev will handle it.
*/
if (!strcmp(it.node->name, "vdev0buffer"))
continue;
rmem = of_reserved_mem_lookup(it.node);
if (!rmem) {
dev_err(dev, "unable to acquire memory-region\n");
return -EINVAL;
}
if (imx_dsp_rproc_sys_to_da(priv, rmem->base, rmem->size, &da))
return -EINVAL;
cpu_addr = devm_ioremap_wc(dev, rmem->base, rmem->size);
if (!cpu_addr) {
dev_err(dev, "failed to map memory %p\n", &rmem->base);
return -ENOMEM;
}
/* Register memory region */
mem = rproc_mem_entry_init(dev, cpu_addr, (dma_addr_t)rmem->base,
rmem->size, da, NULL, NULL, it.node->name);
if (mem)
rproc_coredump_add_segment(rproc, da, rmem->size);
else
return -ENOMEM;
rproc_add_carveout(rproc, mem);
}
return 0;
}
/**
* imx_dsp_rproc_elf_load_segments() - load firmware segments to memory
* @rproc: remote processor which will be booted using these fw segments
* @fw: the ELF firmware image
*
* This function specially checks if memsz is zero or not, otherwise it
* is mostly same as rproc_elf_load_segments().
*/
static int imx_dsp_rproc_elf_load_segments(struct rproc *rproc,
const struct firmware *fw)
{
struct device *dev = &rproc->dev;
u8 class = fw_elf_get_class(fw);
u32 elf_phdr_get_size = elf_size_of_phdr(class);
const u8 *elf_data = fw->data;
const void *ehdr, *phdr;
int i, ret = 0;
u16 phnum;
ehdr = elf_data;
phnum = elf_hdr_get_e_phnum(class, ehdr);
phdr = elf_data + elf_hdr_get_e_phoff(class, ehdr);
/* go through the available ELF segments */
for (i = 0; i < phnum; i++, phdr += elf_phdr_get_size) {
u64 da = elf_phdr_get_p_paddr(class, phdr);
u64 memsz = elf_phdr_get_p_memsz(class, phdr);
u64 filesz = elf_phdr_get_p_filesz(class, phdr);
u64 offset = elf_phdr_get_p_offset(class, phdr);
u32 type = elf_phdr_get_p_type(class, phdr);
void *ptr;
/*
* There is a case that with PT_LOAD type, the
* filesz = memsz = 0. If memsz = 0, rproc_da_to_va
* should return NULL ptr, then error is returned.
* So this case should be skipped from the loop.
* Add !memsz checking here.
*/
if (type != PT_LOAD || !memsz)
continue;
dev_dbg(dev, "phdr: type %d da 0x%llx memsz 0x%llx filesz 0x%llx\n",
type, da, memsz, filesz);
if (filesz > memsz) {
dev_err(dev, "bad phdr filesz 0x%llx memsz 0x%llx\n",
filesz, memsz);
ret = -EINVAL;
break;
}
if (offset + filesz > fw->size) {
dev_err(dev, "truncated fw: need 0x%llx avail 0x%zx\n",
offset + filesz, fw->size);
ret = -EINVAL;
break;
}
if (!rproc_u64_fit_in_size_t(memsz)) {
dev_err(dev, "size (%llx) does not fit in size_t type\n",
memsz);
ret = -EOVERFLOW;
break;
}
/* grab the kernel address for this device address */
ptr = rproc_da_to_va(rproc, da, memsz, NULL);
if (!ptr) {
dev_err(dev, "bad phdr da 0x%llx mem 0x%llx\n", da,
memsz);
ret = -EINVAL;
break;
}
/* put the segment where the remote processor expects it */
if (filesz)
memcpy(ptr, elf_data + offset, filesz);
/*
* Zero out remaining memory for this segment.
*
* This isn't strictly required since dma_alloc_coherent already
* did this for us. albeit harmless, we may consider removing
* this.
*/
if (memsz > filesz)
memset(ptr + filesz, 0, memsz - filesz);
}
return ret;
}
/* Prepare function for rproc_ops */
static int imx_dsp_rproc_prepare(struct rproc *rproc)
{
struct imx_dsp_rproc *priv = rproc->priv;
struct device *dev = rproc->dev.parent;
struct rproc_mem_entry *carveout;
int ret;
ret = imx_dsp_rproc_add_carveout(priv);
if (ret) {
dev_err(dev, "failed on imx_dsp_rproc_add_carveout\n");
return ret;
}
pm_runtime_get_sync(dev);
/*
* Clear buffers after pm rumtime for internal ocram is not
* accessible if power and clock are not enabled.
*/
list_for_each_entry(carveout, &rproc->carveouts, node) {
if (carveout->va)
memset(carveout->va, 0, carveout->len);
}
return 0;
}
/* Unprepare function for rproc_ops */
static int imx_dsp_rproc_unprepare(struct rproc *rproc)
{
pm_runtime_put_sync(rproc->dev.parent);
return 0;
}
/* Kick function for rproc_ops */
static void imx_dsp_rproc_kick(struct rproc *rproc, int vqid)
{
struct imx_dsp_rproc *priv = rproc->priv;
struct device *dev = rproc->dev.parent;
int err;
__u32 mmsg;
if (!priv->tx_ch) {
dev_err(dev, "No initialized mbox tx channel\n");
return;
}
/*
* Send the index of the triggered virtqueue as the mu payload.
* Let remote processor know which virtqueue is used.
*/
mmsg = vqid;
err = mbox_send_message(priv->tx_ch, (void *)&mmsg);
if (err < 0)
dev_err(dev, "%s: failed (%d, err:%d)\n", __func__, vqid, err);
}
static const struct rproc_ops imx_dsp_rproc_ops = {
.prepare = imx_dsp_rproc_prepare,
.unprepare = imx_dsp_rproc_unprepare,
.start = imx_dsp_rproc_start,
.stop = imx_dsp_rproc_stop,
.kick = imx_dsp_rproc_kick,
.load = imx_dsp_rproc_elf_load_segments,
.parse_fw = rproc_elf_load_rsc_table,
.sanity_check = rproc_elf_sanity_check,
.get_boot_addr = rproc_elf_get_boot_addr,
};
/**
* imx_dsp_attach_pm_domains() - attach the power domains
* @priv: private data pointer
*
* On i.MX8QM and i.MX8QXP there is multiple power domains
* required, so need to link them.
*/
static int imx_dsp_attach_pm_domains(struct imx_dsp_rproc *priv)
{
struct device *dev = priv->rproc->dev.parent;
int ret, i;
priv->num_domains = of_count_phandle_with_args(dev->of_node,
"power-domains",
"#power-domain-cells");
/* If only one domain, then no need to link the device */
if (priv->num_domains <= 1)
return 0;
priv->pd_dev = devm_kmalloc_array(dev, priv->num_domains,
sizeof(*priv->pd_dev),
GFP_KERNEL);
if (!priv->pd_dev)
return -ENOMEM;
priv->pd_dev_link = devm_kmalloc_array(dev, priv->num_domains,
sizeof(*priv->pd_dev_link),
GFP_KERNEL);
if (!priv->pd_dev_link)
return -ENOMEM;
for (i = 0; i < priv->num_domains; i++) {
priv->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i);
if (IS_ERR(priv->pd_dev[i])) {
ret = PTR_ERR(priv->pd_dev[i]);
goto detach_pm;
}
/*
* device_link_add will check priv->pd_dev[i], if it is
* NULL, then will break.
*/
priv->pd_dev_link[i] = device_link_add(dev,
priv->pd_dev[i],
DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME);
if (!priv->pd_dev_link[i]) {
dev_pm_domain_detach(priv->pd_dev[i], false);
ret = -EINVAL;
goto detach_pm;
}
}
return 0;
detach_pm:
while (--i >= 0) {
device_link_del(priv->pd_dev_link[i]);
dev_pm_domain_detach(priv->pd_dev[i], false);
}
return ret;
}
static int imx_dsp_detach_pm_domains(struct imx_dsp_rproc *priv)
{
int i;
if (priv->num_domains <= 1)
return 0;
for (i = 0; i < priv->num_domains; i++) {
device_link_del(priv->pd_dev_link[i]);
dev_pm_domain_detach(priv->pd_dev[i], false);
}
return 0;
}
/**
* imx_dsp_rproc_detect_mode() - detect DSP control mode
* @priv: private data pointer
*
* Different platform has different control method for DSP, which depends
* on how the DSP is integrated in platform.
*
* For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System
* Control Unit.
* For i.MX8MP and i.MX8ULP, DSP should be started and stopped by system
* integration module.
*/
static int imx_dsp_rproc_detect_mode(struct imx_dsp_rproc *priv)
{
const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
struct device *dev = priv->rproc->dev.parent;
struct regmap *regmap;
int ret = 0;
switch (dsp_dcfg->dcfg->method) {
case IMX_RPROC_SCU_API:
ret = imx_scu_get_handle(&priv->ipc_handle);
if (ret)
return ret;
break;
case IMX_RPROC_MMIO:
regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,dsp-ctrl");
if (IS_ERR(regmap)) {
dev_err(dev, "failed to find syscon\n");
return PTR_ERR(regmap);
}
priv->regmap = regmap;
break;
default:
ret = -EOPNOTSUPP;
break;
}
return ret;
}
static const char *imx_dsp_clks_names[DSP_RPROC_CLK_MAX] = {
/* DSP clocks */
"core", "ocram", "debug", "ipg", "mu",
};
static int imx_dsp_rproc_clk_get(struct imx_dsp_rproc *priv)
{
struct device *dev = priv->rproc->dev.parent;
struct clk_bulk_data *clks = priv->clks;
int i;
for (i = 0; i < DSP_RPROC_CLK_MAX; i++)
clks[i].id = imx_dsp_clks_names[i];
return devm_clk_bulk_get_optional(dev, DSP_RPROC_CLK_MAX, clks);
}
static int imx_dsp_rproc_probe(struct platform_device *pdev)
{
const struct imx_dsp_rproc_dcfg *dsp_dcfg;
struct device *dev = &pdev->dev;
struct imx_dsp_rproc *priv;
struct rproc *rproc;
const char *fw_name;
int ret;
dsp_dcfg = of_device_get_match_data(dev);
if (!dsp_dcfg)
return -ENODEV;
ret = rproc_of_parse_firmware(dev, 0, &fw_name);
if (ret) {
dev_err(dev, "failed to parse firmware-name property, ret = %d\n",
ret);
return ret;
}
rproc = rproc_alloc(dev, "imx-dsp-rproc", &imx_dsp_rproc_ops, fw_name,
sizeof(*priv));
if (!rproc)
return -ENOMEM;
priv = rproc->priv;
priv->rproc = rproc;
priv->dsp_dcfg = dsp_dcfg;
dev_set_drvdata(dev, rproc);
INIT_WORK(&priv->rproc_work, imx_dsp_rproc_vq_work);
ret = imx_dsp_rproc_detect_mode(priv);
if (ret) {
dev_err(dev, "failed on imx_dsp_rproc_detect_mode\n");
goto err_put_rproc;
}
/* There are multiple power domains required by DSP on some platform */
ret = imx_dsp_attach_pm_domains(priv);
if (ret) {
dev_err(dev, "failed on imx_dsp_attach_pm_domains\n");
goto err_put_rproc;
}
/* Get clocks */
ret = imx_dsp_rproc_clk_get(priv);
if (ret) {
dev_err(dev, "failed on imx_dsp_rproc_clk_get\n");
goto err_detach_domains;
}
init_completion(&priv->pm_comp);
rproc->auto_boot = false;
ret = rproc_add(rproc);
if (ret) {
dev_err(dev, "rproc_add failed\n");
goto err_detach_domains;
}
pm_runtime_enable(dev);
return 0;
err_detach_domains:
imx_dsp_detach_pm_domains(priv);
err_put_rproc:
rproc_free(rproc);
return ret;
}
static int imx_dsp_rproc_remove(struct platform_device *pdev)
{
struct rproc *rproc = platform_get_drvdata(pdev);
struct imx_dsp_rproc *priv = rproc->priv;
pm_runtime_disable(&pdev->dev);
rproc_del(rproc);
imx_dsp_detach_pm_domains(priv);
rproc_free(rproc);
return 0;
}
/* pm runtime functions */
static int imx_dsp_runtime_resume(struct device *dev)
{
struct rproc *rproc = dev_get_drvdata(dev);
struct imx_dsp_rproc *priv = rproc->priv;
const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
int ret;
/*
* There is power domain attached with mailbox, if setup mailbox
* in probe(), then the power of mailbox is always enabled,
* the power can't be saved.
* So move setup of mailbox to runtime resume.
*/
ret = imx_dsp_rproc_mbox_init(priv);
if (ret) {
dev_err(dev, "failed on imx_dsp_rproc_mbox_init\n");
return ret;
}
ret = clk_bulk_prepare_enable(DSP_RPROC_CLK_MAX, priv->clks);
if (ret) {
dev_err(dev, "failed on clk_bulk_prepare_enable\n");
return ret;
}
/* Reset DSP if needed */
if (dsp_dcfg->reset)
dsp_dcfg->reset(priv);
return 0;
}
static int imx_dsp_runtime_suspend(struct device *dev)
{
struct rproc *rproc = dev_get_drvdata(dev);
struct imx_dsp_rproc *priv = rproc->priv;
clk_bulk_disable_unprepare(DSP_RPROC_CLK_MAX, priv->clks);
imx_dsp_rproc_free_mbox(priv);
return 0;
}
static void imx_dsp_load_firmware(const struct firmware *fw, void *context)
{
struct rproc *rproc = context;
int ret;
/*
* Same flow as start procedure.
* Load the ELF segments to memory firstly.
*/
ret = rproc_load_segments(rproc, fw);
if (ret)
goto out;
/* Start the remote processor */
ret = rproc->ops->start(rproc);
if (ret)
goto out;
rproc->ops->kick(rproc, 0);
out:
release_firmware(fw);
}
static __maybe_unused int imx_dsp_suspend(struct device *dev)
{
struct rproc *rproc = dev_get_drvdata(dev);
struct imx_dsp_rproc *priv = rproc->priv;
__u32 mmsg = RP_MBOX_SUSPEND_SYSTEM;
int ret;
if (rproc->state != RPROC_RUNNING)
goto out;
reinit_completion(&priv->pm_comp);
/* Tell DSP that suspend is happening */
ret = mbox_send_message(priv->tx_ch, (void *)&mmsg);
if (ret < 0) {
dev_err(dev, "PM mbox_send_message failed: %d\n", ret);
return ret;
}
/*
* DSP need to save the context at suspend.
* Here waiting the response for DSP, then power can be disabled.
*/
if (!wait_for_completion_timeout(&priv->pm_comp, msecs_to_jiffies(100)))
return -EBUSY;
out:
/*
* The power of DSP is disabled in suspend, so force pm runtime
* to be suspend, then we can reenable the power and clocks at
* resume stage.
*/
return pm_runtime_force_suspend(dev);
}
static __maybe_unused int imx_dsp_resume(struct device *dev)
{
struct rproc *rproc = dev_get_drvdata(dev);
int ret = 0;
ret = pm_runtime_force_resume(dev);
if (ret)
return ret;
if (rproc->state != RPROC_RUNNING)
return 0;
/*
* The power of DSP is disabled at suspend, the memory of dsp
* is reset, the image segments are lost. So need to reload
* firmware and restart the DSP if it is in running state.
*/
ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
rproc->firmware, dev, GFP_KERNEL,
rproc, imx_dsp_load_firmware);
if (ret < 0) {
dev_err(dev, "load firmware failed: %d\n", ret);
goto err;
}
return 0;
err:
pm_runtime_force_suspend(dev);
return ret;
}
static const struct dev_pm_ops imx_dsp_rproc_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(imx_dsp_suspend, imx_dsp_resume)
SET_RUNTIME_PM_OPS(imx_dsp_runtime_suspend,
imx_dsp_runtime_resume, NULL)
};
static const struct of_device_id imx_dsp_rproc_of_match[] = {
{ .compatible = "fsl,imx8qxp-hifi4", .data = &imx_dsp_rproc_cfg_imx8qxp },
{ .compatible = "fsl,imx8qm-hifi4", .data = &imx_dsp_rproc_cfg_imx8qm },
{ .compatible = "fsl,imx8mp-hifi4", .data = &imx_dsp_rproc_cfg_imx8mp },
{ .compatible = "fsl,imx8ulp-hifi4", .data = &imx_dsp_rproc_cfg_imx8ulp },
{},
};
MODULE_DEVICE_TABLE(of, imx_dsp_rproc_of_match);
static struct platform_driver imx_dsp_rproc_driver = {
.probe = imx_dsp_rproc_probe,
.remove = imx_dsp_rproc_remove,
.driver = {
.name = "imx-dsp-rproc",
.of_match_table = imx_dsp_rproc_of_match,
.pm = &imx_dsp_rproc_pm_ops,
},
};
module_platform_driver(imx_dsp_rproc_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("i.MX HiFi Core Remote Processor Control Driver");
MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
drivers/remoteproc/imx_rproc.c
View file @ bd485d27
......@@ -19,6 +19,7 @@
#include <linux/remoteproc.h>
#include <linux/workqueue.h>
#include "imx_rproc.h"
#include "remoteproc_internal.h"
#define IMX7D_SRC_SCR 0x0C
......@@ -71,33 +72,7 @@ struct imx_rproc_mem {
/* att flags */
/* M4 own area. Can be mapped at probe */
#define ATT_OWN BIT(1)
/* address translation table */
struct imx_rproc_att {
u32 da; /* device address (From Cortex M4 view)*/
u32 sa; /* system bus address */
u32 size; /* size of reg range */
int flags;
};
/* Remote core start/stop method */
enum imx_rproc_method {
IMX_RPROC_NONE,
/* Through syscon regmap */
IMX_RPROC_MMIO,
/* Through ARM SMCCC */
IMX_RPROC_SMC,
};
struct imx_rproc_dcfg {
u32 src_reg;
u32 src_mask;
u32 src_start;
u32 src_stop;
const struct imx_rproc_att *att;
size_t att_size;
enum imx_rproc_method method;
};
#define ATT_IOMEM BIT(2)
struct imx_rproc {
struct device *dev;
......@@ -117,7 +92,7 @@ struct imx_rproc {
static const struct imx_rproc_att imx_rproc_att_imx8mn[] = {
/* dev addr , sys addr , size , flags */
/* ITCM */
{ 0x00000000, 0x007E0000, 0x00020000, ATT_OWN },
{ 0x00000000, 0x007E0000, 0x00020000, ATT_OWN | ATT_IOMEM },
/* OCRAM_S */
{ 0x00180000, 0x00180000, 0x00009000, 0 },
/* OCRAM */
......@@ -131,7 +106,7 @@ static const struct imx_rproc_att imx_rproc_att_imx8mn[] = {
/* DDR (Code) - alias */
{ 0x10000000, 0x40000000, 0x0FFE0000, 0 },
/* DTCM */
{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN },
{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN | ATT_IOMEM },
/* OCRAM_S - alias */
{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
/* OCRAM */
......@@ -147,7 +122,7 @@ static const struct imx_rproc_att imx_rproc_att_imx8mn[] = {
static const struct imx_rproc_att imx_rproc_att_imx8mq[] = {
/* dev addr , sys addr , size , flags */
/* TCML - alias */
{ 0x00000000, 0x007e0000, 0x00020000, 0 },
{ 0x00000000, 0x007e0000, 0x00020000, ATT_IOMEM},
/* OCRAM_S */
{ 0x00180000, 0x00180000, 0x00008000, 0 },
/* OCRAM */
......@@ -159,9 +134,9 @@ static const struct imx_rproc_att imx_rproc_att_imx8mq[] = {
/* DDR (Code) - alias */
{ 0x10000000, 0x80000000, 0x0FFE0000, 0 },
/* TCML */
{ 0x1FFE0000, 0x007E0000, 0x00020000, ATT_OWN },
{ 0x1FFE0000, 0x007E0000, 0x00020000, ATT_OWN | ATT_IOMEM},
/* TCMU */
{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN },
{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN | ATT_IOMEM},
/* OCRAM_S */
{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
/* OCRAM */
......@@ -199,12 +174,12 @@ static const struct imx_rproc_att imx_rproc_att_imx7d[] = {
/* OCRAM_PXP (Code) - alias */
{ 0x00940000, 0x00940000, 0x00008000, 0 },
/* TCML (Code) */
{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM },
/* DDR (Code) - alias, first part of DDR (Data) */
{ 0x10000000, 0x80000000, 0x0FFF0000, 0 },
/* TCMU (Data) */
{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM },
/* OCRAM (Data) */
{ 0x20200000, 0x00900000, 0x00020000, 0 },
/* OCRAM_EPDC (Data) */
......@@ -218,18 +193,18 @@ static const struct imx_rproc_att imx_rproc_att_imx7d[] = {
static const struct imx_rproc_att imx_rproc_att_imx6sx[] = {
/* dev addr , sys addr , size , flags */
/* TCML (M4 Boot Code) - alias */
{ 0x00000000, 0x007F8000, 0x00008000, 0 },
{ 0x00000000, 0x007F8000, 0x00008000, ATT_IOMEM },
/* OCRAM_S (Code) */
{ 0x00180000, 0x008F8000, 0x00004000, 0 },
/* OCRAM_S (Code) - alias */
{ 0x00180000, 0x008FC000, 0x00004000, 0 },
/* TCML (Code) */
{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM },
/* DDR (Code) - alias, first part of DDR (Data) */
{ 0x10000000, 0x80000000, 0x0FFF8000, 0 },
/* TCMU (Data) */
{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM },
/* OCRAM_S (Data) - alias? */
{ 0x208F8000, 0x008F8000, 0x00004000, 0 },
/* DDR (Data) */
......@@ -341,7 +316,7 @@ static int imx_rproc_stop(struct rproc *rproc)
}
static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da,
size_t len, u64 *sys)
size_t len, u64 *sys, bool *is_iomem)
{
const struct imx_rproc_dcfg *dcfg = priv->dcfg;
int i;
......@@ -354,6 +329,8 @@ static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da,
unsigned int offset = da - att->da;
*sys = att->sa + offset;
if (is_iomem)
*is_iomem = att->flags & ATT_IOMEM;
return 0;
}
}
......@@ -377,7 +354,7 @@ static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *i
* On device side we have many aliases, so we need to convert device
* address (M4) to system bus address first.
*/
if (imx_rproc_da_to_sys(priv, da, len, &sys))
if (imx_rproc_da_to_sys(priv, da, len, &sys, is_iomem))
return NULL;
for (i = 0; i < IMX_RPROC_MEM_MAX; i++) {
......@@ -553,8 +530,12 @@ static int imx_rproc_addr_init(struct imx_rproc *priv,
if (b >= IMX_RPROC_MEM_MAX)
break;
priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev,
att->sa, att->size);
if (att->flags & ATT_IOMEM)
priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev,
att->sa, att->size);
else
priv->mem[b].cpu_addr = devm_ioremap_wc(&pdev->dev,
att->sa, att->size);
if (!priv->mem[b].cpu_addr) {
dev_err(dev, "failed to remap %#x bytes from %#x\n", att->size, att->sa);
return -ENOMEM;
......@@ -575,8 +556,8 @@ static int imx_rproc_addr_init(struct imx_rproc *priv,
struct resource res;
node = of_parse_phandle(np, "memory-region", a);
/* Not map vdev region */
if (!strcmp(node->name, "vdev"))
/* Not map vdevbuffer, vdevring region */
if (!strncmp(node->name, "vdev", strlen("vdev")))
continue;
err = of_address_to_resource(node, 0, &res);
if (err) {
......@@ -590,14 +571,14 @@ static int imx_rproc_addr_init(struct imx_rproc *priv,
break;
/* Not use resource version, because we might share region */
priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
priv->mem[b].cpu_addr = devm_ioremap_wc(&pdev->dev, res.start, resource_size(&res));
if (!priv->mem[b].cpu_addr) {
dev_err(dev, "failed to remap %pr\n", &res);
return -ENOMEM;
}
priv->mem[b].sys_addr = res.start;
priv->mem[b].size = resource_size(&res);
if (!strcmp(node->name, "rsc_table"))
if (!strcmp(node->name, "rsc-table"))
priv->rsc_table = priv->mem[b].cpu_addr;
b++;
}
......
drivers/remoteproc/imx_rproc.h 0 → 100644
View file @ bd485d27
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
* Copyright 2021 NXP
*/
#ifndef _IMX_RPROC_H
#define _IMX_RPROC_H
/* address translation table */
struct imx_rproc_att {
u32 da; /* device address (From Cortex M4 view)*/
u32 sa; /* system bus address */
u32 size; /* size of reg range */
int flags;
};
/* Remote core start/stop method */
enum imx_rproc_method {
IMX_RPROC_NONE,
/* Through syscon regmap */
IMX_RPROC_MMIO,
/* Through ARM SMCCC */
IMX_RPROC_SMC,
/* Through System Control Unit API */
IMX_RPROC_SCU_API,
};
struct imx_rproc_dcfg {
u32 src_reg;
u32 src_mask;
u32 src_start;
u32 src_stop;
const struct imx_rproc_att *att;
size_t att_size;
enum imx_rproc_method method;
};
#endif /* _IMX_RPROC_H */
drivers/remoteproc/meson_mx_ao_arc.c 0 → 100644
View file @ bd485d27
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
*/
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/genalloc.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/remoteproc.h>
#include <linux/reset.h>
#include <linux/sizes.h>
#include "remoteproc_internal.h"
#define AO_REMAP_REG0 0x0
#define AO_REMAP_REG0_REMAP_AHB_SRAM_BITS_17_14_FOR_ARM_CPU GENMASK(3, 0)
#define AO_REMAP_REG1 0x4
#define AO_REMAP_REG1_MOVE_AHB_SRAM_TO_0X0_INSTEAD_OF_DDR BIT(4)
#define AO_REMAP_REG1_REMAP_AHB_SRAM_BITS_17_14_FOR_MEDIA_CPU GENMASK(3, 0)
#define AO_CPU_CNTL 0x0
#define AO_CPU_CNTL_AHB_SRAM_BITS_31_20 GENMASK(28, 16)
#define AO_CPU_CNTL_HALT BIT(9)
#define AO_CPU_CNTL_UNKNONWN BIT(8)
#define AO_CPU_CNTL_RUN BIT(0)
#define AO_CPU_STAT 0x4
#define AO_SECURE_REG0 0x0
#define AO_SECURE_REG0_AHB_SRAM_BITS_19_12 GENMASK(15, 8)
/* Only bits [31:20] and [17:14] are usable, all other bits must be zero */
#define MESON_AO_RPROC_SRAM_USABLE_BITS 0xfff3c000ULL
#define MESON_AO_RPROC_MEMORY_OFFSET 0x10000000
struct meson_mx_ao_arc_rproc_priv {
void __iomem *remap_base;
void __iomem *cpu_base;
unsigned long sram_va;
phys_addr_t sram_pa;
size_t sram_size;
struct gen_pool *sram_pool;
struct reset_control *arc_reset;
struct clk *arc_pclk;
struct regmap *secbus2_regmap;
};
static int meson_mx_ao_arc_rproc_start(struct rproc *rproc)
{
struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv;
phys_addr_t translated_sram_addr;
u32 tmp;
int ret;
ret = clk_prepare_enable(priv->arc_pclk);
if (ret)
return ret;
tmp = FIELD_PREP(AO_REMAP_REG0_REMAP_AHB_SRAM_BITS_17_14_FOR_ARM_CPU,
priv->sram_pa >> 14);
writel(tmp, priv->remap_base + AO_REMAP_REG0);
/*
* The SRAM content as seen by the ARC core always starts at 0x0
* regardless of the value given here (this was discovered by trial and
* error). For SoCs older than Meson6 we probably have to set
* AO_REMAP_REG1_MOVE_AHB_SRAM_TO_0X0_INSTEAD_OF_DDR to achieve the
* same. (At least) For Meson8 and newer that bit must not be set.
*/
writel(0x0, priv->remap_base + AO_REMAP_REG1);
regmap_update_bits(priv->secbus2_regmap, AO_SECURE_REG0,
AO_SECURE_REG0_AHB_SRAM_BITS_19_12,
FIELD_PREP(AO_SECURE_REG0_AHB_SRAM_BITS_19_12,
priv->sram_pa >> 12));
ret = reset_control_reset(priv->arc_reset);
if (ret) {
clk_disable_unprepare(priv->arc_pclk);
return ret;
}
usleep_range(10, 100);
/*
* Convert from 0xd9000000 to 0xc9000000 as the vendor driver does.
* This only seems to be relevant for the AO_CPU_CNTL register. It is
* unknown why this is needed.
*/
translated_sram_addr = priv->sram_pa - MESON_AO_RPROC_MEMORY_OFFSET;
tmp = FIELD_PREP(AO_CPU_CNTL_AHB_SRAM_BITS_31_20,
translated_sram_addr >> 20);
tmp |= AO_CPU_CNTL_UNKNONWN | AO_CPU_CNTL_RUN;
writel(tmp, priv->cpu_base + AO_CPU_CNTL);
usleep_range(20, 200);
return 0;
}
static int meson_mx_ao_arc_rproc_stop(struct rproc *rproc)
{
struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv;
writel(AO_CPU_CNTL_HALT, priv->cpu_base + AO_CPU_CNTL);
clk_disable_unprepare(priv->arc_pclk);
return 0;
}
static void *meson_mx_ao_arc_rproc_da_to_va(struct rproc *rproc, u64 da,
size_t len, bool *is_iomem)
{
struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv;
/* The memory from the ARC core's perspective always starts at 0x0. */
if ((da + len) > priv->sram_size)
return NULL;
return (void *)priv->sram_va + da;
}
static struct rproc_ops meson_mx_ao_arc_rproc_ops = {
.start = meson_mx_ao_arc_rproc_start,
.stop = meson_mx_ao_arc_rproc_stop,
.da_to_va = meson_mx_ao_arc_rproc_da_to_va,
.get_boot_addr = rproc_elf_get_boot_addr,
.load = rproc_elf_load_segments,
.sanity_check = rproc_elf_sanity_check,
};
static int meson_mx_ao_arc_rproc_probe(struct platform_device *pdev)
{
struct meson_mx_ao_arc_rproc_priv *priv;
struct device *dev = &pdev->dev;
const char *fw_name = NULL;
struct rproc *rproc;
int ret;
device_property_read_string(dev, "firmware-name", &fw_name);
rproc = devm_rproc_alloc(dev, "meson-mx-ao-arc",
&meson_mx_ao_arc_rproc_ops, fw_name,
sizeof(*priv));
if (!rproc)
return -ENOMEM;
rproc->has_iommu = false;
priv = rproc->priv;
priv->sram_pool = of_gen_pool_get(dev->of_node, "sram", 0);
if (!priv->sram_pool) {
dev_err(dev, "Could not get SRAM pool\n");
return -ENODEV;
}
priv->sram_size = gen_pool_avail(priv->sram_pool);
priv->sram_va = gen_pool_alloc(priv->sram_pool, priv->sram_size);
if (!priv->sram_va) {
dev_err(dev, "Could not alloc memory in SRAM pool\n");
return -ENOMEM;
}
priv->sram_pa = gen_pool_virt_to_phys(priv->sram_pool, priv->sram_va);
if (priv->sram_pa & ~MESON_AO_RPROC_SRAM_USABLE_BITS) {
dev_err(dev, "SRAM address contains unusable bits\n");
ret = -EINVAL;
goto err_free_genpool;
}
priv->secbus2_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
"amlogic,secbus2");
if (IS_ERR(priv->secbus2_regmap)) {
dev_err(dev, "Failed to find SECBUS2 regmap\n");
ret = PTR_ERR(priv->secbus2_regmap);
goto err_free_genpool;
}
priv->remap_base = devm_platform_ioremap_resource_byname(pdev, "remap");
if (IS_ERR(priv->remap_base)) {
ret = PTR_ERR(priv->remap_base);
goto err_free_genpool;
}
priv->cpu_base = devm_platform_ioremap_resource_byname(pdev, "cpu");
if (IS_ERR(priv->cpu_base)) {
ret = PTR_ERR(priv->cpu_base);
goto err_free_genpool;
}
priv->arc_reset = devm_reset_control_get_exclusive(dev, NULL);
if (IS_ERR(priv->arc_reset)) {
dev_err(dev, "Failed to get ARC reset\n");
ret = PTR_ERR(priv->arc_reset);
goto err_free_genpool;
}
priv->arc_pclk = devm_clk_get(dev, NULL);
if (IS_ERR(priv->arc_pclk)) {
dev_err(dev, "Failed to get the ARC PCLK\n");
ret = PTR_ERR(priv->arc_pclk);
goto err_free_genpool;
}
platform_set_drvdata(pdev, rproc);
ret = rproc_add(rproc);
if (ret)
goto err_free_genpool;
return 0;
err_free_genpool:
gen_pool_free(priv->sram_pool, priv->sram_va, priv->sram_size);
return ret;
}
static int meson_mx_ao_arc_rproc_remove(struct platform_device *pdev)
{
struct rproc *rproc = platform_get_drvdata(pdev);
struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv;
rproc_del(rproc);
gen_pool_free(priv->sram_pool, priv->sram_va, priv->sram_size);
return 0;
}
static const struct of_device_id meson_mx_ao_arc_rproc_match[] = {
{ .compatible = "amlogic,meson8-ao-arc" },
{ .compatible = "amlogic,meson8b-ao-arc" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, meson_mx_ao_arc_rproc_match);
static struct platform_driver meson_mx_ao_arc_rproc_driver = {
.probe = meson_mx_ao_arc_rproc_probe,
.remove = meson_mx_ao_arc_rproc_remove,
.driver = {
.name = "meson-mx-ao-arc-rproc",
.of_match_table = meson_mx_ao_arc_rproc_match,
},
};
module_platform_driver(meson_mx_ao_arc_rproc_driver);
MODULE_DESCRIPTION("Amlogic Meson6/8/8b/8m2 AO ARC remote processor driver");
MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
MODULE_LICENSE("GPL v2");
drivers/remoteproc/mtk_common.h
View file @ bd485d27
......@@ -72,6 +72,7 @@ struct scp_ipi_desc {
struct mtk_scp;
struct mtk_scp_of_data {
int (*scp_clk_get)(struct mtk_scp *scp);
int (*scp_before_load)(struct mtk_scp *scp);
void (*scp_irq_handler)(struct mtk_scp *scp);
void (*scp_reset_assert)(struct mtk_scp *scp);
......
drivers/remoteproc/mtk_scp.c
View file @ bd485d27
......@@ -312,6 +312,32 @@ static int scp_elf_read_ipi_buf_addr(struct mtk_scp *scp,
return -ENOENT;
}
static int mt8183_scp_clk_get(struct mtk_scp *scp)
{
struct device *dev = scp->dev;
int ret = 0;
scp->clk = devm_clk_get(dev, "main");
if (IS_ERR(scp->clk)) {
dev_err(dev, "Failed to get clock\n");
ret = PTR_ERR(scp->clk);
}
return ret;
}
static int mt8192_scp_clk_get(struct mtk_scp *scp)
{
return mt8183_scp_clk_get(scp);
}
static int mt8195_scp_clk_get(struct mtk_scp *scp)
{
scp->clk = NULL;
return 0;
}
static int mt8183_scp_before_load(struct mtk_scp *scp)
{
/* Clear SCP to host interrupt */
......@@ -785,12 +811,9 @@ static int scp_probe(struct platform_device *pdev)
if (ret)
goto destroy_mutex;
scp->clk = devm_clk_get(dev, "main");
if (IS_ERR(scp->clk)) {
dev_err(dev, "Failed to get clock\n");
ret = PTR_ERR(scp->clk);
ret = scp->data->scp_clk_get(scp);
if (ret)
goto release_dev_mem;
}
/* register SCP initialization IPI */
ret = scp_ipi_register(scp, SCP_IPI_INIT, scp_init_ipi_handler, scp);
......@@ -852,6 +875,7 @@ static int scp_remove(struct platform_device *pdev)
}
static const struct mtk_scp_of_data mt8183_of_data = {
.scp_clk_get = mt8183_scp_clk_get,
.scp_before_load = mt8183_scp_before_load,
.scp_irq_handler = mt8183_scp_irq_handler,
.scp_reset_assert = mt8183_scp_reset_assert,
......@@ -864,6 +888,19 @@ static const struct mtk_scp_of_data mt8183_of_data = {
};
static const struct mtk_scp_of_data mt8192_of_data = {
.scp_clk_get = mt8192_scp_clk_get,
.scp_before_load = mt8192_scp_before_load,
.scp_irq_handler = mt8192_scp_irq_handler,
.scp_reset_assert = mt8192_scp_reset_assert,
.scp_reset_deassert = mt8192_scp_reset_deassert,
.scp_stop = mt8192_scp_stop,
.scp_da_to_va = mt8192_scp_da_to_va,
.host_to_scp_reg = MT8192_GIPC_IN_SET,
.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
};
static const struct mtk_scp_of_data mt8195_of_data = {
.scp_clk_get = mt8195_scp_clk_get,
.scp_before_load = mt8192_scp_before_load,
.scp_irq_handler = mt8192_scp_irq_handler,
.scp_reset_assert = mt8192_scp_reset_assert,
......@@ -877,6 +914,7 @@ static const struct mtk_scp_of_data mt8192_of_data = {
static const struct of_device_id mtk_scp_of_match[] = {
{ .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data },
{ .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data },
{ .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data },
{},
};
MODULE_DEVICE_TABLE(of, mtk_scp_of_match);
......
drivers/remoteproc/omap_remoteproc.c
View file @ bd485d27
......@@ -901,8 +901,7 @@ static int _omap_rproc_resume(struct rproc *rproc, bool auto_suspend)
static int __maybe_unused omap_rproc_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct rproc *rproc = platform_get_drvdata(pdev);
struct rproc *rproc = dev_get_drvdata(dev);
struct omap_rproc *oproc = rproc->priv;
int ret = 0;
......@@ -938,8 +937,7 @@ static int __maybe_unused omap_rproc_suspend(struct device *dev)
static int __maybe_unused omap_rproc_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct rproc *rproc = platform_get_drvdata(pdev);
struct rproc *rproc = dev_get_drvdata(dev);
struct omap_rproc *oproc = rproc->priv;
int ret = 0;
......
drivers/remoteproc/qcom_q6v5.c
View file @ bd485d27
......@@ -16,8 +16,30 @@
#include "qcom_common.h"
#include "qcom_q6v5.h"
#define Q6V5_LOAD_STATE_MSG_LEN 64
#define Q6V5_PANIC_DELAY_MS 200
static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable)
{
char buf[Q6V5_LOAD_STATE_MSG_LEN];
int ret;
if (!q6v5->qmp)
return 0;
ret = snprintf(buf, sizeof(buf),
"{class: image, res: load_state, name: %s, val: %s}",
q6v5->load_state, enable ? "on" : "off");
WARN_ON(ret >= Q6V5_LOAD_STATE_MSG_LEN);
ret = qmp_send(q6v5->qmp, buf, sizeof(buf));
if (ret)
dev_err(q6v5->dev, "failed to toggle load state\n");
return ret;
}
/**
* qcom_q6v5_prepare() - reinitialize the qcom_q6v5 context before start
* @q6v5: reference to qcom_q6v5 context to be reinitialized
......@@ -26,6 +48,12 @@
*/
int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5)
{
int ret;
ret = q6v5_load_state_toggle(q6v5, true);
if (ret)
return ret;
reinit_completion(&q6v5->start_done);
reinit_completion(&q6v5->stop_done);
......@@ -47,6 +75,7 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_prepare);
int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5)
{
disable_irq(q6v5->handover_irq);
q6v5_load_state_toggle(q6v5, false);
return !q6v5->handover_issued;
}
......@@ -196,12 +225,13 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_panic);
* @pdev: platform_device reference for acquiring resources
* @rproc: associated remoteproc instance
* @crash_reason: SMEM id for crash reason string, or 0 if none
* @load_state: load state resource string
* @handover: function to be called when proxy resources should be released
*
* Return: 0 on success, negative errno on failure
*/
int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
struct rproc *rproc, int crash_reason,
struct rproc *rproc, int crash_reason, const char *load_state,
void (*handover)(struct qcom_q6v5 *q6v5))
{
int ret;
......@@ -286,9 +316,34 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
return PTR_ERR(q6v5->state);
}
q6v5->load_state = devm_kstrdup_const(&pdev->dev, load_state, GFP_KERNEL);
q6v5->qmp = qmp_get(&pdev->dev);
if (IS_ERR(q6v5->qmp)) {
if (PTR_ERR(q6v5->qmp) != -ENODEV)
return dev_err_probe(&pdev->dev, PTR_ERR(q6v5->qmp),
"failed to acquire load state\n");
q6v5->qmp = NULL;
} else if (!q6v5->load_state) {
if (!load_state)
dev_err(&pdev->dev, "load state resource string empty\n");
qmp_put(q6v5->qmp);
return load_state ? -ENOMEM : -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_q6v5_init);
/**
* qcom_q6v5_deinit() - deinitialize the q6v5 common struct
* @q6v5: reference to qcom_q6v5 context to be deinitialized
*/
void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5)
{
qmp_put(q6v5->qmp);
}
EXPORT_SYMBOL_GPL(qcom_q6v5_deinit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Q6V5");
drivers/remoteproc/qcom_q6v5.h
View file @ bd485d27
......@@ -5,6 +5,7 @@
#include <linux/kernel.h>
#include <linux/completion.h>
#include <linux/soc/qcom/qcom_aoss.h>
struct rproc;
struct qcom_smem_state;
......@@ -15,6 +16,8 @@ struct qcom_q6v5 {
struct rproc *rproc;
struct qcom_smem_state *state;
struct qmp *qmp;
unsigned stop_bit;
int wdog_irq;
......@@ -32,12 +35,14 @@ struct qcom_q6v5 {
bool running;
const char *load_state;
void (*handover)(struct qcom_q6v5 *q6v5);
};
int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
struct rproc *rproc, int crash_reason,
struct rproc *rproc, int crash_reason, const char *load_state,
void (*handover)(struct qcom_q6v5 *q6v5));
void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5);
int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5);
int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5);
......
drivers/remoteproc/qcom_q6v5_adsp.c
View file @ bd485d27
......@@ -185,7 +185,9 @@ static int adsp_start(struct rproc *rproc)
int ret;
unsigned int val;
qcom_q6v5_prepare(&adsp->q6v5);
ret = qcom_q6v5_prepare(&adsp->q6v5);
if (ret)
return ret;
ret = clk_prepare_enable(adsp->xo);
if (ret)
......@@ -465,7 +467,7 @@ static int adsp_probe(struct platform_device *pdev)
if (ret)
goto disable_pm;
ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, NULL,
qcom_adsp_pil_handover);
if (ret)
goto disable_pm;
......@@ -500,6 +502,7 @@ static int adsp_remove(struct platform_device *pdev)
rproc_del(adsp->rproc);
qcom_q6v5_deinit(&adsp->q6v5);
qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
qcom_remove_sysmon_subdev(adsp->sysmon);
qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
......
drivers/remoteproc/qcom_q6v5_mss.c
View file @ bd485d27
......@@ -77,6 +77,14 @@
#define HALT_ACK_TIMEOUT_US 100000
/* QACCEPT Register Offsets */
#define QACCEPT_ACCEPT_REG 0x0
#define QACCEPT_ACTIVE_REG 0x4
#define QACCEPT_DENY_REG 0x8
#define QACCEPT_REQ_REG 0xC
#define QACCEPT_TIMEOUT_US 50
/* QDSP6SS_RESET */
#define Q6SS_STOP_CORE BIT(0)
#define Q6SS_CORE_ARES BIT(1)
......@@ -137,13 +145,15 @@ struct rproc_hexagon_res {
char **proxy_clk_names;
char **reset_clk_names;
char **active_clk_names;
char **active_pd_names;
char **proxy_pd_names;
int version;
bool need_mem_protection;
bool has_alt_reset;
bool has_mba_logs;
bool has_spare_reg;
bool has_qaccept_regs;
bool has_ext_cntl_regs;
bool has_vq6;
};
struct q6v5 {
......@@ -159,8 +169,18 @@ struct q6v5 {
u32 halt_q6;
u32 halt_modem;
u32 halt_nc;
u32 halt_vq6;
u32 conn_box;
u32 qaccept_mdm;
u32 qaccept_cx;
u32 qaccept_axi;
u32 axim1_clk_off;
u32 crypto_clk_off;
u32 force_clk_on;
u32 rscc_disable;
struct reset_control *mss_restart;
struct reset_control *pdc_reset;
......@@ -169,12 +189,10 @@ struct q6v5 {
struct clk *active_clks[8];
struct clk *reset_clks[4];
struct clk *proxy_clks[4];
struct device *active_pds[1];
struct device *proxy_pds[3];
int active_clk_count;
int reset_clk_count;
int proxy_clk_count;
int active_pd_count;
int proxy_pd_count;
struct reg_info active_regs[1];
......@@ -204,6 +222,9 @@ struct q6v5 {
bool has_alt_reset;
bool has_mba_logs;
bool has_spare_reg;
bool has_qaccept_regs;
bool has_ext_cntl_regs;
bool has_vq6;
int mpss_perm;
int mba_perm;
const char *hexagon_mdt_image;
......@@ -216,6 +237,7 @@ enum {
MSS_MSM8996,
MSS_MSM8998,
MSS_SC7180,
MSS_SC7280,
MSS_SDM845,
};
......@@ -476,6 +498,12 @@ static int q6v5_reset_assert(struct q6v5 *qproc)
regmap_update_bits(qproc->conn_map, qproc->conn_box,
AXI_GATING_VALID_OVERRIDE, 0);
ret = reset_control_deassert(qproc->mss_restart);
} else if (qproc->has_ext_cntl_regs) {
regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
reset_control_assert(qproc->pdc_reset);
reset_control_assert(qproc->mss_restart);
reset_control_deassert(qproc->pdc_reset);
ret = reset_control_deassert(qproc->mss_restart);
} else {
ret = reset_control_assert(qproc->mss_restart);
}
......@@ -493,7 +521,7 @@ static int q6v5_reset_deassert(struct q6v5 *qproc)
ret = reset_control_reset(qproc->mss_restart);
writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
reset_control_deassert(qproc->pdc_reset);
} else if (qproc->has_spare_reg) {
} else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
ret = reset_control_reset(qproc->mss_restart);
} else {
ret = reset_control_deassert(qproc->mss_restart);
......@@ -607,7 +635,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
}
goto pbl_wait;
} else if (qproc->version == MSS_SC7180) {
} else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
val = readl(qproc->reg_base + QDSP6SS_SLEEP);
val |= Q6SS_CBCR_CLKEN;
writel(val, qproc->reg_base + QDSP6SS_SLEEP);
......@@ -790,6 +818,89 @@ static int q6v5proc_reset(struct q6v5 *qproc)
return ret;
}
static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
{
unsigned int val;
int ret;
if (!qproc->has_qaccept_regs)
return 0;
if (qproc->has_ext_cntl_regs) {
regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
!val, 1, Q6SS_CBCR_TIMEOUT_US);
if (ret) {
dev_err(qproc->dev, "failed to enable axim1 clock\n");
return -ETIMEDOUT;
}
}
regmap_write(map, offset + QACCEPT_REQ_REG, 1);
/* Wait for accept */
ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5,
QACCEPT_TIMEOUT_US);
if (ret) {
dev_err(qproc->dev, "qchannel enable failed\n");
return -ETIMEDOUT;
}
return 0;
}
static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
{
int ret;
unsigned int val, retry;
unsigned int nretry = 10;
bool takedown_complete = false;
if (!qproc->has_qaccept_regs)
return;
while (!takedown_complete && nretry) {
nretry--;
/* Wait for active transactions to complete */
regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5,
QACCEPT_TIMEOUT_US);
/* Request Q-channel transaction takedown */
regmap_write(map, offset + QACCEPT_REQ_REG, 0);
/*
* If the request is denied, reset the Q-channel takedown request,
* wait for active transactions to complete and retry takedown.
*/
retry = 10;
while (retry) {
usleep_range(5, 10);
retry--;
ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val);
if (!ret && val) {
regmap_write(map, offset + QACCEPT_REQ_REG, 1);
break;
}
ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val);
if (!ret && !val) {
takedown_complete = true;
break;
}
}
if (!retry)
break;
}
/* Rely on mss_restart to clear out pending transactions on takedown failure */
if (!takedown_complete)
dev_err(qproc->dev, "qchannel takedown failed\n");
}
static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
struct regmap *halt_map,
u32 offset)
......@@ -895,18 +1006,14 @@ static int q6v5_mba_load(struct q6v5 *qproc)
int xfermemop_ret;
bool mba_load_err = false;
qcom_q6v5_prepare(&qproc->q6v5);
ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
if (ret < 0) {
dev_err(qproc->dev, "failed to enable active power domains\n");
goto disable_irqs;
}
ret = qcom_q6v5_prepare(&qproc->q6v5);
if (ret)
return ret;
ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
if (ret < 0) {
dev_err(qproc->dev, "failed to enable proxy power domains\n");
goto disable_active_pds;
goto disable_irqs;
}
ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
......@@ -957,6 +1064,12 @@ static int q6v5_mba_load(struct q6v5 *qproc)
goto assert_reset;
}
ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
if (ret) {
dev_err(qproc->dev, "failed to enable axi bridge\n");
goto disable_active_clks;
}
/*
* Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
* the Q6 access to this region.
......@@ -1003,8 +1116,13 @@ static int q6v5_mba_load(struct q6v5 *qproc)
halt_axi_ports:
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
if (qproc->has_vq6)
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
mba_load_err = true;
reclaim_mba:
xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
......@@ -1039,8 +1157,6 @@ static int q6v5_mba_load(struct q6v5 *qproc)
qproc->fallback_proxy_reg_count);
disable_proxy_pds:
q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
disable_active_pds:
q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
disable_irqs:
qcom_q6v5_unprepare(&qproc->q6v5);
......@@ -1056,6 +1172,8 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
qproc->dp_size = 0;
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
if (qproc->has_vq6)
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
if (qproc->version == MSS_MSM8996) {
......@@ -1068,6 +1186,24 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
}
if (qproc->has_ext_cntl_regs) {
regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
!val, 1, Q6SS_CBCR_TIMEOUT_US);
if (ret)
dev_err(qproc->dev, "failed to enable axim1 clock\n");
ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
!val, 1, Q6SS_CBCR_TIMEOUT_US);
if (ret)
dev_err(qproc->dev, "failed to enable crypto clock\n");
}
q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
q6v5_reset_assert(qproc);
q6v5_clk_disable(qproc->dev, qproc->reset_clks,
......@@ -1076,7 +1212,6 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
qproc->active_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
/* In case of failure or coredump scenario where reclaiming MBA memory
* could not happen reclaim it here.
......@@ -1480,21 +1615,22 @@ static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
{
struct of_phandle_args args;
struct resource *res;
int halt_cell_cnt = 3;
int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
qproc->reg_base = devm_platform_ioremap_resource_byname(pdev, "qdsp6");
if (IS_ERR(qproc->reg_base))
return PTR_ERR(qproc->reg_base);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
qproc->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb");
if (IS_ERR(qproc->rmb_base))
return PTR_ERR(qproc->rmb_base);
if (qproc->has_vq6)
halt_cell_cnt++;
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
"qcom,halt-regs", 3, 0, &args);
"qcom,halt-regs", halt_cell_cnt, 0, &args);
if (ret < 0) {
dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
return -EINVAL;
......@@ -1509,6 +1645,52 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
qproc->halt_modem = args.args[1];
qproc->halt_nc = args.args[2];
if (qproc->has_vq6)
qproc->halt_vq6 = args.args[3];
if (qproc->has_qaccept_regs) {
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
"qcom,qaccept-regs",
3, 0, &args);
if (ret < 0) {
dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
return -EINVAL;
}
qproc->qaccept_mdm = args.args[0];
qproc->qaccept_cx = args.args[1];
qproc->qaccept_axi = args.args[2];
}
if (qproc->has_ext_cntl_regs) {
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
"qcom,ext-regs",
2, 0, &args);
if (ret < 0) {
dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
return -EINVAL;
}
qproc->conn_map = syscon_node_to_regmap(args.np);
of_node_put(args.np);
if (IS_ERR(qproc->conn_map))
return PTR_ERR(qproc->conn_map);
qproc->force_clk_on = args.args[0];
qproc->rscc_disable = args.args[1];
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
"qcom,ext-regs",
2, 1, &args);
if (ret < 0) {
dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
return -EINVAL;
}
qproc->axim1_clk_off = args.args[0];
qproc->crypto_clk_off = args.args[1];
}
if (qproc->has_spare_reg) {
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
"qcom,spare-regs",
......@@ -1600,7 +1782,7 @@ static int q6v5_init_reset(struct q6v5 *qproc)
return PTR_ERR(qproc->mss_restart);
}
if (qproc->has_alt_reset || qproc->has_spare_reg) {
if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
"pdc_reset");
if (IS_ERR(qproc->pdc_reset)) {
......@@ -1707,6 +1889,9 @@ static int q6v5_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, qproc);
qproc->has_qaccept_regs = desc->has_qaccept_regs;
qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
qproc->has_vq6 = desc->has_vq6;
qproc->has_spare_reg = desc->has_spare_reg;
ret = q6v5_init_mem(qproc, pdev);
if (ret)
......@@ -1756,14 +1941,6 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->active_reg_count = ret;
ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
desc->active_pd_names);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to attach active power domains\n");
goto free_rproc;
}
qproc->active_pd_count = ret;
ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
desc->proxy_pd_names);
/* Fallback to regulators for old device trees */
......@@ -1773,12 +1950,12 @@ static int q6v5_probe(struct platform_device *pdev)
desc->fallback_proxy_supply);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
goto detach_active_pds;
goto free_rproc;
}
qproc->fallback_proxy_reg_count = ret;
} else if (ret < 0) {
dev_err(&pdev->dev, "Failed to init power domains\n");
goto detach_active_pds;
goto free_rproc;
} else {
qproc->proxy_pd_count = ret;
}
......@@ -1792,7 +1969,7 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->need_mem_protection = desc->need_mem_protection;
qproc->has_mba_logs = desc->has_mba_logs;
ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem",
qcom_msa_handover);
if (ret)
goto detach_proxy_pds;
......@@ -1822,8 +1999,6 @@ static int q6v5_probe(struct platform_device *pdev)
qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
detach_proxy_pds:
q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
detach_active_pds:
q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
free_rproc:
rproc_free(rproc);
......@@ -1837,13 +2012,13 @@ static int q6v5_remove(struct platform_device *pdev)
rproc_del(rproc);
qcom_q6v5_deinit(&qproc->q6v5);
qcom_remove_sysmon_subdev(qproc->sysmon);
qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
rproc_free(rproc);
......@@ -1867,10 +2042,6 @@ static const struct rproc_hexagon_res sc7180_mss = {
"nav",
NULL
},
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"cx",
"mx",
......@@ -1881,9 +2052,40 @@ static const struct rproc_hexagon_res sc7180_mss = {
.has_alt_reset = false,
.has_mba_logs = true,
.has_spare_reg = true,
.has_qaccept_regs = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_SC7180,
};
static const struct rproc_hexagon_res sc7280_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
"xo",
"pka",
NULL
},
.active_clk_names = (char*[]){
"iface",
"offline",
"snoc_axi",
NULL
},
.proxy_pd_names = (char*[]){
"cx",
"mss",
NULL
},
.need_mem_protection = true,
.has_alt_reset = false,
.has_mba_logs = true,
.has_spare_reg = false,
.has_qaccept_regs = true,
.has_ext_cntl_regs = true,
.has_vq6 = true,
.version = MSS_SC7280,
};
static const struct rproc_hexagon_res sdm845_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
......@@ -1903,10 +2105,6 @@ static const struct rproc_hexagon_res sdm845_mss = {
"mnoc_axi",
NULL
},
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"cx",
"mx",
......@@ -1917,6 +2115,9 @@ static const struct rproc_hexagon_res sdm845_mss = {
.has_alt_reset = true,
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_SDM845,
};
......@@ -1945,6 +2146,9 @@ static const struct rproc_hexagon_res msm8998_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8998,
};
......@@ -1976,6 +2180,9 @@ static const struct rproc_hexagon_res msm8996_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8996,
};
......@@ -2018,6 +2225,9 @@ static const struct rproc_hexagon_res msm8916_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8916,
};
......@@ -2068,6 +2278,9 @@ static const struct rproc_hexagon_res msm8974_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8974,
};
......@@ -2078,6 +2291,7 @@ static const struct of_device_id q6v5_of_match[] = {
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
{ .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
{ },
};
......
drivers/remoteproc/qcom_q6v5_pas.c
View file @ bd485d27
......@@ -37,9 +37,9 @@ struct adsp_data {
bool has_aggre2_clk;
bool auto_boot;
char **active_pd_names;
char **proxy_pd_names;
const char *load_state;
const char *ssr_name;
const char *sysmon_name;
int ssctl_id;
......@@ -57,10 +57,8 @@ struct qcom_adsp {
struct regulator *cx_supply;
struct regulator *px_supply;
struct device *active_pds[1];
struct device *proxy_pds[3];
int active_pd_count;
int proxy_pd_count;
int pas_id;
......@@ -149,15 +147,13 @@ static int adsp_start(struct rproc *rproc)
struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
int ret;
qcom_q6v5_prepare(&adsp->q6v5);
ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count);
if (ret < 0)
goto disable_irqs;
ret = qcom_q6v5_prepare(&adsp->q6v5);
if (ret)
return ret;
ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
if (ret < 0)
goto disable_active_pds;
goto disable_irqs;
ret = clk_prepare_enable(adsp->xo);
if (ret)
......@@ -201,8 +197,6 @@ static int adsp_start(struct rproc *rproc)
clk_disable_unprepare(adsp->xo);
disable_proxy_pds:
adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
disable_active_pds:
adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
disable_irqs:
qcom_q6v5_unprepare(&adsp->q6v5);
......@@ -234,7 +228,6 @@ static int adsp_stop(struct rproc *rproc)
if (ret)
dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
handover = qcom_q6v5_unprepare(&adsp->q6v5);
if (handover)
qcom_pas_handover(&adsp->q6v5);
......@@ -456,19 +449,13 @@ static int adsp_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
ret = adsp_pds_attach(&pdev->dev, adsp->active_pds,
desc->active_pd_names);
if (ret < 0)
goto free_rproc;
adsp->active_pd_count = ret;
ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds,
desc->proxy_pd_names);
if (ret < 0)
goto detach_active_pds;
goto free_rproc;
adsp->proxy_pd_count = ret;
ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, desc->load_state,
qcom_pas_handover);
if (ret)
goto detach_proxy_pds;
......@@ -492,8 +479,6 @@ static int adsp_probe(struct platform_device *pdev)
detach_proxy_pds:
adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
detach_active_pds:
adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count);
free_rproc:
rproc_free(rproc);
......@@ -506,6 +491,7 @@ static int adsp_remove(struct platform_device *pdev)
rproc_del(adsp->rproc);
qcom_q6v5_deinit(&adsp->q6v5);
qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
qcom_remove_sysmon_subdev(adsp->sysmon);
qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
......@@ -526,20 +512,29 @@ static const struct adsp_data adsp_resource_init = {
.ssctl_id = 0x14,
};
static const struct adsp_data sdm845_adsp_resource_init = {
.crash_reason_smem = 423,
.firmware_name = "adsp.mdt",
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
.load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
};
static const struct adsp_data sm8150_adsp_resource = {
.crash_reason_smem = 423,
.firmware_name = "adsp.mdt",
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"cx",
NULL
},
.load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
......@@ -551,15 +546,12 @@ static const struct adsp_data sm8250_adsp_resource = {
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
.load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
......@@ -571,21 +563,18 @@ static const struct adsp_data sm8350_adsp_resource = {
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
.load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
};
static const struct adsp_data msm8998_adsp_resource = {
static const struct adsp_data msm8996_adsp_resource = {
.crash_reason_smem = 423,
.firmware_name = "adsp.mdt",
.pas_id = 1,
......@@ -611,20 +600,29 @@ static const struct adsp_data cdsp_resource_init = {
.ssctl_id = 0x17,
};
static const struct adsp_data sdm845_cdsp_resource_init = {
.crash_reason_smem = 601,
.firmware_name = "cdsp.mdt",
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
.load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
};
static const struct adsp_data sm8150_cdsp_resource = {
.crash_reason_smem = 601,
.firmware_name = "cdsp.mdt",
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"cx",
NULL
},
.load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
......@@ -636,14 +634,11 @@ static const struct adsp_data sm8250_cdsp_resource = {
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"cx",
NULL
},
.load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
......@@ -655,14 +650,11 @@ static const struct adsp_data sm8350_cdsp_resource = {
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"cx",
NULL
},
.load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
......@@ -675,15 +667,12 @@ static const struct adsp_data mpss_resource_init = {
.minidump_id = 3,
.has_aggre2_clk = false,
.auto_boot = false,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"cx",
"mss",
NULL
},
.load_state = "modem",
.ssr_name = "mpss",
.sysmon_name = "modem",
.ssctl_id = 0x12,
......@@ -695,14 +684,11 @@ static const struct adsp_data sc8180x_mpss_resource = {
.pas_id = 4,
.has_aggre2_clk = false,
.auto_boot = false,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"cx",
NULL
},
.load_state = "modem",
.ssr_name = "mpss",
.sysmon_name = "modem",
.ssctl_id = 0x12,
......@@ -714,6 +700,10 @@ static const struct adsp_data slpi_resource_init = {
.pas_id = 12,
.has_aggre2_clk = true,
.auto_boot = true,
.proxy_pd_names = (char*[]){
"ssc_cx",
NULL
},
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
......@@ -725,15 +715,12 @@ static const struct adsp_data sm8150_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
.load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
......@@ -745,15 +732,12 @@ static const struct adsp_data sm8250_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
.load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
......@@ -765,35 +749,17 @@ static const struct adsp_data sm8350_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
.active_pd_names = (char*[]){
"load_state",
NULL
},
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
.load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
};
static const struct adsp_data msm8998_slpi_resource = {
.crash_reason_smem = 424,
.firmware_name = "slpi.mdt",
.pas_id = 12,
.has_aggre2_clk = true,
.auto_boot = true,
.proxy_pd_names = (char*[]){
"ssc_cx",
NULL
},
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
};
static const struct adsp_data wcss_resource_init = {
.crash_reason_smem = 421,
.firmware_name = "wcnss.mdt",
......@@ -822,20 +788,21 @@ static const struct adsp_data sdx55_mpss_resource = {
static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
{ .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
{ .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource},
{ .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
{ .compatible = "qcom,msm8998-adsp-pas", .data = &msm8998_adsp_resource},
{ .compatible = "qcom,msm8998-slpi-pas", .data = &msm8998_slpi_resource},
{ .compatible = "qcom,msm8998-adsp-pas", .data = &msm8996_adsp_resource},
{ .compatible = "qcom,msm8998-slpi-pas", .data = &slpi_resource_init},
{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
{ .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init},
{ .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init},
{ .compatible = "qcom,sc8180x-adsp-pas", .data = &sm8150_adsp_resource},
{ .compatible = "qcom,sc8180x-cdsp-pas", .data = &sm8150_cdsp_resource},
{ .compatible = "qcom,sc8180x-mpss-pas", .data = &sc8180x_mpss_resource},
{ .compatible = "qcom,sdm660-adsp-pas", .data = &adsp_resource_init},
{ .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
{ .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
{ .compatible = "qcom,sdm845-adsp-pas", .data = &sdm845_adsp_resource_init},
{ .compatible = "qcom,sdm845-cdsp-pas", .data = &sdm845_cdsp_resource_init},
{ .compatible = "qcom,sdx55-mpss-pas", .data = &sdx55_mpss_resource},
{ .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource},
{ .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource},
......
drivers/remoteproc/qcom_q6v5_wcss.c
View file @ bd485d27
......@@ -1044,8 +1044,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem,
NULL);
ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, NULL);
if (ret)
goto free_rproc;
......@@ -1074,7 +1073,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
static int q6v5_wcss_remove(struct platform_device *pdev)
{
struct rproc *rproc = platform_get_drvdata(pdev);
struct q6v5_wcss *wcss = rproc->priv;
qcom_q6v5_deinit(&wcss->q6v5);
rproc_del(rproc);
rproc_free(rproc);
......
drivers/remoteproc/qcom_wcnss.c
View file @ bd485d27
......@@ -25,7 +25,6 @@
#include <linux/soc/qcom/mdt_loader.h>
#include <linux/soc/qcom/smem.h>
#include <linux/soc/qcom/smem_state.h>
#include <linux/rpmsg/qcom_smd.h>
#include "qcom_common.h"
#include "remoteproc_internal.h"
......
drivers/remoteproc/remoteproc_core.c
View file @ bd485d27
......@@ -556,9 +556,6 @@ static int rproc_handle_vdev(struct rproc *rproc, void *ptr,
/* Initialise vdev subdevice */
snprintf(name, sizeof(name), "vdev%dbuffer", rvdev->index);
rvdev->dev.parent = &rproc->dev;
ret = copy_dma_range_map(&rvdev->dev, rproc->dev.parent);
if (ret)
return ret;
rvdev->dev.release = rproc_rvdev_release;
dev_set_name(&rvdev->dev, "%s#%s", dev_name(rvdev->dev.parent), name);
dev_set_drvdata(&rvdev->dev, rvdev);
......@@ -568,6 +565,11 @@ static int rproc_handle_vdev(struct rproc *rproc, void *ptr,
put_device(&rvdev->dev);
return ret;
}
ret = copy_dma_range_map(&rvdev->dev, rproc->dev.parent);
if (ret)
goto free_rvdev;
/* Make device dma capable by inheriting from parent's capabilities */
set_dma_ops(&rvdev->dev, get_dma_ops(rproc->dev.parent));
......
drivers/remoteproc/remoteproc_coredump.c
View file @ bd485d27
......@@ -152,8 +152,8 @@ static void rproc_copy_segment(struct rproc *rproc, void *dest,
struct rproc_dump_segment *segment,
size_t offset, size_t size)
{
bool is_iomem = false;
void *ptr;
bool is_iomem;
if (segment->dump) {
segment->dump(rproc, segment, dest, offset, size);
......
drivers/remoteproc/remoteproc_elf_loader.c
View file @ bd485d27
......@@ -178,8 +178,8 @@ int rproc_elf_load_segments(struct rproc *rproc, const struct firmware *fw)
u64 filesz = elf_phdr_get_p_filesz(class, phdr);
u64 offset = elf_phdr_get_p_offset(class, phdr);
u32 type = elf_phdr_get_p_type(class, phdr);
bool is_iomem = false;
void *ptr;
bool is_iomem;
if (type != PT_LOAD)
continue;
......@@ -220,7 +220,7 @@ int rproc_elf_load_segments(struct rproc *rproc, const struct firmware *fw)
/* put the segment where the remote processor expects it */
if (filesz) {
if (is_iomem)
memcpy_fromio(ptr, (void __iomem *)(elf_data + offset), filesz);
memcpy_toio((void __iomem *)ptr, elf_data + offset, filesz);
else
memcpy(ptr, elf_data + offset, filesz);
}
......
drivers/remoteproc/remoteproc_virtio.c
View file @ bd485d27
......@@ -23,6 +23,18 @@
#include "remoteproc_internal.h"
static struct rproc_vdev *vdev_to_rvdev(struct virtio_device *vdev)
{
return container_of(vdev->dev.parent, struct rproc_vdev, dev);
}
static struct rproc *vdev_to_rproc(struct virtio_device *vdev)
{
struct rproc_vdev *rvdev = vdev_to_rvdev(vdev);
return rvdev->rproc;
}
/* kick the remote processor, and let it know which virtqueue to poke at */
static bool rproc_virtio_notify(struct virtqueue *vq)
{
......
drivers/remoteproc/ti_k3_dsp_remoteproc.c
View file @ bd485d27
......@@ -481,7 +481,7 @@ static int k3_dsp_reserved_mem_init(struct k3_dsp_rproc *kproc)
return -EINVAL;
}
if (num_rmems < 2) {
dev_err(dev, "device needs atleast two memory regions to be defined, num = %d\n",
dev_err(dev, "device needs at least two memory regions to be defined, num = %d\n",
num_rmems);
return -EINVAL;
}
......
drivers/remoteproc/ti_k3_r5_remoteproc.c
View file @ bd485d27
......@@ -876,7 +876,7 @@ static int k3_r5_reserved_mem_init(struct k3_r5_rproc *kproc)
return -EINVAL;
}
if (num_rmems < 2) {
dev_err(dev, "device needs atleast two memory regions to be defined, num = %d\n",
dev_err(dev, "device needs at least two memory regions to be defined, num = %d\n",
num_rmems);
return -EINVAL;
}
......
drivers/rpmsg/rpmsg_char.c
View file @ bd485d27
......@@ -22,8 +22,6 @@
#include <linux/uaccess.h>
#include <uapi/linux/rpmsg.h>
#include "rpmsg_internal.h"
#define RPMSG_DEV_MAX (MINORMASK + 1)
static dev_t rpmsg_major;
......
include/linux/remoteproc.h
View file @ bd485d27
......@@ -684,18 +684,6 @@ int rproc_coredump_add_custom_segment(struct rproc *rproc,
void *priv);
int rproc_coredump_set_elf_info(struct rproc *rproc, u8 class, u16 machine);
static inline struct rproc_vdev *vdev_to_rvdev(struct virtio_device *vdev)
{
return container_of(vdev->dev.parent, struct rproc_vdev, dev);
}
static inline struct rproc *vdev_to_rproc(struct virtio_device *vdev)
{
struct rproc_vdev *rvdev = vdev_to_rvdev(vdev);
return rvdev->rproc;
}
void rproc_add_subdev(struct rproc *rproc, struct rproc_subdev *subdev);
void rproc_remove_subdev(struct rproc *rproc, struct rproc_subdev *subdev);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7