Commit be046fc9 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Kleber Sacilotto de Souza

memory: tegra: Apply interrupts mask per SoC

BugLink: https://bugs.launchpad.net/bugs/1791953

[ Upstream commit 1c74d5c0 ]

Currently we are enabling handling of interrupts specific to Tegra124+
which happen to overlap with previous generations. Let's specify
interrupts mask per SoC generation for consistency and in a preparation
of squashing of Tegra20 driver into the common one that will enable
handling of GART faults which may be undesirable by newer generations.
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarSasha Levin <alexander.levin@microsoft.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarStefan Bader <stefan.bader@canonical.com>
Signed-off-by: default avatarKleber Sacilotto de Souza <kleber.souza@canonical.com>
parent c853d8b4
...@@ -20,14 +20,6 @@ ...@@ -20,14 +20,6 @@
#include "mc.h" #include "mc.h"
#define MC_INTSTATUS 0x000 #define MC_INTSTATUS 0x000
#define MC_INT_DECERR_MTS (1 << 16)
#define MC_INT_SECERR_SEC (1 << 13)
#define MC_INT_DECERR_VPR (1 << 12)
#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
#define MC_INT_INVALID_SMMU_PAGE (1 << 10)
#define MC_INT_ARBITRATION_EMEM (1 << 9)
#define MC_INT_SECURITY_VIOLATION (1 << 8)
#define MC_INT_DECERR_EMEM (1 << 6)
#define MC_INTMASK 0x004 #define MC_INTMASK 0x004
...@@ -248,13 +240,11 @@ static const char *const error_names[8] = { ...@@ -248,13 +240,11 @@ static const char *const error_names[8] = {
static irqreturn_t tegra_mc_irq(int irq, void *data) static irqreturn_t tegra_mc_irq(int irq, void *data)
{ {
struct tegra_mc *mc = data; struct tegra_mc *mc = data;
unsigned long status, mask; unsigned long status;
unsigned int bit; unsigned int bit;
/* mask all interrupts to avoid flooding */ /* mask all interrupts to avoid flooding */
mask = mc_readl(mc, MC_INTMASK); status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
status = mc_readl(mc, MC_INTSTATUS) & mask;
if (!status) if (!status)
return IRQ_NONE; return IRQ_NONE;
...@@ -349,7 +339,6 @@ static int tegra_mc_probe(struct platform_device *pdev) ...@@ -349,7 +339,6 @@ static int tegra_mc_probe(struct platform_device *pdev)
const struct of_device_id *match; const struct of_device_id *match;
struct resource *res; struct resource *res;
struct tegra_mc *mc; struct tegra_mc *mc;
u32 value;
int err; int err;
match = of_match_node(tegra_mc_of_match, pdev->dev.of_node); match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
...@@ -417,11 +406,7 @@ static int tegra_mc_probe(struct platform_device *pdev) ...@@ -417,11 +406,7 @@ static int tegra_mc_probe(struct platform_device *pdev)
WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n"); WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | mc_writel(mc, mc->soc->intmask, MC_INTMASK);
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM;
mc_writel(mc, value, MC_INTMASK);
return 0; return 0;
} }
......
...@@ -14,6 +14,15 @@ ...@@ -14,6 +14,15 @@
#include <soc/tegra/mc.h> #include <soc/tegra/mc.h>
#define MC_INT_DECERR_MTS (1 << 16)
#define MC_INT_SECERR_SEC (1 << 13)
#define MC_INT_DECERR_VPR (1 << 12)
#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
#define MC_INT_INVALID_SMMU_PAGE (1 << 10)
#define MC_INT_ARBITRATION_EMEM (1 << 9)
#define MC_INT_SECURITY_VIOLATION (1 << 8)
#define MC_INT_DECERR_EMEM (1 << 6)
static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset) static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
{ {
return readl(mc->regs + offset); return readl(mc->regs + offset);
......
...@@ -930,4 +930,6 @@ const struct tegra_mc_soc tegra114_mc_soc = { ...@@ -930,4 +930,6 @@ const struct tegra_mc_soc tegra114_mc_soc = {
.atom_size = 32, .atom_size = 32,
.client_id_mask = 0x7f, .client_id_mask = 0x7f,
.smmu = &tegra114_smmu_soc, .smmu = &tegra114_smmu_soc,
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
MC_INT_DECERR_EMEM,
}; };
...@@ -1019,6 +1019,9 @@ const struct tegra_mc_soc tegra124_mc_soc = { ...@@ -1019,6 +1019,9 @@ const struct tegra_mc_soc tegra124_mc_soc = {
.smmu = &tegra124_smmu_soc, .smmu = &tegra124_smmu_soc,
.emem_regs = tegra124_mc_emem_regs, .emem_regs = tegra124_mc_emem_regs,
.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs), .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
}; };
#endif /* CONFIG_ARCH_TEGRA_124_SOC */ #endif /* CONFIG_ARCH_TEGRA_124_SOC */
...@@ -1041,5 +1044,8 @@ const struct tegra_mc_soc tegra132_mc_soc = { ...@@ -1041,5 +1044,8 @@ const struct tegra_mc_soc tegra132_mc_soc = {
.atom_size = 32, .atom_size = 32,
.client_id_mask = 0x7f, .client_id_mask = 0x7f,
.smmu = &tegra132_smmu_soc, .smmu = &tegra132_smmu_soc,
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
}; };
#endif /* CONFIG_ARCH_TEGRA_132_SOC */ #endif /* CONFIG_ARCH_TEGRA_132_SOC */
...@@ -1077,4 +1077,7 @@ const struct tegra_mc_soc tegra210_mc_soc = { ...@@ -1077,4 +1077,7 @@ const struct tegra_mc_soc tegra210_mc_soc = {
.atom_size = 64, .atom_size = 64,
.client_id_mask = 0xff, .client_id_mask = 0xff,
.smmu = &tegra210_smmu_soc, .smmu = &tegra210_smmu_soc,
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
}; };
...@@ -952,4 +952,6 @@ const struct tegra_mc_soc tegra30_mc_soc = { ...@@ -952,4 +952,6 @@ const struct tegra_mc_soc tegra30_mc_soc = {
.atom_size = 16, .atom_size = 16,
.client_id_mask = 0x7f, .client_id_mask = 0x7f,
.smmu = &tegra30_smmu_soc, .smmu = &tegra30_smmu_soc,
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
MC_INT_DECERR_EMEM,
}; };
...@@ -99,6 +99,8 @@ struct tegra_mc_soc { ...@@ -99,6 +99,8 @@ struct tegra_mc_soc {
u8 client_id_mask; u8 client_id_mask;
const struct tegra_smmu_soc *smmu; const struct tegra_smmu_soc *smmu;
u32 intmask;
}; };
struct tegra_mc { struct tegra_mc {
......
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