Commit bf97b276 authored by Daniel Vetter's avatar Daniel Vetter

drm/i915: implement w/a for incorrect guarband clipping

According to Bsepc, this should be set by default, but isn't. See vo1c.4
"Render Engine Command Streamer", Section 1.1.14.3 "3D_CHICKEN3"

Bspec also says that we always need to set all mask bits.

v2: Add comment about the mask bits wtf.
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 48ecfa10
...@@ -497,6 +497,7 @@ ...@@ -497,6 +497,7 @@
*/ */
# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
#define _3D_CHICKEN3 0x02090 #define _3D_CHICKEN3 0x02090
#define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5)
#define MI_MODE 0x0209c #define MI_MODE 0x0209c
# define VS_TIMER_DISPATCH (1 << 6) # define VS_TIMER_DISPATCH (1 << 6)
......
...@@ -8897,6 +8897,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) ...@@ -8897,6 +8897,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
GEN6_RCCUNIT_CLOCK_GATE_DISABLE); GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
/* Bspec says we need to always set all mask bits. */
I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
_3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
/* /*
* According to the spec the following bits should be * According to the spec the following bits should be
* set in order to enable memory self-refresh and fbc: * set in order to enable memory self-refresh and fbc:
......
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