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Commit bfc69bdb authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
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pinctrl: renesas: rzg2l: Add RZ/G2UL support 

RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin
definitions are different compared to RZ/G2L.

This patch adds a new compatible to take care of these differences by
adding r9a07g043_data with r9a07g043_gpio_configs and
rzg2l_dedicated_pins.common.
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220401180230.19950-1-biju.das.jz@bp.renesas.comSigned-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent ff06501c
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Showing with 124 additions and 81 deletions
drivers/pinctrl/renesas/Kconfig
View file @ bfc69bdb
...@@ -38,6 +38,7 @@ config PINCTRL_RENESAS ...@@ -38,6 +38,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0 select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0 select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0
select PINCTRL_RZG2L if ARCH_R9A07G043
select PINCTRL_RZG2L if ARCH_R9A07G044 select PINCTRL_RZG2L if ARCH_R9A07G044
select PINCTRL_RZG2L if ARCH_R9A07G054 select PINCTRL_RZG2L if ARCH_R9A07G054
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
...@@ -184,14 +185,14 @@ config PINCTRL_RZA2 ...@@ -184,14 +185,14 @@ config PINCTRL_RZA2
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_RZG2L config PINCTRL_RZG2L
bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST bool "pin control support for RZ/{G2L,G2UL,V2L}" if COMPILE_TEST
depends on OF depends on OF
select GPIOLIB select GPIOLIB
select GENERIC_PINCTRL_GROUPS select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF select GENERIC_PINCONF
help help
This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L} This selects GPIO and pinctrl driver for Renesas RZ/{G2L,G2UL,V2L}
platforms. platforms.
config PINCTRL_PFC_R8A77470 config PINCTRL_PFC_R8A77470
......
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View file @ bfc69bdb
...@@ -996,83 +996,112 @@ static const u32 rzg2l_gpio_configs[] = { ...@@ -996,83 +996,112 @@ static const u32 rzg2l_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
}; };
static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { static const u32 r9a07g043_gpio_configs[] = {
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
(PIN_CFG_SR | PIN_CFG_IOLH_A | PIN_CFG_IEN)) }, RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
(PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, };
{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, static struct {
{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, struct rzg2l_dedicated_configs common[35];
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, struct rzg2l_dedicated_configs rzg2l_pins[7];
{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, } rzg2l_dedicated_pins = {
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, .common = {
{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, (PIN_CFG_SR | PIN_CFG_IOLH_A | PIN_CFG_IEN)) },
{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
{ "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
{ "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
},
.rzg2l_pins = {
{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
}
}; };
static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
...@@ -1250,15 +1279,28 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) ...@@ -1250,15 +1279,28 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
return 0; return 0;
} }
static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs,
.dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
};
static struct rzg2l_pinctrl_data r9a07g044_data = { static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pins = rzg2l_gpio_names, .port_pins = rzg2l_gpio_names,
.port_pin_configs = rzg2l_gpio_configs, .port_pin_configs = rzg2l_gpio_configs,
.dedicated_pins = rzg2l_dedicated_pins, .dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins), .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
}; };
static const struct of_device_id rzg2l_pinctrl_of_table[] = { static const struct of_device_id rzg2l_pinctrl_of_table[] = {
{
.compatible = "renesas,r9a07g043-pinctrl",
.data = &r9a07g043_data,
},
{ {
.compatible = "renesas,r9a07g044-pinctrl", .compatible = "renesas,r9a07g044-pinctrl",
.data = &r9a07g044_data, .data = &r9a07g044_data,
......
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