Commit bfe890e5 authored by Philipp Hortmann's avatar Philipp Hortmann Committed by Greg Kroah-Hartman

staging: rtl8192e: Join constants Rtl819XMACPHY_.. with Rtl8192PciE..

Join constants Rtl819XMACPHY_Array with Rtl8192PciEMACPHY_Array to
RTL8192E_MACPHY_ARR to improve readability.
Signed-off-by: default avatarPhilipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/6e5609e6b31892671d203c9da1a947bd42b70c37.1678814935.git.philipp.g.hortmann@gmail.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 85246543
...@@ -292,7 +292,7 @@ void rtl92e_config_mac(struct net_device *dev) ...@@ -292,7 +292,7 @@ void rtl92e_config_mac(struct net_device *dev)
} else { } else {
dwArrayLen = RTL8192E_MACPHY_ARR_LEN; dwArrayLen = RTL8192E_MACPHY_ARR_LEN;
pdwArray = Rtl819XMACPHY_Array; pdwArray = RTL8192E_MACPHY_ARR;
} }
for (i = 0; i < dwArrayLen; i += 3) { for (i = 0; i < dwArrayLen; i += 3) {
if (pdwArray[i] == 0x318) if (pdwArray[i] == 0x318)
......
...@@ -9,7 +9,6 @@ ...@@ -9,7 +9,6 @@
#define MAX_DOZE_WAITING_TIMES_9x 64 #define MAX_DOZE_WAITING_TIMES_9x 64
#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array #define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array #define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array #define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
......
...@@ -325,7 +325,7 @@ u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN] = { ...@@ -325,7 +325,7 @@ u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN] = {
0x007, 0x00000700, 0x007, 0x00000700,
}; };
u32 Rtl8192PciEMACPHY_Array[] = { u32 RTL8192E_MACPHY_ARR[] = {
0x03c, 0xffff0000, 0x00000f0f, 0x03c, 0xffff0000, 0x00000f0f,
0x340, 0xffffffff, 0x161a1a1a, 0x340, 0xffffffff, 0x161a1a1a,
0x344, 0xffffffff, 0x12121416, 0x344, 0xffffffff, 0x12121416,
......
...@@ -18,7 +18,7 @@ extern u32 Rtl8192PciERadioA_Array[RTL8192E_RADIO_A_ARR_LEN]; ...@@ -18,7 +18,7 @@ extern u32 Rtl8192PciERadioA_Array[RTL8192E_RADIO_A_ARR_LEN];
#define RTL8192E_RADIO_B_ARR_LEN 78 #define RTL8192E_RADIO_B_ARR_LEN 78
extern u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN]; extern u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN];
#define RTL8192E_MACPHY_ARR_LEN 18 #define RTL8192E_MACPHY_ARR_LEN 18
extern u32 Rtl8192PciEMACPHY_Array[RTL8192E_MACPHY_ARR_LEN]; extern u32 RTL8192E_MACPHY_ARR[RTL8192E_MACPHY_ARR_LEN];
#define RTL8192E_MACPHY_ARR_PG_LEN 30 #define RTL8192E_MACPHY_ARR_PG_LEN 30
extern u32 RTL8192E_MACPHY_ARR_PG[RTL8192E_MACPHY_ARR_PG_LEN]; extern u32 RTL8192E_MACPHY_ARR_PG[RTL8192E_MACPHY_ARR_PG_LEN];
#define RTL8192E_AGCTAB_ARR_LEN 384 #define RTL8192E_AGCTAB_ARR_LEN 384
......
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