Commit c1282ae8 authored by Hanks Chen's avatar Hanks Chen Committed by Linus Walleij

pinctrl: mediatek: add mt6779 eint support

add driver setting to support mt6779 eint
Signed-off-by: default avatarMars Cheng <mars.cheng@mediatek.com>
Signed-off-by: default avatarHanks Chen <hanks.chen@mediatek.com>
Acked-by: default avatarSean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/1595503197-15246-6-git-send-email-hanks.chen@mediatek.comSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 920e469e
...@@ -732,11 +732,19 @@ static const char * const mt6779_pinctrl_register_base_names[] = { ...@@ -732,11 +732,19 @@ static const char * const mt6779_pinctrl_register_base_names[] = {
"iocfg_rt", "iocfg_lt", "iocfg_tl", "iocfg_rt", "iocfg_lt", "iocfg_tl",
}; };
static const struct mtk_eint_hw mt6779_eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 195,
.db_cnt = 13,
};
static const struct mtk_pin_soc mt6779_data = { static const struct mtk_pin_soc mt6779_data = {
.reg_cal = mt6779_reg_cals, .reg_cal = mt6779_reg_cals,
.pins = mtk_pins_mt6779, .pins = mtk_pins_mt6779,
.npins = ARRAY_SIZE(mtk_pins_mt6779), .npins = ARRAY_SIZE(mtk_pins_mt6779),
.ngrps = ARRAY_SIZE(mtk_pins_mt6779), .ngrps = ARRAY_SIZE(mtk_pins_mt6779),
.eint_hw = &mt6779_eint_hw,
.gpio_m = 0, .gpio_m = 0,
.ies_present = true, .ies_present = true,
.base_names = mt6779_pinctrl_register_base_names, .base_names = mt6779_pinctrl_register_base_names,
......
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