amdgpu/dc: another round of dce/dcn construct cleanups.

This removes any remaining pointless return codepaths from the
DCE code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

@@ -142,13 +142,11 @@ void dce100_set_bandwidth(
 
 /**************************************************************************/
 
-bool dce100_hw_sequencer_construct(struct dc *dc)
+void dce100_hw_sequencer_construct(struct dc *dc)
 {
 	dce110_hw_sequencer_construct(dc);
 
 	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
 	dc->hwss.set_bandwidth = dce100_set_bandwidth;
-
-	return true;
 }
 

drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h

@@ -31,7 +31,7 @@
 struct dc;
 struct dc_state;
 
-bool dce100_hw_sequencer_construct(struct dc *dc);
+void dce100_hw_sequencer_construct(struct dc *dc);
 
 void dce100_set_bandwidth(
 		struct dc *dc,

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

@@ -909,9 +909,7 @@ static bool construct(
 		goto res_create_fail;
 
 	/* Create hardware sequencer */
-	if (!dce100_hw_sequencer_construct(dc))
-		goto res_create_fail;
-
+	dce100_hw_sequencer_construct(dc);
 	return true;
 
 res_create_fail:

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

@@ -393,12 +393,8 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx)
 	if (!cp110)
 		return NULL;
 
-	if (dce110_compressor_construct(cp110, ctx))
+	dce110_compressor_construct(cp110, ctx);
 	return &cp110->base;
-
-	BREAK_TO_DEBUGGER();
-	kfree(cp110);
-	return NULL;
 }
 
 void dce110_compressor_destroy(struct compressor **compressor)
@@ -485,7 +481,7 @@ static const struct compressor_funcs dce110_compressor_funcs = {
 };
 
 
-bool dce110_compressor_construct(struct dce110_compressor *compressor,
+void dce110_compressor_construct(struct dce110_compressor *compressor,
 	struct dc_context *ctx)
 {
 
@@ -522,6 +518,5 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor,
 	compressor->base.funcs = &dce110_compressor_funcs;
 
 #endif
-	return true;
 }
 

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

@@ -42,7 +42,7 @@ struct dce110_compressor {
 
 struct compressor *dce110_compressor_create(struct dc_context *ctx);
 
-bool dce110_compressor_construct(struct dce110_compressor *cp110,
+void dce110_compressor_construct(struct dce110_compressor *cp110,
 	struct dc_context *ctx);
 
 void dce110_compressor_destroy(struct compressor **cp);

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

@@ -2723,10 +2723,8 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 
 };
 
-bool dce110_hw_sequencer_construct(struct dc *dc)
+void dce110_hw_sequencer_construct(struct dc *dc)
 {
 	dc->hwss = dce110_funcs;
-
-	return true;
 }
 

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

@@ -33,7 +33,7 @@ struct dc;
 struct dc_state;
 struct dm_pp_display_configuration;
 
-bool dce110_hw_sequencer_construct(struct dc *dc);
+void dce110_hw_sequencer_construct(struct dc *dc);
 
 enum dc_status dce110_apply_ctx_to_hw(
 		struct dc *dc,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c

@@ -44,13 +44,11 @@ static const struct opp_funcs funcs = {
 				dce110_opp_program_bit_depth_reduction
 };
 
-bool dce110_opp_v_construct(struct dce110_opp *opp110,
+void dce110_opp_v_construct(struct dce110_opp *opp110,
 	struct dc_context *ctx)
 {
 	opp110->base.funcs = &funcs;
 
 	opp110->base.ctx = ctx;
-
-	return true;
 }
 

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h

@@ -29,7 +29,7 @@
 #include "opp.h"
 #include "core_types.h"
 
-bool dce110_opp_v_construct(struct dce110_opp *opp110,
+void dce110_opp_v_construct(struct dce110_opp *opp110,
 	struct dc_context *ctx);
 
 /* underlay callbacks */

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

@@ -1041,8 +1041,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
 		(dce110_oppv == NULL))
 			return false;
 
-	if (!dce110_opp_v_construct(dce110_oppv, ctx))
-		return false;
+	dce110_opp_v_construct(dce110_oppv, ctx);
 
 	dce110_timing_generator_v_construct(dce110_tgv, ctx);
 	dce110_mem_input_v_construct(dce110_miv, ctx);
@@ -1292,8 +1291,7 @@ static bool construct(
 		goto res_create_fail;
 
 	/* Create hardware sequencer */
-	if (!dce110_hw_sequencer_construct(dc))
-		goto res_create_fail;
+	dce110_hw_sequencer_construct(dc);
 
 	dc->caps.max_planes =  pool->base.pipe_count;
 

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

@@ -668,13 +668,10 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = {
 				dce110_timing_generator_v_enable_advanced_request
 };
 
-bool dce110_timing_generator_v_construct(
+void dce110_timing_generator_v_construct(
 	struct dce110_timing_generator *tg110,
 	struct dc_context *ctx)
 {
-	if (!tg110)
-		return false;
-
 	tg110->controller_id = CONTROLLER_ID_UNDERLAY0;
 
 	tg110->base.funcs = &dce110_tg_v_funcs;
@@ -688,6 +685,4 @@ bool dce110_timing_generator_v_construct(
 	tg110->min_h_blank = 56;
 	tg110->min_h_front_porch = 4;
 	tg110->min_h_back_porch = 4;
-
-	return true;
 }

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h

@@ -26,7 +26,7 @@
 #ifndef __DC_TIMING_GENERATOR_V_DCE110_H__
 #define __DC_TIMING_GENERATOR_V_DCE110_H__
 
-bool dce110_timing_generator_v_construct(
+void dce110_timing_generator_v_construct(
 	struct dce110_timing_generator *tg110,
 	struct dc_context *ctx);
 

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

@@ -791,7 +791,7 @@ void dce112_compressor_set_fbc_invalidation_triggers(
 	dm_write_reg(compressor->ctx, addr, value);
 }
 
-bool dce112_compressor_construct(struct dce112_compressor *compressor,
+void dce112_compressor_construct(struct dce112_compressor *compressor,
 	struct dc_context *ctx)
 {
 	struct dc_bios *bp = ctx->dc_bios;
@@ -833,7 +833,6 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor,
 		compressor->base.embedded_panel_v_size =
 			panel_info.lcd_timing.vertical_addressable;
 	}
-	return true;
 }
 
 struct compressor *dce112_compressor_create(struct dc_context *ctx)
@@ -844,12 +843,8 @@ struct compressor *dce112_compressor_create(struct dc_context *ctx)
 	if (!cp110)
 		return NULL;
 
-	if (dce112_compressor_construct(cp110, ctx))
+	dce112_compressor_construct(cp110, ctx);
 	return &cp110->base;
-
-	BREAK_TO_DEBUGGER();
-	kfree(cp110);
-	return NULL;
 }
 
 void dce112_compressor_destroy(struct compressor **compressor)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

@@ -42,7 +42,7 @@ struct dce112_compressor {
 
 struct compressor *dce112_compressor_create(struct dc_context *ctx);
 
-bool dce112_compressor_construct(struct dce112_compressor *cp110,
+void dce112_compressor_construct(struct dce112_compressor *cp110,
 	struct dc_context *ctx);
 
 void dce112_compressor_destroy(struct compressor **cp);

drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

@@ -152,14 +152,12 @@ static bool dce112_enable_display_power_gating(
 		return false;
 }
 
-bool dce112_hw_sequencer_construct(struct dc *dc)
+void dce112_hw_sequencer_construct(struct dc *dc)
 {
 	/* All registers used by dce11.2 match those in dce11 in offset and
 	 * structure
 	 */
 	dce110_hw_sequencer_construct(dc);
 	dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
-
-	return true;
 }
 

drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h

@@ -30,7 +30,7 @@
 
 struct dc;
 
-bool dce112_hw_sequencer_construct(struct dc *dc);
+void dce112_hw_sequencer_construct(struct dc *dc);
 
 #endif /* __DC_HWSS_DCE112_H__ */
 

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

@@ -1256,8 +1256,7 @@ static bool construct(
 	dc->caps.max_planes =  pool->base.pipe_count;
 
 	/* Create hardware sequencer */
-	if (!dce112_hw_sequencer_construct(dc))
-		goto res_create_fail;
+	dce112_hw_sequencer_construct(dc);
 
 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
 

drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

@@ -245,7 +245,7 @@ static void dce120_update_dchub(
 
 
 
-bool dce120_hw_sequencer_construct(struct dc *dc)
+void dce120_hw_sequencer_construct(struct dc *dc)
 {
 	/* All registers used by dce11.2 match those in dce11 in offset and
 	 * structure
@@ -253,7 +253,5 @@ bool dce120_hw_sequencer_construct(struct dc *dc)
 	dce110_hw_sequencer_construct(dc);
 	dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
 	dc->hwss.update_dchub = dce120_update_dchub;
-
-	return true;
 }
 

drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h

@@ -30,7 +30,7 @@
 
 struct dc;
 
-bool dce120_hw_sequencer_construct(struct dc *dc);
+void dce120_hw_sequencer_construct(struct dc *dc);
 
 #endif /* __DC_HWSS_DCE112_H__ */
 

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

@@ -429,12 +429,8 @@ static struct timing_generator *dce120_timing_generator_create(
 	if (!tg110)
 		return NULL;
 
-	if (dce120_timing_generator_construct(tg110, ctx, instance, offsets))
+	dce120_timing_generator_construct(tg110, ctx, instance, offsets);
 	return &tg110->base;
-
-	BREAK_TO_DEBUGGER();
-	kfree(tg110);
-	return NULL;
 }
 
 static void dce120_transform_destroy(struct transform **xfm)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

@@ -1143,15 +1143,12 @@ static const struct timing_generator_funcs dce120_tg_funcs = {
 };
 
 
-bool dce120_timing_generator_construct(
+void dce120_timing_generator_construct(
 	struct dce110_timing_generator *tg110,
 	struct dc_context *ctx,
 	uint32_t instance,
 	const struct dce110_timing_generator_offsets *offsets)
 {
-	if (!tg110)
-			return false;
-
 	tg110->controller_id = CONTROLLER_ID_D0 + instance;
 	tg110->base.inst = instance;
 
@@ -1175,6 +1172,4 @@ bool dce120_timing_generator_construct(
 	tg110->min_h_sync_width = 8;
 	tg110->min_v_sync_width = 1;
 	tg110->min_v_blank = 3;
-
-	return true;
 }

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h

@@ -32,7 +32,7 @@
 #include "dce110/dce110_timing_generator.h"
 
 
-bool dce120_timing_generator_construct(
+void dce120_timing_generator_construct(
 	struct dce110_timing_generator *tg110,
 	struct dc_context *ctx,
 	uint32_t instance,

drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c

@@ -771,7 +771,7 @@ void dce80_compressor_set_fbc_invalidation_triggers(
 	dm_write_reg(compressor->ctx, addr, value);
 }
 
-bool dce80_compressor_construct(struct dce80_compressor *compressor,
+void dce80_compressor_construct(struct dce80_compressor *compressor,
 	struct dc_context *ctx)
 {
 	struct dc_bios *bp = ctx->dc_bios;
@@ -813,7 +813,6 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor,
 		compressor->base.embedded_panel_v_size =
 			panel_info.lcd_timing.vertical_addressable;
 	}
-	return true;
 }
 
 struct compressor *dce80_compressor_create(struct dc_context *ctx)
@@ -824,12 +823,8 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx)
 	if (!cp80)
 		return NULL;
 
-	if (dce80_compressor_construct(cp80, ctx))
+	dce80_compressor_construct(cp80, ctx);
 	return &cp80->base;
-
-	BREAK_TO_DEBUGGER();
-	kfree(cp80);
-	return NULL;
 }
 
 void dce80_compressor_destroy(struct compressor **compressor)

drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h

@@ -42,7 +42,7 @@ struct dce80_compressor {
 
 struct compressor *dce80_compressor_create(struct dc_context *ctx);
 
-bool dce80_compressor_construct(struct dce80_compressor *cp80,
+void dce80_compressor_construct(struct dce80_compressor *cp80,
 		struct dc_context *ctx);
 
 void dce80_compressor_destroy(struct compressor **cp);

drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c

@@ -106,14 +106,12 @@ static bool dce80_enable_display_power_gating(
 		return false;
 }
 
-bool dce80_hw_sequencer_construct(struct dc *dc)
+void dce80_hw_sequencer_construct(struct dc *dc)
 {
 	dce110_hw_sequencer_construct(dc);
 
 	dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
 	dc->hwss.pipe_control_lock = dce_pipe_control_lock;
 	dc->hwss.set_bandwidth = dce100_set_bandwidth;
-
-	return true;
 }
 

drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h

@@ -30,7 +30,7 @@
 
 struct dc;
 
-bool dce80_hw_sequencer_construct(struct dc *dc);
+void dce80_hw_sequencer_construct(struct dc *dc);
 
 #endif /* __DC_HWSS_DCE80_H__ */
 

drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

@@ -910,8 +910,7 @@ static bool dce80_construct(
 		goto res_create_fail;
 
 	/* Create hardware sequencer */
-	if (!dce80_hw_sequencer_construct(dc))
-		goto res_create_fail;
+	dce80_hw_sequencer_construct(dc);
 
 	return true;
 
@@ -1075,8 +1074,7 @@ static bool dce81_construct(
 		goto res_create_fail;
 
 	/* Create hardware sequencer */
-	if (!dce80_hw_sequencer_construct(dc))
-		goto res_create_fail;
+	dce80_hw_sequencer_construct(dc);
 
 	return true;
 
@@ -1236,8 +1234,7 @@ static bool dce83_construct(
 		goto res_create_fail;
 
 	/* Create hardware sequencer */
-	if (!dce80_hw_sequencer_construct(dc))
-		goto res_create_fail;
+	dce80_hw_sequencer_construct(dc);
 
 	return true;
 

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c

@@ -397,7 +397,7 @@ static const struct transform_funcs dcn10_dpp_funcs = {
 /* Constructor, Destructor               */
 /*****************************************/
 
-bool dcn10_dpp_construct(
+void dcn10_dpp_construct(
 	struct dcn10_dpp *xfm,
 	struct dc_context *ctx,
 	uint32_t inst,
@@ -421,6 +421,4 @@ bool dcn10_dpp_construct(
 
 	xfm->lb_bits_per_entry = LB_BITS_PER_ENTRY;
 	xfm->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
-
-	return true;
 }

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

@@ -1356,7 +1356,7 @@ void ippn10_cnv_setup (
 
 void ippn10_full_bypass(struct transform *xfm_base);
 
-bool dcn10_dpp_construct(struct dcn10_dpp *xfm110,
+void dcn10_dpp_construct(struct dcn10_dpp *xfm110,
 	struct dc_context *ctx,
 	uint32_t inst,
 	const struct dcn_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c

@@ -786,7 +786,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {
 /* Constructor, Destructor               */
 /*****************************************/
 
-bool dcn10_mem_input_construct(
+void dcn10_mem_input_construct(
 	struct dcn10_mem_input *mi,
 	struct dc_context *ctx,
 	uint32_t inst,
@@ -802,7 +802,5 @@ bool dcn10_mem_input_construct(
 	mi->base.inst = inst;
 	mi->base.opp_id = 0xf;
 	mi->base.mpcc_id = 0xf;
-
-	return true;
 }
 

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h

@@ -538,7 +538,7 @@ struct dcn10_mem_input {
 	const struct dcn_mi_mask *mi_mask;
 };
 
-bool dcn10_mem_input_construct(
+void dcn10_mem_input_construct(
 	struct dcn10_mem_input *mi,
 	struct dc_context *ctx,
 	uint32_t inst,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

@@ -462,13 +462,9 @@ static struct transform *dcn10_dpp_create(
 	if (!dpp)
 		return NULL;
 
-	if (dcn10_dpp_construct(dpp, ctx, inst,
-			&tf_regs[inst], &tf_shift, &tf_mask))
+	dcn10_dpp_construct(dpp, ctx, inst,
+			    &tf_regs[inst], &tf_shift, &tf_mask);
 	return &dpp->base;
-
-	BREAK_TO_DEBUGGER();
-	kfree(dpp);
-	return NULL;
 }
 
 static struct input_pixel_processor *dcn10_ipp_create(
@@ -771,13 +767,9 @@ static struct mem_input *dcn10_mem_input_create(
 	if (!mem_inputn10)
 		return NULL;
 
-	if (dcn10_mem_input_construct(mem_inputn10, ctx, inst,
-			&mi_regs[inst], &mi_shift, &mi_mask))
+	dcn10_mem_input_construct(mem_inputn10, ctx, inst,
+				  &mi_regs[inst], &mi_shift, &mi_mask);
 	return &mem_inputn10->base;
-
-	BREAK_TO_DEBUGGER();
-	kfree(mem_inputn10);
-	return NULL;
 }
 
 static void get_pixel_clock_parameters(