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Commit c26ba334 authored by Dave Jiang's avatar Dave Jiang Committed by Russell King
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[ARM PATCH] 1963/1: Intel XScale IOP310 removal 

Patch from Dave Jiang

Code cleanup. Removed all IOP80310 support. Also some minor compile warning fixups for 80321. Preping for IOP321 and IOP331 code submissions.
parent 30e24c39
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arch/arm/boot/compressed/head-xscale.S
View file @ c26ba334
......@@ -47,23 +47,3 @@ __XScale_start:
#ifdef CONFIG_ARCH_COTULLA_IDP
mov r7, #MACH_TYPE_COTULLA_IDP
#endif
#ifdef CONFIG_ARCH_IQ80310
/*
* Crank the CPU up to 733MHz
*/
mov r1, #9
mcr p14, 0, r1, c6, c0, 0
/*
* Disable ECC error notification
* At some point, we should add an ECC handler to Linux
*/
mov r1, #0x1500
mov r0, #0x4
str r0, [r1, #0x34]
mov r7, #MACH_TYPE_IQ80310
#endif
arch/arm/configs/iq80310_defconfig deleted 100644 → 0
View file @ 30e24c39
This diff is collapsed.
arch/arm/configs/iq80321_defconfig
View file @ c26ba334
This diff is collapsed.
arch/arm/kernel/debug.S
View file @ c26ba334
......@@ -411,9 +411,7 @@
.macro addruart,rx
mov \rx, #0xfe000000 @ physical
#ifdef CONFIG_ARCH_IQ80310
orr \rx, \rx, #0x00810000 @ location of the UART
#elif defined(CONFIG_ARCH_IQ80321)
#if defined(CONFIG_ARCH_IQ80321)
orr \rx, \rx, #0x00800000 @ location of the UART
#else
#error Unknown IOP3XX implementation
......
arch/arm/kernel/entry-armv.S
View file @ c26ba334
......@@ -562,40 +562,6 @@ ENTRY(soft_irq_mask)
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_IOP310)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mrc p13, 0, \irqstat, c4, c0, 0 @ get INTSRC
mrc p13, 0, \base, c0, c0, 0 @ get INTCTL
tst \irqstat, #(1<<29) @ if INTSRC_BI
tstne \base, #(1<<3) @ and INTCTL_BM
movne \irqnr, #IRQ_XS80200_BCU
bne 1001f
tst \irqstat, #(1<<28) @ if INTSRC_PI
tstne \base, #(1<<2) @ and INTCTL_PM
movne \irqnr, #IRQ_XS80200_PMU
bne 1001f
tst \irqstat, #(1<<31) @ if INTSRC_FI
tstne \base, #(1<<0) @ and INTCTL_FM
movne \irqnr, #IRQ_XS80200_EXTFIQ
bne 1001f
tst \irqstat, #(1<<30) @ if INTSRC_II
tstne \base, #(1<<1) @ and INTCTL_IM
movne \irqnr, #IRQ_XS80200_EXTIRQ
1001:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_IOP321)
.macro disable_fiq
.endm
......
arch/arm/mach-iop3xx/Kconfig
View file @ c26ba334
......@@ -4,13 +4,7 @@ menu "IOP3xx Implementation Options"
choice
prompt "IOP3xx System Type"
default ARCH_IQ80310
config ARCH_IQ80310
bool "IQ80310"
help
Say Y here if you want to run your kernel on the Intel IQ80310
evaluation kit for the IOP310 chipset.
default ARCH_IQ80321
config ARCH_IQ80321
bool "IQ80321"
......@@ -20,12 +14,6 @@ config ARCH_IQ80321
endchoice
# Which IOP variant are we running?
config ARCH_IOP310
bool
default ARCH_IQ80310
help
The IQ80310 uses the IOP310 variant.
config ARCH_IOP321
bool
default ARCH_IQ80321
......@@ -42,14 +30,6 @@ config IOP3XX_DMA
bool "Support Intel IOP3xx DMA (EXPERIMENTAL)"
depends on EXPERIMENTAL
config IOP3XX_MU
bool "Support Intel IOP3xx Messaging Unit (EXPERIMENTAL)"
depends on EXPERIMENTAL
config IOP3XX_PMON
bool "Support Intel IOP3xx Performance Monitor (EXPERIMENTAL)"
depends on EXPERIMENTAL
endmenu
endif
arch/arm/mach-iop3xx/Makefile
View file @ c26ba334
......@@ -10,21 +10,9 @@ obj-m :=
obj-n :=
obj- :=
obj-$(CONFIG_ARCH_IOP310) += xs80200-irq.o iop310-irq.o iop310-pci.o mm.o
obj-$(CONFIG_ARCH_IQ80310) += iq80310-pci.o iq80310-irq.o
obj-$(CONFIG_ARCH_IOP321) += iop321-irq.o iop321-pci.o mm-321.o iop321-time.o
obj-$(CONFIG_ARCH_IQ80321) += iq80321-pci.o
ifeq ($(CONFIG_ARCH_IQ80310),y)
ifneq ($(CONFIG_XSCALE_PMU_TIMER),y)
obj-y += iq80310-time.o
endif
endif
obj-$(CONFIG_IOP3XX_AAU) += aau.o
obj-$(CONFIG_IOP3XX_DMA) += dma.o
obj-$(CONFIG_IOP3XX_MU) += message.o
obj-$(CONFIG_IOP3XX_PMON) += pmon.o
arch/arm/mach-iop3xx/arch.c
View file @ c26ba334
......@@ -21,49 +21,23 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#ifdef CONFIG_ARCH_IQ80310
extern void iq80310_map_io(void);
extern void iq80310_init_irq(void);
#endif
#ifdef CONFIG_ARCH_IQ80321
extern void iq80321_map_io(void);
extern void iop321_init_irq(void);
extern void iop321_init_time(void);
#endif
#ifdef CONFIG_ARCH_IQ80310
static void __init
fixup_iq80310(struct machine_desc *desc, struct tag *tags,
char **cmdline, struct meminfo *mi)
{
system_rev = (*(volatile unsigned int*)0xfe830000) & 0x0f;
if (system_rev)
system_rev = 0xF;
}
#endif
#ifdef CONFIG_ARCH_IQ80321
static void __init
fixup_iop321(struct machine_desc *desc, struct param_struct *params,
fixup_iop321(struct machine_desc *desc, struct tag *tags,
char **cmdline, struct meminfo *mi)
{
}
#endif
#ifdef CONFIG_ARCH_IQ80310
MACHINE_START(IQ80310, "Cyclone IQ80310")
MAINTAINER("MontaVista Software Inc.")
BOOT_MEM(0xa0000000, 0xfe000000, 0xfe000000)
FIXUP(fixup_iq80310)
MAPIO(iq80310_map_io)
INITIRQ(iq80310_init_irq)
MACHINE_END
#elif defined(CONFIG_ARCH_IQ80321)
#if defined(CONFIG_ARCH_IQ80321)
MACHINE_START(IQ80321, "Intel IQ80321")
MAINTAINER("MontaVista Software, Inc.")
MAINTAINER("Intel Corporation")
BOOT_MEM(PHYS_OFFSET, IQ80321_UART1, 0xfe800000)
FIXUP(fixup_iop321)
MAPIO(iq80321_map_io)
......@@ -72,5 +46,5 @@ MACHINE_START(IQ80321, "Intel IQ80321")
MACHINE_END
#else
#error No machine descriptor defined for this IOP310 implementation
#error No machine descriptor defined for this IOP3xx implementation
#endif
arch/arm/mach-iop3xx/iop310-irq.c deleted 100644 → 0
View file @ 30e24c39
/*
* linux/arch/arm/mach-iop3xx/iop310-irq.c
*
* Generic IOP310 IRQ handling functionality
*
* Author: Nicolas Pitre
* Copyright: (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Added IOP310 chipset and IQ80310 board demuxing, masking code. - DS
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <asm/hardware.h>
extern void xs80200_irq_mask(unsigned int);
extern void xs80200_irq_unmask(unsigned int);
extern void xs80200_init_irq(void);
extern void do_IRQ(int, struct pt_regs *);
static u32 iop310_mask /* = 0 */;
static void iop310_irq_mask (unsigned int irq)
{
iop310_mask ++;
/*
* No mask bits on the 80312, so we have to
* mask everything from the outside!
*/
if (iop310_mask == 1) {
disable_irq(IRQ_XS80200_EXTIRQ);
irq_desc[IRQ_XS80200_EXTIRQ].chip->mask(IRQ_XS80200_EXTIRQ);
}
}
static void iop310_irq_unmask (unsigned int irq)
{
if (iop310_mask)
iop310_mask --;
/*
* Check if all 80312 sources are unmasked now
*/
if (iop310_mask == 0)
enable_irq(IRQ_XS80200_EXTIRQ);
}
struct irqchip ext_chip = {
.ack = iop310_irq_mask,
.mask = iop310_irq_mask,
.unmask = iop310_irq_unmask,
};
void
iop310_irq_demux(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
{
u32 fiq1isr = *((volatile u32*)IOP310_FIQ1ISR);
u32 fiq2isr = *((volatile u32*)IOP310_FIQ2ISR);
struct irqdesc *d;
unsigned int irqno = 0;
if(fiq1isr)
{
if(fiq1isr & 0x1)
irqno = IRQ_IOP310_DMA0;
if(fiq1isr & 0x2)
irqno = IRQ_IOP310_DMA1;
if(fiq1isr & 0x4)
irqno = IRQ_IOP310_DMA2;
if(fiq1isr & 0x10)
irqno = IRQ_IOP310_PMON;
if(fiq1isr & 0x20)
irqno = IRQ_IOP310_AAU;
}
else
{
if(fiq2isr & 0x2)
irqno = IRQ_IOP310_I2C;
if(fiq2isr & 0x4)
irqno = IRQ_IOP310_MU;
}
if (irqno) {
d = irq_desc + irqno;
d->handle(irqno, d, regs);
}
}
void __init iop310_init_irq(void)
{
unsigned int i;
for(i = IOP310_IRQ_OFS; i < NR_IOP310_IRQS; i++)
{
set_irq_chip(i, &ext_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
xs80200_init_irq();
}
arch/arm/mach-iop3xx/iop310-pci.c deleted 100644 → 0
View file @ 30e24c39
This diff is collapsed.
arch/arm/mach-iop3xx/iop321-pci.c
View file @ c26ba334
......@@ -158,6 +158,7 @@ iop321_write_config(struct pci_bus *bus, unsigned int devfn, int where,
: "r" (value), "r" (addr),
"r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
}
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops iop321_ops = {
......
arch/arm/mach-iop3xx/iop321-time.c
View file @ c26ba334
......@@ -79,7 +79,7 @@ extern int setup_arm_irq(int, struct irqaction*);
void __init iop321_init_time(void)
{
u32 timer_ctl;
u32 latch = LATCH;
/* u32 latch = LATCH; */
gettimeoffset = iop321_gettimeoffset;
setup_irq(IRQ_IOP321_TIMER0, &iop321_timer_irq);
......
arch/arm/mach-iop3xx/iq80310-irq.c deleted 100644 → 0
View file @ 30e24c39
/*
* linux/arch/arm/mach-iop3xx/iq80310-irq.c
*
* IRQ hadling/demuxing for IQ80310 board
*
* Author: Nicolas Pitre
* Copyright: (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* 2.4.7-rmk1-iop310.1
* Moved demux from asm to C - DS
* Fixes for various revision boards - DS
*/
#include <linux/init.h>
#include <linux/list.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/hardware.h>
#include <asm/system.h>
extern void iop310_init_irq(void);
extern void iop310_irq_demux(unsigned int, struct irqdesc *, struct pt_regs *);
static void iq80310_irq_mask(unsigned int irq)
{
*(volatile char *)IQ80310_INT_MASK |= (1 << (irq - IQ80310_IRQ_OFS));
}
static void iq80310_irq_unmask(unsigned int irq)
{
*(volatile char *)IQ80310_INT_MASK &= ~(1 << (irq - IQ80310_IRQ_OFS));
}
static struct irqchip iq80310_irq_chip = {
.ack = iq80310_irq_mask,
.mask = iq80310_irq_mask,
.unmask = iq80310_irq_unmask,
};
extern struct irqchip ext_chip;
static void
iq80310_cpld_irq_handler(unsigned int irq, struct irqdesc *desc,
struct pt_regs *regs)
{
unsigned int irq_stat = *(volatile u8*)IQ80310_INT_STAT;
unsigned int irq_mask = *(volatile u8*)IQ80310_INT_MASK;
unsigned int i, handled = 0;
struct irqdesc *d;
desc->chip->ack(irq);
/*
* Mask out the interrupts which aren't enabled.
*/
irq_stat &= 0x1f & ~irq_mask;
/*
* Test each IQ80310 CPLD interrupt
*/
for (i = IRQ_IQ80310_TIMER, d = irq_desc + IRQ_IQ80310_TIMER;
irq_stat; i++, d++, irq_stat >>= 1)
if (irq_stat & 1) {
d->handle(i, d, regs);
handled++;
}
/*
* If running on a board later than REV D.1, we can
* decode the PCI interrupt status.
*/
if (system_rev) {
irq_stat = *((volatile u8*)IQ80310_PCI_INT_STAT) & 7;
for (i = IRQ_IQ80310_INTA, d = irq_desc + IRQ_IQ80310_INTA;
irq_stat; i++, d++, irq_stat >>= 1)
if (irq_stat & 0x1) {
d->handle(i, d, regs);
handled++;
}
}
/*
* If on a REV D.1 or lower board, we just assumed INTA
* since PCI is not routed, and it may actually be an
* on-chip interrupt.
*
* Note that we're giving on-chip interrupts slightly
* higher priority than PCI by handling them first.
*
* On boards later than REV D.1, if we didn't read a
* CPLD interrupt, we assume it's from a device on the
* chipset itself.
*/
if (system_rev == 0 || handled == 0)
iop310_irq_demux(irq, desc, regs);
desc->chip->unmask(irq);
}
void __init iq80310_init_irq(void)
{
volatile char *mask = (volatile char *)IQ80310_INT_MASK;
unsigned int i;
iop310_init_irq();
/*
* Setup PIRSR to route PCI interrupts into xs80200
*/
*IOP310_PIRSR = 0xff;
/*
* Setup the IRQs in the FE820000/FE860000 registers
*/
for (i = IQ80310_IRQ_OFS; i <= IRQ_IQ80310_INTD; i++) {
set_irq_chip(i, &iq80310_irq_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/*
* Setup the PCI IRQs
*/
for (i = IRQ_IQ80310_INTA; i < IRQ_IQ80310_INTC; i++) {
set_irq_chip(i, &ext_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID);
}
*mask = 0xff; /* mask all sources */
set_irq_chained_handler(IRQ_XS80200_EXTIRQ,
&iq80310_cpld_irq_handler);
}
arch/arm/mach-iop3xx/iq80310-pci.c deleted 100644 → 0
View file @ 30e24c39
/*
* arch/arm/mach-iop3xx/iq80310-pci.c
*
* PCI support for the Intel IQ80310 reference board
*
* Matt Porter <mporter@mvista.com>
*
* Copyright (C) 2001 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
/*
* The following macro is used to lookup irqs in a standard table
* format for those systems that do not already have PCI
* interrupts properly routed. We assume 1 <= pin <= 4
*/
#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
({ int _ctl_ = -1; \
unsigned int _idsel = idsel - minid; \
if (_idsel <= maxid) \
_ctl_ = pci_irq_table[_idsel][pin-1]; \
_ctl_; })
#define INTA IRQ_IQ80310_INTA
#define INTB IRQ_IQ80310_INTB
#define INTC IRQ_IQ80310_INTC
#define INTD IRQ_IQ80310_INTD
#define INTE IRQ_IQ80310_I82559
typedef u8 irq_table[4];
/*
* IRQ tables for primary bus.
*
* On a Rev D.1 and older board, INT A-C are not routed, so we
* just fake it as INTA and than we take care of handling it
* correctly in the IRQ demux routine.
*/
static irq_table pci_pri_d_irq_table[] = {
/* Pin: A B C D */
{ INTA, INTD, INTA, INTA }, /* PCI Slot J3 */
{ INTD, INTA, INTA, INTA }, /* PCI Slot J4 */
};
static irq_table pci_pri_f_irq_table[] = {
/* Pin: A B C D */
{ INTC, INTD, INTA, INTB }, /* PCI Slot J3 */
{ INTD, INTA, INTB, INTC }, /* PCI Slot J4 */
};
static int __init
iq80310_pri_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
irq_table *pci_irq_table;
BUG_ON(pin < 1 || pin > 4);
if (!system_rev) {
pci_irq_table = pci_pri_d_irq_table;
} else {
pci_irq_table = pci_pri_f_irq_table;
}
return PCI_IRQ_TABLE_LOOKUP(2, 3);
}
/*
* IRQ tables for secondary bus.
*
* On a Rev D.1 and older board, INT A-C are not routed, so we
* just fake it as INTA and than we take care of handling it
* correctly in the IRQ demux routine.
*/
static irq_table pci_sec_d_irq_table[] = {
/* Pin: A B C D */
{ INTA, INTA, INTA, INTD }, /* PCI Slot J1 */
{ INTA, INTA, INTD, INTA }, /* PCI Slot J5 */
{ INTE, INTE, INTE, INTE }, /* P2P Bridge */
};
static irq_table pci_sec_f_irq_table[] = {
/* Pin: A B C D */
{ INTA, INTB, INTC, INTD }, /* PCI Slot J1 */
{ INTB, INTC, INTD, INTA }, /* PCI Slot J5 */
{ INTE, INTE, INTE, INTE }, /* P2P Bridge */
};
static int __init
iq80310_sec_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
irq_table *pci_irq_table;
BUG_ON(pin < 1 || pin > 4);
if (!system_rev) {
pci_irq_table = pci_sec_d_irq_table;
} else {
pci_irq_table = pci_sec_f_irq_table;
}
return PCI_IRQ_TABLE_LOOKUP(0, 2);
}
static int iq80310_pri_host;
static int iq80310_setup(int nr, struct pci_sys_data *sys)
{
switch (nr) {
case 0:
if (!iq80310_pri_host)
return 0;
sys->map_irq = iq80310_pri_map_irq;
break;
case 1:
sys->map_irq = iq80310_sec_map_irq;
break;
default:
return 0;
}
return iop310_setup(nr, sys);
}
static void iq80310_preinit(void)
{
iq80310_pri_host = *(volatile u32 *)IQ80310_BACKPLANE & 1;
printk(KERN_INFO "PCI: IQ80310 is a%s\n",
iq80310_pri_host ? " system controller" : "n agent");
iop310_init();
}
static struct hw_pci iq80310_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 2,
.setup = iq80310_setup,
.scan = iop310_scan_bus,
.preinit = iq80310_preinit,
};
static int __init iq80310_pci_init(void)
{
if (machine_is_iq80310())
pci_common_init(&iq80310_pci);
return 0;
}
subsys_initcall(iq80310_pci_init);
arch/arm/mach-iop3xx/iq80310-time.c deleted 100644 → 0
View file @ 30e24c39
/*
* linux/arch/arm/mach-iop3xx/time-iq80310.c
*
* Timer functions for IQ80310 onboard timer
*
* Author: Nicolas Pitre
* Copyright: (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h>
#include <linux/timex.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/mach/irq.h>
static void iq80310_write_timer (u_long val)
{
volatile u_char *la0 = (volatile u_char *)IQ80310_TIMER_LA0;
volatile u_char *la1 = (volatile u_char *)IQ80310_TIMER_LA1;
volatile u_char *la2 = (volatile u_char *)IQ80310_TIMER_LA2;
*la0 = val;
*la1 = val >> 8;
*la2 = (val >> 16) & 0x3f;
}
static u_long iq80310_read_timer (void)
{
volatile u_char *la0 = (volatile u_char *)IQ80310_TIMER_LA0;
volatile u_char *la1 = (volatile u_char *)IQ80310_TIMER_LA1;
volatile u_char *la2 = (volatile u_char *)IQ80310_TIMER_LA2;
volatile u_char *la3 = (volatile u_char *)IQ80310_TIMER_LA3;
u_long b0, b1, b2, b3, val;
b0 = *la0; b1 = *la1; b2 = *la2; b3 = *la3;
b0 = (((b0 & 0x40) >> 1) | (b0 & 0x1f));
b1 = (((b1 & 0x40) >> 1) | (b1 & 0x1f));
b2 = (((b2 & 0x40) >> 1) | (b2 & 0x1f));
b3 = (b3 & 0x0f);
val = ((b0 << 0) | (b1 << 6) | (b2 << 12) | (b3 << 18));
return val;
}
/*
* IRQs are disabled before entering here from do_gettimeofday().
* Note that the counter may wrap. When it does, 'elapsed' will
* be small, but we will have a pending interrupt.
*/
static unsigned long iq80310_gettimeoffset (void)
{
unsigned long elapsed, usec;
unsigned int stat1, stat2;
stat1 = *(volatile u8 *)IQ80310_INT_STAT;
elapsed = iq80310_read_timer();
stat2 = *(volatile u8 *)IQ80310_INT_STAT;
/*
* If an interrupt was pending before we read the timer,
* we've already wrapped. Factor this into the time.
* If an interrupt was pending after we read the timer,
* it may have wrapped between checking the interrupt
* status and reading the timer. Re-read the timer to
* be sure its value is after the wrap.
*/
if (stat1 & 1)
elapsed += LATCH;
else if (stat2 & 1)
elapsed = LATCH + iq80310_read_timer();
/*
* Now convert them to usec.
*/
usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH;
return usec;
}
static irqreturn_t
iq80310_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
volatile u_char *timer_en = (volatile u_char *)IQ80310_TIMER_EN;
/* clear timer interrupt */
*timer_en &= ~2;
*timer_en |= 2;
do_timer(regs);
return IRQ_HANDLED;
}
extern unsigned long (*gettimeoffset)(void);
static struct irqaction timer_irq = {
.name = "timer",
.handler = iq80310_timer_interrupt,
};
void __init time_init(void)
{
volatile u_char *timer_en = (volatile u_char *)IQ80310_TIMER_EN;
gettimeoffset = iq80310_gettimeoffset;
setup_irq(IRQ_IQ80310_TIMER, &timer_irq);
*timer_en = 0;
iq80310_write_timer(LATCH);
*timer_en |= 2;
*timer_en |= 1;
}
arch/arm/mach-iop3xx/mm.c deleted 100644 → 0
View file @ 30e24c39
/*
* linux/arch/arm/mach-iop3xx/mm.c
*
* Low level memory initialization for IOP310 based systems
*
* Author: Nicolas Pitre <npitre@mvista.com>
*
* Copyright 2000-2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#ifdef CONFIG_IOP310_MU
#include "message.h"
#endif
/*
* Standard IO mapping for all IOP310 based systems
*/
static struct map_desc iop80310_std_desc[] __initdata = {
/* virtual physical length type */
// IOP310 Memory Mapped Registers
{ 0xe8001000, 0x00001000, 0x00001000, MT_DEVICE },
// PCI I/O Space
{ 0xfe000000, 0x90000000, 0x00020000, MT_DEVICE }
};
void __init iop310_map_io(void)
{
iotable_init(iop80310_std_desc, ARRAY_SIZE(iop80310_std_desc));
}
/*
* IQ80310 specific IO mappings
*/
#ifdef CONFIG_ARCH_IQ80310
static struct map_desc iq80310_io_desc[] __initdata = {
/* virtual physical length type */
// IQ80310 On-Board Devices
{ 0xfe800000, 0xfe800000, 0x00100000, MT_DEVICE }
};
void __init iq80310_map_io(void)
{
#ifdef CONFIG_IOP310_MU
/* acquiring 1MB of memory aligned on 1MB boundary for MU */
mu_mem = __alloc_bootmem(0x100000, 0x100000, 0);
#endif
iop310_map_io();
iotable_init(iq80310_io_desc, ARRAY_SIZE(iq80310_io_desc));
}
#endif // CONFIG_ARCH_IQ80310
arch/arm/mach-iop3xx/xs80200-irq.c deleted 100644 → 0
View file @ 30e24c39
/*
* linux/arch/arm/mach-iop3xx/xs80200-irq.c
*
* Generic IRQ handling for the XS80200 XScale core.
*
* Author: Nicolas Pitre
* Copyright: (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/list.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <asm/hardware.h>
static void xs80200_irq_mask (unsigned int irq)
{
unsigned long intctl;
asm ("mrc p13, 0, %0, c0, c0, 0" : "=r" (intctl));
switch (irq) {
case IRQ_XS80200_BCU: intctl &= ~(1<<3); break;
case IRQ_XS80200_PMU: intctl &= ~(1<<2); break;
case IRQ_XS80200_EXTIRQ: intctl &= ~(1<<1); break;
case IRQ_XS80200_EXTFIQ: intctl &= ~(1<<0); break;
}
asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (intctl));
}
static void xs80200_irq_unmask (unsigned int irq)
{
unsigned long intctl;
asm ("mrc p13, 0, %0, c0, c0, 0" : "=r" (intctl));
switch (irq) {
case IRQ_XS80200_BCU: intctl |= (1<<3); break;
case IRQ_XS80200_PMU: intctl |= (1<<2); break;
case IRQ_XS80200_EXTIRQ: intctl |= (1<<1); break;
case IRQ_XS80200_EXTFIQ: intctl |= (1<<0); break;
}
asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (intctl));
}
static struct irqchip xs80200_chip = {
.ack = xs80200_irq_mask,
.mask = xs80200_irq_mask,
.unmask = xs80200_irq_unmask,
};
void __init xs80200_init_irq(void)
{
unsigned int i;
asm("mcr p13, 0, %0, c0, c0, 0" : : "r" (0));
for (i = 0; i < NR_XS80200_IRQS; i++) {
set_irq_chip(i, &xs80200_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID);
}
}
include/asm-arm/arch-iop3xx/dma.h
View file @ c26ba334
/*
* linux/include/asm-arm/arch-iop80310/dma.h
* linux/include/asm-arm/arch-iop3xx/dma.h
*
* Copyright (C) 2001 MontaVista Software, Inc.
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _IOP310_DMA_H_
#define _IOP310_DMA_H_
#ifndef _IOP3XX_DMA_H_P
#define _IOP3XX_DMA_H_P
/* 2 DMA on primary PCI and 1 on secondary for 80310 */
#define MAX_IOP310_DMA_CHANNEL 3
/* 80310 not supported */
#define MAX_IOP3XX_DMA_CHANNEL 2
#define MAX_DMA_DESC 64 /*128 */
#define DMA_FREE 0x0
#define DMA_ACTIVE 0x1
#define DMA_COMPLETE 0x2
#define DMA_ERROR 0x4
/*
* Make the generic DMA bits go away since we don't use it
*/
......@@ -22,27 +27,10 @@
#define MAX_DMA_ADDRESS 0xffffffff
#define IOP310_DMA_P0 0
#define IOP310_DMA_P1 1
#define IOP310_DMA_S0 2
#define DMA_MOD_READ 0x0001
#define DMA_MOD_WRITE 0x0002
#define DMA_MOD_CACHED 0x0004
#define DMA_MOD_NONCACHED 0x0008
#define DMA_DESC_DONE 0x0010
#define DMA_INCOMPLETE 0x0020
#define DMA_HOLD 0x0040
#define DMA_END_CHAIN 0x0080
#define DMA_COMPLETE 0x0100
#define DMA_NOTIFY 0x0200
#define DMA_NEW_HEAD 0x0400
#define DMA_USER_MASK (DMA_NOTIFY | DMA_INCOMPLETE | \
DMA_HOLD | DMA_COMPLETE)
#define DMA_POLL 0x0
#define DMA_INTERRUPT 0x1
#define DMA_DCR_MTM 0x00000040 /* memory to memory transfer */
#define DMA_DCR_DAC 0x00000020 /* Dual Addr Cycle Enab */
#define DMA_DCR_IE 0x00000010 /* Interrupt Enable */
#define DMA_DCR_PCI_IOR 0x00000002 /* I/O Read */
......@@ -55,55 +43,12 @@
#define DMA_DCR_PCI_MRL 0x0000000E /* Memory Read Line */
#define DMA_DCR_PCI_MWI 0x0000000F /* Mem Write and Inval */
#define DMA_USER_CMD_IE 0x00000001 /* user request int */
#define DMA_USER_END_CHAIN 0x00000002 /* end of sgl chain flag */
/* ATU defines */
#define IOP310_ATUCR_PRIM_OUT_ENAB /* Configuration */ 0x00000002
#define IOP310_ATUCR_DIR_ADDR_ENAB /* Configuration */ 0x00000080
typedef void (*dma_callback_t) (void *buf_context);
/*
* DMA Descriptor
*/
typedef struct _dma_desc
{
u32 NDAR; /* next descriptor address */
u32 PDAR; /* PCI address */
u32 PUADR; /* upper PCI address */
u32 LADR; /* local address */
u32 BC; /* byte count */
u32 DC; /* descriptor control */
} dma_desc_t;
typedef struct _dma_sgl
{
dma_desc_t dma_desc; /* DMA descriptor pointer */
u32 status; /* descriptor status */
void *data; /* local virt */
struct _dma_sgl *next; /* next descriptor */
} dma_sgl_t;
/* dma sgl head */
typedef struct _dma_head
{
u32 total; /* total elements in SGL */
u32 status; /* status of sgl */
u32 mode; /* read or write mode */
dma_sgl_t *list; /* pointer to list */
dma_callback_t callback; /* callback function */
} dma_head_t;
//extern iop3xx_dma_t dma_chan[2];
/* function prototypes */
int dma_request(dmach_t, const char *);
int dma_queue_buffer(dmach_t, dma_head_t *);
int dma_suspend(dmach_t);
int dma_resume(dmach_t);
int dma_flush_all(dmach_t);
void dma_free(dmach_t);
void dma_set_irq_threshold(dmach_t, int);
dma_sgl_t *dma_get_buffer(dmach_t, int);
void dma_return_buffer(dmach_t, dma_sgl_t *);
#ifdef CONFIG_IOP3XX_DMACOPY
extern int iop_memcpy;
void * dma_memcpy(void * to, const void* from, __kernel_size_t n);
#endif
#endif /* _ASM_ARCH_DMA_H */
#endif /* _ASM_ARCH_DMA_H_P */
include/asm-arm/arch-iop3xx/hardware.h
View file @ c26ba334
/*
* linux/include/asm-arm/arch-iop80310/hardware.h
* linux/include/asm-arm/arch-iop3xx/hardware.h
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
......@@ -15,28 +15,11 @@
* The PCI IO space is located at virtual 0xfe000000 from physical
* 0x90000000. The PCI BARs must be programmed with physical addresses,
* but when we read them, we convert them to virtual addresses. See
* arch/arm/mach-iop310/iop310-pci.c
* arch/arm/mach-iop3xx/iop3XX-pci.c
*/
#define pcibios_assign_all_busses() 1
#ifdef CONFIG_ARCH_IOP310
/*
* these are the values for the secondary PCI bus on the 80312 chip. I will
* have to do some fixup in the bus/dev fixup code
*/
#define PCIBIOS_MIN_IO 0
#define PCIBIOS_MIN_MEM 0x88000000
// Generic chipset bits
#include "iop310.h"
// Board specific
#if defined(CONFIG_ARCH_IQ80310)
#include "iq80310.h"
#endif
#endif
#ifdef CONFIG_ARCH_IOP321
#define PCIBIOS_MIN_IO 0x90000000
......
include/asm-arm/arch-iop3xx/iop310-irqs.h deleted 100644 → 0
View file @ 30e24c39
/*
* linux/include/asm-arm/arch-iop310/irqs.h
*
* Author: Nicolas Pitre
* Copyright: (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* 06/13/01: Added 80310 on-chip interrupt sources <dsaxena@mvista.com>
*
*/
#include <linux/config.h>
/*
* XS80200 specific IRQs
*/
#define IRQ_XS80200_BCU 0 /* Bus Control Unit */
#define IRQ_XS80200_PMU 1 /* Performance Monitoring Unit */
#define IRQ_XS80200_EXTIRQ 2 /* external IRQ signal */
#define IRQ_XS80200_EXTFIQ 3 /* external IRQ signal */
#define NR_XS80200_IRQS 4
#define XSCALE_PMU_IRQ IRQ_XS80200_PMU
/*
* IOP80310 chipset interrupts
*/
#define IOP310_IRQ_OFS NR_XS80200_IRQS
#define IOP310_IRQ(x) (IOP310_IRQ_OFS + (x))
/*
* On FIQ1ISR register
*/
#define IRQ_IOP310_DMA0 IOP310_IRQ(0) /* DMA Channel 0 */
#define IRQ_IOP310_DMA1 IOP310_IRQ(1) /* DMA Channel 1 */
#define IRQ_IOP310_DMA2 IOP310_IRQ(2) /* DMA Channel 2 */
#define IRQ_IOP310_PMON IOP310_IRQ(3) /* Bus performance Unit */
#define IRQ_IOP310_AAU IOP310_IRQ(4) /* Application Accelator Unit */
/*
* On FIQ2ISR register
*/
#define IRQ_IOP310_I2C IOP310_IRQ(5) /* I2C unit */
#define IRQ_IOP310_MU IOP310_IRQ(6) /* messaging unit */
#define NR_IOP310_IRQS (IOP310_IRQ(6) + 1)
#define NR_IRQS NR_IOP310_IRQS
/*
* Interrupts available on the Cyclone IQ80310 board
*/
#ifdef CONFIG_ARCH_IQ80310
#define IQ80310_IRQ_OFS NR_IOP310_IRQS
#define IQ80310_IRQ(y) ((IQ80310_IRQ_OFS) + (y))
#define IRQ_IQ80310_TIMER IQ80310_IRQ(0) /* Timer Interrupt */
#define IRQ_IQ80310_I82559 IQ80310_IRQ(1) /* I82559 Ethernet Interrupt */
#define IRQ_IQ80310_UART1 IQ80310_IRQ(2) /* UART1 Interrupt */
#define IRQ_IQ80310_UART2 IQ80310_IRQ(3) /* UART2 Interrupt */
#define IRQ_IQ80310_INTD IQ80310_IRQ(4) /* PCI INTD */
/*
* ONLY AVAILABLE ON REV F OR NEWER BOARDS!
*/
#define IRQ_IQ80310_INTA IQ80310_IRQ(5) /* PCI INTA */
#define IRQ_IQ80310_INTB IQ80310_IRQ(6) /* PCI INTB */
#define IRQ_IQ80310_INTC IQ80310_IRQ(7) /* PCI INTC */
#undef NR_IRQS
#define NR_IRQS (IQ80310_IRQ(7) + 1)
#endif // CONFIG_ARCH_IQ80310
include/asm-arm/arch-iop3xx/iop310.h deleted 100644 → 0
View file @ 30e24c39
This diff is collapsed.
include/asm-arm/arch-iop3xx/iop321.h
View file @ c26ba334
......@@ -30,7 +30,7 @@
#define IOP321_PCI_IO_BASE 0x90000000
#define IOP321_PCI_IO_SIZE 0x00010000
#define IOP321_PCI_MEM_BASE 0x40000000
#define IOP321_PCI_MEM_BASE 0x80000000
#define IOP321_PCI_MEM_SIZE 0x40000000
/*
......
include/asm-arm/arch-iop3xx/iq80310.h deleted 100644 → 0
View file @ 30e24c39
/*
* linux/include/asm/arch-iop80310/iq80310.h
*
* Intel IQ-80310 evaluation board registers
*/
#ifndef _IQ80310_H_
#define _IQ80310_H_
#define IQ80310_RAMBASE 0xa0000000
#define IQ80310_UART1 0xfe800000 /* UART #1 */
#define IQ80310_UART2 0xfe810000 /* UART #2 */
#define IQ80310_INT_STAT 0xfe820000 /* Interrupt (XINT3#) Status */
#define IQ80310_BOARD_REV 0xfe830000 /* Board revision register */
#define IQ80310_CPLD_REV 0xfe840000 /* CPLD revision register */
#define IQ80310_7SEG_1 0xfe840000 /* 7-Segment MSB */
#define IQ80310_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
#define IQ80310_PCI_INT_STAT 0xfe850000 /* PCI Interrupt Status */
#define IQ80310_INT_MASK 0xfe860000 /* Interrupt (XINT3#) Mask */
#define IQ80310_BACKPLANE 0xfe870000 /* Backplane Detect */
#define IQ80310_TIMER_LA0 0xfe880000 /* Timer LA0 */
#define IQ80310_TIMER_LA1 0xfe890000 /* Timer LA1 */
#define IQ80310_TIMER_LA2 0xfe8a0000 /* Timer LA2 */
#define IQ80310_TIMER_LA3 0xfe8b0000 /* Timer LA3 */
#define IQ80310_TIMER_EN 0xfe8c0000 /* Timer Enable */
#define IQ80310_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
#define IQ80310_JTAG 0xfe8e0000 /* JTAG Port Access */
#define IQ80310_BATT_STAT 0xfe8f0000 /* Battery Status */
#endif // _IQ80310_H_
include/asm-arm/arch-iop3xx/irqs.h
View file @ c26ba334
......@@ -15,11 +15,7 @@
/*
* Whic iop3xx implementation is this?
*/
#ifdef CONFIG_ARCH_IOP310
#include "iop310-irqs.h"
#else
#ifdef CONFIG_ARCH_IOP321
#include "iop321-irqs.h"
......
include/asm-arm/arch-iop3xx/memory.h
View file @ c26ba334
/*
* linux/include/asm-arm/arch-iop80310/memory.h
* linux/include/asm-arm/arch-iop3xx/memory.h
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <linux/config.h>
#include <asm/arch/iop310.h>
#include <asm/arch/iop321.h>
/*
......@@ -21,23 +20,13 @@
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
#ifdef CONFIG_ARCH_IOP310
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP310_SIATVR)) | ((*IOP310_SIABAR) & 0xfffffff0))
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP310_SIALR)) | ( *IOP310_SIATVR)))
#elif defined(CONFIG_ARCH_IOP321)
#if defined(CONFIG_ARCH_IOP321)
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0))
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2)))
#endif
/* boot mem allocate global pointer for MU circular queues QBAR */
#ifdef CONFIG_IOP3XX_MU
extern void *mu_mem;
#endif
#define PFN_TO_NID(addr) (0)
#endif
include/asm-arm/arch-iop3xx/param.h
View file @ c26ba334
/*
* linux/include/asm-arm/arch-iop80310/param.h
* linux/include/asm-arm/arch-iop3xx/param.h
*/
include/asm-arm/arch-iop3xx/pmon.h deleted 100644 → 0
View file @ 30e24c39
/*
* Definitions for XScale 80312 PMON
* (C) 2001 Intel Corporation
* Author: Chen Chen(chen.chen@intel.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _IOP310_PMON_H_
#define _IOP310_PMON_H_
/*
* Different modes for Event Select Register for intel 80312
*/
#define IOP310_PMON_MODE0 0x00000000
#define IOP310_PMON_MODE1 0x00000001
#define IOP310_PMON_MODE2 0x00000002
#define IOP310_PMON_MODE3 0x00000003
#define IOP310_PMON_MODE4 0x00000004
#define IOP310_PMON_MODE5 0x00000005
#define IOP310_PMON_MODE6 0x00000006
#define IOP310_PMON_MODE7 0x00000007
typedef struct _iop310_pmon_result
{
u32 timestamp; /* Global Time Stamp Register */
u32 timestamp_overflow; /* Time Stamp overflow count */
u32 event_count[14]; /* Programmable Event Counter
Registers 1-14 */
u32 event_overflow[14]; /* Overflow counter for PECR1-14 */
} iop310_pmon_res_t;
/* function prototypes */
/* Claim IQ80312 PMON for usage */
int iop310_pmon_claim(void);
/* Start IQ80312 PMON */
int iop310_pmon_start(int, int);
/* Stop Performance Monitor Unit */
int iop310_pmon_stop(iop310_pmon_res_t *);
/* Release IQ80312 PMON */
int iop310_pmon_release(int);
#endif
include/asm-arm/arch-iop3xx/serial.h
View file @ c26ba334
......@@ -15,18 +15,6 @@
/* Standard COM flags */
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#ifdef CONFIG_ARCH_IQ80310
#define IRQ_UART1 IRQ_IQ80310_UART1
#define IRQ_UART2 IRQ_IQ80310_UART2
#define STD_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, IQ80310_UART2, IRQ_UART2, STD_COM_FLAGS }, /* ttyS0 */ \
{ 0, BASE_BAUD, IQ80310_UART1, IRQ_UART1, STD_COM_FLAGS } /* ttyS1 */
#endif // CONFIG_ARCH_IQ80310
#ifdef CONFIG_ARCH_IQ80321
#define IRQ_UART1 IRQ_IQ80321_UART
......
include/asm-arm/arch-iop3xx/system.h
View file @ c26ba334
/*
* linux/include/asm-arm/arch-iop80310/system.h
* linux/include/asm-arm/arch-iop3xx/system.h
*
* Copyright (C) 2001 MontaVista Software, Inc.
*
......
include/asm-arm/arch-iop3xx/timex.h
View file @ c26ba334
/*
* linux/include/asm-arm/arch-iop3xx/timex.h
*
* IOP310 architecture timex specifications
* IOP3xx architecture timex specifications
*/
#include <linux/config.h>
#ifdef CONFIG_ARCH_IQ80310
#ifndef CONFIG_XSCALE_PMU_TIMER
/* This is for the on-board timer */
#define CLOCK_TICK_RATE 33000000 /* Underlying HZ */
#else
/* This is for the underlying xs80200 PMU clock. We run the core @ 733MHz */
#define CLOCK_TICK_RATE 733000000
#endif // IQ80310
#elif defined(CONFIG_ARCH_IQ80321)
#if defined(CONFIG_ARCH_IQ80321)
#define CLOCK_TICK_RATE 200000000
......
include/asm-arm/arch-iop3xx/uncompress.h
View file @ c26ba334
/*
* linux/include/asm-arm/arch-iop80310/uncompress.h
* linux/include/asm-arm/arch-iop3xx/uncompress.h
*/
#include <linux/config.h>
#include <linux/serial_reg.h>
#include <asm/hardware.h>
#ifdef CONFIG_ARCH_IQ80310
#define UART2_BASE ((volatile unsigned char *)IQ80310_UART2)
#elif defined(CONFIG_ARCH_IQ80321)
#if defined(CONFIG_ARCH_IQ80321)
#define UART2_BASE ((volatile unsigned char *)IQ80321_UART1)
#endif
......
include/asm-arm/mach/pci.h
View file @ c26ba334
......@@ -52,10 +52,6 @@ void pci_common_init(struct hw_pci *);
/*
* PCI controllers
*/
extern int iop310_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *iop310_scan_bus(int nr, struct pci_sys_data *);
extern void iop310_init(void);
extern int iop321_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *);
extern void iop321_init(void);
......
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