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Commit c41e02c3 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Linus Walleij
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pinctrl: remove sirf atlas/prima drivers 

The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <baohua@kernel.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarBarry Song <baohua@kernel.org>
Link: https://lore.kernel.org/r/20210120132045.2127659-4-arnd@kernel.orgSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 484c58d6
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Documentation/devicetree/bindings/gpio/gpio-atlas7.txt deleted 100644 → 0
View file @ 484c58d6
CSR SiRFatlas7 GPIO controller bindings
Required properties:
- compatible : "sirf,atlas7-gpio"
- reg : Address range of the pinctrl registers
- interrupts : Interrupts used by every GPIO group
- gpio-banks : How many gpio banks on this controller
- gpio-controller : Indicates this device is a GPIO controller
- interrupt-controller : Marks the device node as an interrupt controller
The GPIO controller also acts as an interrupt controller. It uses the default
two cells specifier as described in Documentation/devicetree/bindings/
interrupt-controller/interrupts.txt.
Example:
gpio_0: gpio_mediam@17040000 {
compatible = "sirf,atlas7-gpio";
reg = <0x17040000 0x1000>;
interrupts = <0 13 0>, <0 14 0>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
gpio-banks = <2>;
gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 32 0 0>;
gpio-ranges-group-names = "lvds_gpio_grp",
"uart_nand_gpio_grp";
};
leds {
compatible = "gpio-leds";
led1 {
gpios = <&gpio_1 15 0>;
...
};
led2 {
gpios = <&gpio_2 34 0>;
...
};
};
Please refer to gpio.txt in this directory for details of the common
gpio properties used by devices.
Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt deleted 100644 → 0
View file @ 484c58d6
CSR SiRFatlas7 pinmux controller
Required properties:
- compatible : "sirf,atlas7-ioc"
- reg : Address range of the pinctrl registers
For example, pinctrl might have properties like the following:
pinctrl: ioc@18880000 {
compatible = "sirf,atlas7-ioc";
reg = <0x18880000 0x1000>;
a_ac97_pmx: ac97@0 {
ac97 {
groups = "audio_ac97_grp";
function = "audio_ac97";
};
};
...
sd2_pmx: sd2@0 {
sd2 {
groups = "sd2_grp0";
function = "sd2";
};
};
...
sample0_cfg: sample0@0 {
sample0 {
pins = "ldd_0", "ldd_1";
bias-pull-up;
};
};
sample1_cfg: sample1@0 {
sample1 {
pins = "ldd_2", "ldd_3";
input-schmitt-enable;
};
};
sample2_cfg: sample2@0 {
sample2 {
groups = "uart4_nopause_grp";
bias-pull-down;
};
};
sample3_cfg: sample3@0 {
sample3 {
pins = "ldd_4", "ldd_5";
drive-strength = <2>;
};
};
};
Please refer to pinctrl-bindings.txt in this directory for details of the common
pinctrl bindings used by client devices.
SiRFatlas7's pinmux nodes act as a container for an arbitrary number of subnodes.
Each of these subnodes represents some desired configuration for a group of pins.
Required subnode-properties:
- groups : An array of strings. Each string contains the name of a group.
- function: A string containing the name of the function to mux to the
group.
Valid values for group and function names can be found from looking at the
group and function arrays in driver files:
drivers/pinctrl/pinctrl-sirf.c
For example, pinctrl might have subnodes like the following:
sd0_pmx: sd0@0 {
sd0 {
groups = "sd0_grp";
function = "sd0";
};
};
sd1_pmx0: sd1@0 {
sd1 {
groups = "sd1_grp0";
function = "sd1_m0";
};
};
sd1_pmx1: sd1@1 {
sd1 {
groups = "sd1_grp1";
function = "sd1_m1";
};
};
For a specific board, if it wants to use sd1,
it can add the following to its board-specific .dts file.
sd1: sd@12340000 {
pinctrl-names = "default";
pinctrl-0 = <&sd1_pmx0>;
}
or
sd1: sd@12340000 {
pinctrl-names = "default";
pinctrl-0 = <&sd1_pmx1>;
}
drivers/pinctrl/Kconfig
View file @ c41e02c3
......@@ -226,14 +226,6 @@ config PINCTRL_SINGLE
help
This selects the device tree based generic pinctrl driver.
config PINCTRL_SIRF
bool "CSR SiRFprimaII pin controller driver"
depends on ARCH_SIRF
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GPIOLIB_IRQCHIP
config PINCTRL_SX150X
bool "Semtech SX150x I2C GPIO expander pinctrl driver"
depends on I2C=y
......
drivers/pinctrl/Makefile
View file @ c41e02c3
......@@ -31,7 +31,6 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
......
drivers/pinctrl/sirf/Makefile deleted 100644 → 0
View file @ 484c58d6
# SPDX-License-Identifier: GPL-2.0-only
# CSR SiRFsoc pinmux support
obj-y += pinctrl-sirf.o
obj-y += pinctrl-prima2.o
obj-y += pinctrl-atlas6.o
obj-y += pinctrl-atlas7.o
drivers/pinctrl/sirf/pinctrl-atlas6.c deleted 100644 → 0
View file @ 484c58d6
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* pinctrl pads, groups, functions for CSR SiRFatlasVI
*
* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
* company.
*/
#include <linux/pinctrl/pinctrl.h>
#include <linux/bitops.h>
#include "pinctrl-sirf.h"
/*
* pad list for the pinmux subsystem
* refer to atlasVI_io_table_v0.93.xls
*/
static const struct pinctrl_pin_desc sirfsoc_pads[] = {
PINCTRL_PIN(0, "gpio0-0"),
PINCTRL_PIN(1, "gpio0-1"),
PINCTRL_PIN(2, "gpio0-2"),
PINCTRL_PIN(3, "gpio0-3"),
PINCTRL_PIN(4, "pwm0"),
PINCTRL_PIN(5, "pwm1"),
PINCTRL_PIN(6, "pwm2"),
PINCTRL_PIN(7, "pwm3"),
PINCTRL_PIN(8, "warm_rst_b"),
PINCTRL_PIN(9, "odo_0"),
PINCTRL_PIN(10, "odo_1"),
PINCTRL_PIN(11, "dr_dir"),
PINCTRL_PIN(12, "rts_0"),
PINCTRL_PIN(13, "scl_1"),
PINCTRL_PIN(14, "ntrst"),
PINCTRL_PIN(15, "sda_1"),
PINCTRL_PIN(16, "x_ldd[16]"),
PINCTRL_PIN(17, "x_ldd[17]"),
PINCTRL_PIN(18, "x_ldd[18]"),
PINCTRL_PIN(19, "x_ldd[19]"),
PINCTRL_PIN(20, "x_ldd[20]"),
PINCTRL_PIN(21, "x_ldd[21]"),
PINCTRL_PIN(22, "x_ldd[22]"),
PINCTRL_PIN(23, "x_ldd[23]"),
PINCTRL_PIN(24, "gps_sgn"),
PINCTRL_PIN(25, "gps_mag"),
PINCTRL_PIN(26, "gps_clk"),
PINCTRL_PIN(27, "sd_cd_b_2"),
PINCTRL_PIN(28, "sd_vcc_on_2"),
PINCTRL_PIN(29, "sd_wp_b_2"),
PINCTRL_PIN(30, "sd_clk_3"),
PINCTRL_PIN(31, "sd_cmd_3"),
PINCTRL_PIN(32, "x_sd_dat_3[0]"),
PINCTRL_PIN(33, "x_sd_dat_3[1]"),
PINCTRL_PIN(34, "x_sd_dat_3[2]"),
PINCTRL_PIN(35, "x_sd_dat_3[3]"),
PINCTRL_PIN(36, "usb_clk"),
PINCTRL_PIN(37, "usb_dir"),
PINCTRL_PIN(38, "usb_nxt"),
PINCTRL_PIN(39, "usb_stp"),
PINCTRL_PIN(40, "usb_dat[7]"),
PINCTRL_PIN(41, "usb_dat[6]"),
PINCTRL_PIN(42, "x_cko_1"),
PINCTRL_PIN(43, "spi_clk_1"),
PINCTRL_PIN(44, "spi_dout_1"),
PINCTRL_PIN(45, "spi_din_1"),
PINCTRL_PIN(46, "spi_en_1"),
PINCTRL_PIN(47, "x_txd_1"),
PINCTRL_PIN(48, "x_txd_2"),
PINCTRL_PIN(49, "x_rxd_1"),
PINCTRL_PIN(50, "x_rxd_2"),
PINCTRL_PIN(51, "x_usclk_0"),
PINCTRL_PIN(52, "x_utxd_0"),
PINCTRL_PIN(53, "x_urxd_0"),
PINCTRL_PIN(54, "x_utfs_0"),
PINCTRL_PIN(55, "x_urfs_0"),
PINCTRL_PIN(56, "usb_dat5"),
PINCTRL_PIN(57, "usb_dat4"),
PINCTRL_PIN(58, "usb_dat3"),
PINCTRL_PIN(59, "usb_dat2"),
PINCTRL_PIN(60, "usb_dat1"),
PINCTRL_PIN(61, "usb_dat0"),
PINCTRL_PIN(62, "x_ldd[14]"),
PINCTRL_PIN(63, "x_ldd[15]"),
PINCTRL_PIN(64, "x_gps_gpio"),
PINCTRL_PIN(65, "x_ldd[13]"),
PINCTRL_PIN(66, "x_df_we_b"),
PINCTRL_PIN(67, "x_df_re_b"),
PINCTRL_PIN(68, "x_txd_0"),
PINCTRL_PIN(69, "x_rxd_0"),
PINCTRL_PIN(70, "x_l_lck"),
PINCTRL_PIN(71, "x_l_fck"),
PINCTRL_PIN(72, "x_l_de"),
PINCTRL_PIN(73, "x_ldd[0]"),
PINCTRL_PIN(74, "x_ldd[1]"),
PINCTRL_PIN(75, "x_ldd[2]"),
PINCTRL_PIN(76, "x_ldd[3]"),
PINCTRL_PIN(77, "x_ldd[4]"),
PINCTRL_PIN(78, "x_cko_0"),
PINCTRL_PIN(79, "x_ldd[5]"),
PINCTRL_PIN(80, "x_ldd[6]"),
PINCTRL_PIN(81, "x_ldd[7]"),
PINCTRL_PIN(82, "x_ldd[8]"),
PINCTRL_PIN(83, "x_ldd[9]"),
PINCTRL_PIN(84, "x_ldd[10]"),
PINCTRL_PIN(85, "x_ldd[11]"),
PINCTRL_PIN(86, "x_ldd[12]"),
PINCTRL_PIN(87, "x_vip_vsync"),
PINCTRL_PIN(88, "x_vip_hsync"),
PINCTRL_PIN(89, "x_vip_pxclk"),
PINCTRL_PIN(90, "x_sda_0"),
PINCTRL_PIN(91, "x_scl_0"),
PINCTRL_PIN(92, "x_df_ry_by"),
PINCTRL_PIN(93, "x_df_cs_b[1]"),
PINCTRL_PIN(94, "x_df_cs_b[0]"),
PINCTRL_PIN(95, "x_l_pclk"),
PINCTRL_PIN(96, "x_df_dqs"),
PINCTRL_PIN(97, "x_df_wp_b"),
PINCTRL_PIN(98, "ac97_sync"),
PINCTRL_PIN(99, "ac97_bit_clk "),
PINCTRL_PIN(100, "ac97_dout"),
PINCTRL_PIN(101, "ac97_din"),
PINCTRL_PIN(102, "x_rtc_io"),
PINCTRL_PIN(103, "x_usb1_dp"),
PINCTRL_PIN(104, "x_usb1_dn"),
};
static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
{
.group = 1,
.mask = BIT(30) | BIT(31),
}, {
.group = 2,
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
BIT(16) | BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
},
};
static const struct sirfsoc_padmux lcd_16bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
.muxmask = lcd_16bits_sirfsoc_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75,
76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
{
.group = 2,
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
BIT(16) | BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
}, {
.group = 1,
.mask = BIT(30) | BIT(31),
}, {
.group = 0,
.mask = BIT(16) | BIT(17),
},
};
static const struct sirfsoc_padmux lcd_18bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
.muxmask = lcd_18bits_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4) | BIT(15),
.funcval = 0,
};
static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73,
74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
{
.group = 2,
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
BIT(16) | BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
}, {
.group = 1,
.mask = BIT(30) | BIT(31),
}, {
.group = 0,
.mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
BIT(21) | BIT(22) | BIT(23),
},
};
static const struct sirfsoc_padmux lcd_24bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
.muxmask = lcd_24bits_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4) | BIT(15),
.funcval = 0,
};
static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62,
63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84,
85, 86, 95};
static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
{
.group = 2,
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) |
BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
}, {
.group = 1,
.mask = BIT(30) | BIT(31),
}, {
.group = 0,
.mask = BIT(8),
},
};
static const struct sirfsoc_padmux lcdrom_padmux = {
.muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
.muxmask = lcdrom_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = BIT(4),
};
static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75,
76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95};
static const struct sirfsoc_muxmask uart0_muxmask[] = {
{
.group = 0,
.mask = BIT(12),
}, {
.group = 1,
.mask = BIT(23),
}, {
.group = 2,
.mask = BIT(4) | BIT(5),
},
};
static const struct sirfsoc_padmux uart0_padmux = {
.muxmask_counts = ARRAY_SIZE(uart0_muxmask),
.muxmask = uart0_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(9),
.funcval = BIT(9),
};
static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
{
.group = 2,
.mask = BIT(4) | BIT(5),
},
};
static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
.muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
.muxmask = uart0_nostreamctrl_muxmask,
};
static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
static const struct sirfsoc_muxmask uart1_muxmask[] = {
{
.group = 1,
.mask = BIT(15) | BIT(17),
},
};
static const struct sirfsoc_padmux uart1_padmux = {
.muxmask_counts = ARRAY_SIZE(uart1_muxmask),
.muxmask = uart1_muxmask,
};
static const unsigned uart1_pins[] = { 47, 49 };
static const struct sirfsoc_muxmask uart2_muxmask[] = {
{
.group = 0,
.mask = BIT(10) | BIT(14),
}, {
.group = 1,
.mask = BIT(16) | BIT(18),
},
};
static const struct sirfsoc_padmux uart2_padmux = {
.muxmask_counts = ARRAY_SIZE(uart2_muxmask),
.muxmask = uart2_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(10),
.funcval = BIT(10),
};
static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
{
.group = 1,
.mask = BIT(16) | BIT(18),
},
};
static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
.muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
.muxmask = uart2_nostreamctrl_muxmask,
};
static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
{
.group = 0,
.mask = BIT(30) | BIT(31),
}, {
.group = 1,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
},
};
static const struct sirfsoc_padmux sdmmc3_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
.muxmask = sdmmc3_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = 0,
};
static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
static const struct sirfsoc_muxmask spi0_muxmask[] = {
{
.group = 0,
.mask = BIT(30),
}, {
.group = 1,
.mask = BIT(0) | BIT(2) | BIT(3),
},
};
static const struct sirfsoc_padmux spi0_padmux = {
.muxmask_counts = ARRAY_SIZE(spi0_muxmask),
.muxmask = spi0_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = BIT(7),
};
static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
static const struct sirfsoc_muxmask cko1_muxmask[] = {
{
.group = 1,
.mask = BIT(10),
},
};
static const struct sirfsoc_padmux cko1_padmux = {
.muxmask_counts = ARRAY_SIZE(cko1_muxmask),
.muxmask = cko1_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = 0,
};
static const unsigned cko1_pins[] = { 42 };
static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
{
.group = 1,
.mask = BIT(10),
},
};
static const struct sirfsoc_padmux i2s_mclk_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
.muxmask = i2s_mclk_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = BIT(3),
};
static const unsigned i2s_mclk_pins[] = { 42 };
static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
{
.group = 1,
.mask = BIT(19),
},
};
static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
.muxmask = i2s_ext_clk_input_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(2),
.funcval = BIT(2),
};
static const unsigned i2s_ext_clk_input_pins[] = { 51 };
static const struct sirfsoc_muxmask i2s_muxmask[] = {
{
.group = 3,
.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
},
};
static const struct sirfsoc_padmux i2s_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
.muxmask = i2s_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
};
static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
{
.group = 3,
.mask = BIT(2) | BIT(3) | BIT(4),
},
};
static const struct sirfsoc_padmux i2s_no_din_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
.muxmask = i2s_no_din_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
};
static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
{
.group = 3,
.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
},
};
static const struct sirfsoc_padmux i2s_6chn_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
.muxmask = i2s_6chn_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(9),
.funcval = BIT(1) | BIT(9),
};
static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
static const struct sirfsoc_muxmask ac97_muxmask[] = {
{
.group = 3,
.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
},
};
static const struct sirfsoc_padmux ac97_padmux = {
.muxmask_counts = ARRAY_SIZE(ac97_muxmask),
.muxmask = ac97_muxmask,
};
static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
static const struct sirfsoc_muxmask spi1_muxmask[] = {
{
.group = 1,
.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
},
};
static const struct sirfsoc_padmux spi1_padmux = {
.muxmask_counts = ARRAY_SIZE(spi1_muxmask),
.muxmask = spi1_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(16),
.funcval = 0,
};
static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
{
.group = 2,
.mask = BIT(2) | BIT(3),
},
};
static const struct sirfsoc_padmux sdmmc1_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
.muxmask = sdmmc1_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = BIT(5),
};
static const unsigned sdmmc1_pins[] = { 66, 67 };
static const struct sirfsoc_muxmask gps_muxmask[] = {
{
.group = 0,
.mask = BIT(24) | BIT(25) | BIT(26),
},
};
static const struct sirfsoc_padmux gps_padmux = {
.muxmask_counts = ARRAY_SIZE(gps_muxmask),
.muxmask = gps_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13),
.funcval = 0,
};
static const unsigned gps_pins[] = { 24, 25, 26 };
static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
{
.group = 0,
.mask = BIT(24) | BIT(25) | BIT(26),
},
};
static const struct sirfsoc_padmux sdmmc5_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
.muxmask = sdmmc5_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13),
.funcval = BIT(13),
};
static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
static const struct sirfsoc_muxmask usp0_muxmask[] = {
{
.group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
},
};
static const struct sirfsoc_padmux usp0_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_muxmask),
.muxmask = usp0_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(9),
.funcval = 0,
};
static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
{
.group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
},
};
static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
.muxmask = usp0_only_utfs_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(6),
.funcval = 0,
};
static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
{
.group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
},
};
static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
.muxmask = usp0_only_urfs_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(9),
.funcval = 0,
};
static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
{
.group = 1,
.mask = BIT(20) | BIT(21),
},
};
static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
.muxmask = usp0_uart_nostreamctrl_muxmask,
};
static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
static const struct sirfsoc_muxmask usp1_muxmask[] = {
{
.group = 0,
.mask = BIT(15),
}, {
.group = 1,
.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
},
};
static const struct sirfsoc_padmux usp1_padmux = {
.muxmask_counts = ARRAY_SIZE(usp1_muxmask),
.muxmask = usp1_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(16),
.funcval = BIT(16),
};
static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
{
.group = 1,
.mask = BIT(12) | BIT(13),
},
};
static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
.muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
.muxmask = usp1_uart_nostreamctrl_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(16),
.funcval = BIT(16),
};
static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 };
static const struct sirfsoc_muxmask nand_muxmask[] = {
{
.group = 2,
.mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
}, {
.group = 3,
.mask = BIT(0) | BIT(1),
},
};
static const struct sirfsoc_padmux nand_padmux = {
.muxmask_counts = ARRAY_SIZE(nand_muxmask),
.muxmask = nand_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5) | BIT(19),
.funcval = 0,
};
static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
{
.group = 3,
.mask = BIT(1),
},
};
static const struct sirfsoc_padmux sdmmc0_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
.muxmask = sdmmc0_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5) | BIT(19),
.funcval = BIT(19),
};
static const unsigned sdmmc0_pins[] = { 97 };
static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
{
.group = 0,
.mask = BIT(27) | BIT(28) | BIT(29),
},
};
static const struct sirfsoc_padmux sdmmc2_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
.muxmask = sdmmc2_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = 0,
};
static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
{
.group = 0,
.mask = BIT(27) | BIT(28),
},
};
static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
.muxmask = sdmmc2_nowp_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = 0,
};
static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
static const struct sirfsoc_muxmask cko0_muxmask[] = {
{
.group = 2,
.mask = BIT(14),
},
};
static const struct sirfsoc_padmux cko0_padmux = {
.muxmask_counts = ARRAY_SIZE(cko0_muxmask),
.muxmask = cko0_muxmask,
};
static const unsigned cko0_pins[] = { 78 };
static const struct sirfsoc_muxmask vip_muxmask[] = {
{
.group = 1,
.mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
| BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) |
BIT(29),
},
};
static const struct sirfsoc_padmux vip_padmux = {
.muxmask_counts = ARRAY_SIZE(vip_muxmask),
.muxmask = vip_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(18),
.funcval = BIT(18),
};
static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59,
60, 61 };
static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
{
.group = 0,
.mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
| BIT(21) | BIT(22) | BIT(23),
}, {
.group = 2,
.mask = BIT(23) | BIT(24) | BIT(25),
},
};
static const struct sirfsoc_padmux vip_noupli_padmux = {
.muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
.muxmask = vip_noupli_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(15),
.funcval = BIT(15),
};
static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
87, 88, 89 };
static const struct sirfsoc_muxmask i2c0_muxmask[] = {
{
.group = 2,
.mask = BIT(26) | BIT(27),
},
};
static const struct sirfsoc_padmux i2c0_padmux = {
.muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
.muxmask = i2c0_muxmask,
};
static const unsigned i2c0_pins[] = { 90, 91 };
static const struct sirfsoc_muxmask i2c1_muxmask[] = {
{
.group = 0,
.mask = BIT(13) | BIT(15),
},
};
static const struct sirfsoc_padmux i2c1_padmux = {
.muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
.muxmask = i2c1_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(16),
.funcval = 0,
};
static const unsigned i2c1_pins[] = { 13, 15 };
static const struct sirfsoc_muxmask pwm0_muxmask[] = {
{
.group = 0,
.mask = BIT(4),
},
};
static const struct sirfsoc_padmux pwm0_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
.muxmask = pwm0_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(12),
.funcval = 0,
};
static const unsigned pwm0_pins[] = { 4 };
static const struct sirfsoc_muxmask pwm1_muxmask[] = {
{
.group = 0,
.mask = BIT(5),
},
};
static const struct sirfsoc_padmux pwm1_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
.muxmask = pwm1_muxmask,
};
static const unsigned pwm1_pins[] = { 5 };
static const struct sirfsoc_muxmask pwm2_muxmask[] = {
{
.group = 0,
.mask = BIT(6),
},
};
static const struct sirfsoc_padmux pwm2_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
.muxmask = pwm2_muxmask,
};
static const unsigned pwm2_pins[] = { 6 };
static const struct sirfsoc_muxmask pwm3_muxmask[] = {
{
.group = 0,
.mask = BIT(7),
},
};
static const struct sirfsoc_padmux pwm3_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
.muxmask = pwm3_muxmask,
};
static const unsigned pwm3_pins[] = { 7 };
static const struct sirfsoc_muxmask pwm4_muxmask[] = {
{
.group = 2,
.mask = BIT(14),
},
};
static const struct sirfsoc_padmux pwm4_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
.muxmask = pwm4_muxmask,
};
static const unsigned pwm4_pins[] = { 78 };
static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
{
.group = 0,
.mask = BIT(8),
},
};
static const struct sirfsoc_padmux warm_rst_padmux = {
.muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
.muxmask = warm_rst_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
static const unsigned warm_rst_pins[] = { 8 };
static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
{
.group = 1,
.mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
| BIT(9) | BIT(24) | BIT(25) | BIT(26) |
BIT(27) | BIT(28) | BIT(29),
},
};
static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
.muxmask = usb0_upli_drvbus_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(18),
.funcval = 0,
};
static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40,
41, 56, 57, 58, 59, 60, 61 };
static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
{
.group = 0,
.mask = BIT(28),
},
};
static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
.muxmask = usb1_utmi_drvbus_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
};
static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
.muxmask_counts = 0,
.ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
.funcmask = BIT(2),
.funcval = BIT(2),
};
static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
.muxmask_counts = 0,
.ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
.funcmask = BIT(2),
.funcval = 0,
};
static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
{
.group = 0,
.mask = BIT(9) | BIT(10) | BIT(11),
},
};
static const struct sirfsoc_padmux pulse_count_padmux = {
.muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
.muxmask = pulse_count_muxmask,
};
static const unsigned pulse_count_pins[] = { 9, 10, 11 };
static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
usp0_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
usp1_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
};
static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
static const char * const lcdromgrp[] = { "lcdromgrp" };
static const char * const uart0grp[] = { "uart0grp" };
static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
static const char * const uart1grp[] = { "uart1grp" };
static const char * const uart2grp[] = { "uart2grp" };
static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
static const char * const usp0_uart_nostreamctrl_grp[] = {
"usp0_uart_nostreamctrl_grp" };
static const char * const usp0grp[] = { "usp0grp" };
static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
static const char * const usp1grp[] = { "usp1grp" };
static const char * const usp1_uart_nostreamctrl_grp[] = {
"usp1_uart_nostreamctrl_grp" };
static const char * const i2c0grp[] = { "i2c0grp" };
static const char * const i2c1grp[] = { "i2c1grp" };
static const char * const pwm0grp[] = { "pwm0grp" };
static const char * const pwm1grp[] = { "pwm1grp" };
static const char * const pwm2grp[] = { "pwm2grp" };
static const char * const pwm3grp[] = { "pwm3grp" };
static const char * const pwm4grp[] = { "pwm4grp" };
static const char * const vipgrp[] = { "vipgrp" };
static const char * const vip_noupligrp[] = { "vip_noupligrp" };
static const char * const warm_rstgrp[] = { "warm_rstgrp" };
static const char * const cko0grp[] = { "cko0grp" };
static const char * const cko1grp[] = { "cko1grp" };
static const char * const sdmmc0grp[] = { "sdmmc0grp" };
static const char * const sdmmc1grp[] = { "sdmmc1grp" };
static const char * const sdmmc2grp[] = { "sdmmc2grp" };
static const char * const sdmmc3grp[] = { "sdmmc3grp" };
static const char * const sdmmc5grp[] = { "sdmmc5grp" };
static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
static const char * const
uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const pulse_countgrp[] = { "pulse_countgrp" };
static const char * const i2smclkgrp[] = { "i2smclkgrp" };
static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
static const char * const i2sgrp[] = { "i2sgrp" };
static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
static const char * const ac97grp[] = { "ac97grp" };
static const char * const nandgrp[] = { "nandgrp" };
static const char * const spi0grp[] = { "spi0grp" };
static const char * const spi1grp[] = { "spi1grp" };
static const char * const gpsgrp[] = { "gpsgrp" };
static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp,
uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
usp0_uart_nostreamctrl_grp,
usp0_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp,
usp0_only_utfs_padmux),
SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp,
usp0_only_urfs_padmux),
SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
usp1_uart_nostreamctrl_grp,
usp1_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc2_nowp",
sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus",
usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
i2s_ext_clk_input_padmux),
SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
};
struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
(struct pinctrl_pin_desc *)sirfsoc_pads,
ARRAY_SIZE(sirfsoc_pads),
(struct sirfsoc_pin_group *)sirfsoc_pin_groups,
ARRAY_SIZE(sirfsoc_pin_groups),
(struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
ARRAY_SIZE(sirfsoc_pmx_functions),
};
drivers/pinctrl/sirf/pinctrl-atlas7.c deleted 100644 → 0
View file @ 484c58d6
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/pinctrl/sirf/pinctrl-prima2.c deleted 100644 → 0
View file @ 484c58d6
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* pinctrl pads, groups, functions for CSR SiRFprimaII
*
* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
* company.
*/
#include <linux/pinctrl/pinctrl.h>
#include <linux/bitops.h>
#include "pinctrl-sirf.h"
/*
* pad list for the pinmux subsystem
* refer to CS-131858-DC-6A.xls
*/
static const struct pinctrl_pin_desc sirfsoc_pads[] = {
PINCTRL_PIN(0, "gpio0-0"),
PINCTRL_PIN(1, "gpio0-1"),
PINCTRL_PIN(2, "gpio0-2"),
PINCTRL_PIN(3, "gpio0-3"),
PINCTRL_PIN(4, "pwm0"),
PINCTRL_PIN(5, "pwm1"),
PINCTRL_PIN(6, "pwm2"),
PINCTRL_PIN(7, "pwm3"),
PINCTRL_PIN(8, "warm_rst_b"),
PINCTRL_PIN(9, "odo_0"),
PINCTRL_PIN(10, "odo_1"),
PINCTRL_PIN(11, "dr_dir"),
PINCTRL_PIN(12, "viprom_fa"),
PINCTRL_PIN(13, "scl_1"),
PINCTRL_PIN(14, "ntrst"),
PINCTRL_PIN(15, "sda_1"),
PINCTRL_PIN(16, "x_ldd[16]"),
PINCTRL_PIN(17, "x_ldd[17]"),
PINCTRL_PIN(18, "x_ldd[18]"),
PINCTRL_PIN(19, "x_ldd[19]"),
PINCTRL_PIN(20, "x_ldd[20]"),
PINCTRL_PIN(21, "x_ldd[21]"),
PINCTRL_PIN(22, "x_ldd[22]"),
PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
PINCTRL_PIN(24, "gps_sgn"),
PINCTRL_PIN(25, "gps_mag"),
PINCTRL_PIN(26, "gps_clk"),
PINCTRL_PIN(27, "sd_cd_b_1"),
PINCTRL_PIN(28, "sd_vcc_on_1"),
PINCTRL_PIN(29, "sd_wp_b_1"),
PINCTRL_PIN(30, "sd_clk_3"),
PINCTRL_PIN(31, "sd_cmd_3"),
PINCTRL_PIN(32, "x_sd_dat_3[0]"),
PINCTRL_PIN(33, "x_sd_dat_3[1]"),
PINCTRL_PIN(34, "x_sd_dat_3[2]"),
PINCTRL_PIN(35, "x_sd_dat_3[3]"),
PINCTRL_PIN(36, "x_sd_clk_4"),
PINCTRL_PIN(37, "x_sd_cmd_4"),
PINCTRL_PIN(38, "x_sd_dat_4[0]"),
PINCTRL_PIN(39, "x_sd_dat_4[1]"),
PINCTRL_PIN(40, "x_sd_dat_4[2]"),
PINCTRL_PIN(41, "x_sd_dat_4[3]"),
PINCTRL_PIN(42, "x_cko_1"),
PINCTRL_PIN(43, "x_ac97_bit_clk"),
PINCTRL_PIN(44, "x_ac97_dout"),
PINCTRL_PIN(45, "x_ac97_din"),
PINCTRL_PIN(46, "x_ac97_sync"),
PINCTRL_PIN(47, "x_txd_1"),
PINCTRL_PIN(48, "x_txd_2"),
PINCTRL_PIN(49, "x_rxd_1"),
PINCTRL_PIN(50, "x_rxd_2"),
PINCTRL_PIN(51, "x_usclk_0"),
PINCTRL_PIN(52, "x_utxd_0"),
PINCTRL_PIN(53, "x_urxd_0"),
PINCTRL_PIN(54, "x_utfs_0"),
PINCTRL_PIN(55, "x_urfs_0"),
PINCTRL_PIN(56, "x_usclk_1"),
PINCTRL_PIN(57, "x_utxd_1"),
PINCTRL_PIN(58, "x_urxd_1"),
PINCTRL_PIN(59, "x_utfs_1"),
PINCTRL_PIN(60, "x_urfs_1"),
PINCTRL_PIN(61, "x_usclk_2"),
PINCTRL_PIN(62, "x_utxd_2"),
PINCTRL_PIN(63, "x_urxd_2"),
PINCTRL_PIN(64, "x_utfs_2"),
PINCTRL_PIN(65, "x_urfs_2"),
PINCTRL_PIN(66, "x_df_we_b"),
PINCTRL_PIN(67, "x_df_re_b"),
PINCTRL_PIN(68, "x_txd_0"),
PINCTRL_PIN(69, "x_rxd_0"),
PINCTRL_PIN(78, "x_cko_0"),
PINCTRL_PIN(79, "x_vip_pxd[7]"),
PINCTRL_PIN(80, "x_vip_pxd[6]"),
PINCTRL_PIN(81, "x_vip_pxd[5]"),
PINCTRL_PIN(82, "x_vip_pxd[4]"),
PINCTRL_PIN(83, "x_vip_pxd[3]"),
PINCTRL_PIN(84, "x_vip_pxd[2]"),
PINCTRL_PIN(85, "x_vip_pxd[1]"),
PINCTRL_PIN(86, "x_vip_pxd[0]"),
PINCTRL_PIN(87, "x_vip_vsync"),
PINCTRL_PIN(88, "x_vip_hsync"),
PINCTRL_PIN(89, "x_vip_pxclk"),
PINCTRL_PIN(90, "x_sda_0"),
PINCTRL_PIN(91, "x_scl_0"),
PINCTRL_PIN(92, "x_df_ry_by"),
PINCTRL_PIN(93, "x_df_cs_b[1]"),
PINCTRL_PIN(94, "x_df_cs_b[0]"),
PINCTRL_PIN(95, "x_l_pclk"),
PINCTRL_PIN(96, "x_l_lck"),
PINCTRL_PIN(97, "x_l_fck"),
PINCTRL_PIN(98, "x_l_de"),
PINCTRL_PIN(99, "x_ldd[0]"),
PINCTRL_PIN(100, "x_ldd[1]"),
PINCTRL_PIN(101, "x_ldd[2]"),
PINCTRL_PIN(102, "x_ldd[3]"),
PINCTRL_PIN(103, "x_ldd[4]"),
PINCTRL_PIN(104, "x_ldd[5]"),
PINCTRL_PIN(105, "x_ldd[6]"),
PINCTRL_PIN(106, "x_ldd[7]"),
PINCTRL_PIN(107, "x_ldd[8]"),
PINCTRL_PIN(108, "x_ldd[9]"),
PINCTRL_PIN(109, "x_ldd[10]"),
PINCTRL_PIN(110, "x_ldd[11]"),
PINCTRL_PIN(111, "x_ldd[12]"),
PINCTRL_PIN(112, "x_ldd[13]"),
PINCTRL_PIN(113, "x_ldd[14]"),
PINCTRL_PIN(114, "x_ldd[15]"),
PINCTRL_PIN(115, "x_usb1_dp"),
PINCTRL_PIN(116, "x_usb1_dn"),
};
static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
{
.group = 3,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
.mask = BIT(31),
},
};
static const struct sirfsoc_padmux lcd_16bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
.muxmask = lcd_16bits_sirfsoc_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
{
.group = 3,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
.mask = BIT(31),
}, {
.group = 0,
.mask = BIT(16) | BIT(17),
},
};
static const struct sirfsoc_padmux lcd_18bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
.muxmask = lcd_18bits_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
{
.group = 3,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
.mask = BIT(31),
}, {
.group = 0,
.mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
BIT(21) | BIT(22) | BIT(23),
},
};
static const struct sirfsoc_padmux lcd_24bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
.muxmask = lcd_24bits_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
110, 111, 112, 113, 114 };
static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
{
.group = 3,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
.mask = BIT(31),
}, {
.group = 0,
.mask = BIT(23),
},
};
static const struct sirfsoc_padmux lcdrom_padmux = {
.muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
.muxmask = lcdrom_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = BIT(4),
};
static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
static const struct sirfsoc_muxmask uart0_muxmask[] = {
{
.group = 2,
.mask = BIT(4) | BIT(5),
}, {
.group = 1,
.mask = BIT(23) | BIT(28),
},
};
static const struct sirfsoc_padmux uart0_padmux = {
.muxmask_counts = ARRAY_SIZE(uart0_muxmask),
.muxmask = uart0_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(9),
.funcval = BIT(9),
};
static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
{
.group = 2,
.mask = BIT(4) | BIT(5),
},
};
static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
.muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
.muxmask = uart0_nostreamctrl_muxmask,
};
static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
static const struct sirfsoc_muxmask uart1_muxmask[] = {
{
.group = 1,
.mask = BIT(15) | BIT(17),
},
};
static const struct sirfsoc_padmux uart1_padmux = {
.muxmask_counts = ARRAY_SIZE(uart1_muxmask),
.muxmask = uart1_muxmask,
};
static const unsigned uart1_pins[] = { 47, 49 };
static const struct sirfsoc_muxmask uart2_muxmask[] = {
{
.group = 1,
.mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
},
};
static const struct sirfsoc_padmux uart2_padmux = {
.muxmask_counts = ARRAY_SIZE(uart2_muxmask),
.muxmask = uart2_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(10),
.funcval = BIT(10),
};
static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
{
.group = 1,
.mask = BIT(16) | BIT(18),
},
};
static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
.muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
.muxmask = uart2_nostreamctrl_muxmask,
};
static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
{
.group = 0,
.mask = BIT(30) | BIT(31),
}, {
.group = 1,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
},
};
static const struct sirfsoc_padmux sdmmc3_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
.muxmask = sdmmc3_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = 0,
};
static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
static const struct sirfsoc_muxmask spi0_muxmask[] = {
{
.group = 1,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
},
};
static const struct sirfsoc_padmux spi0_padmux = {
.muxmask_counts = ARRAY_SIZE(spi0_muxmask),
.muxmask = spi0_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = BIT(7),
};
static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
{
.group = 1,
.mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
},
};
static const struct sirfsoc_padmux sdmmc4_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
.muxmask = sdmmc4_muxmask,
};
static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
static const struct sirfsoc_muxmask cko1_muxmask[] = {
{
.group = 1,
.mask = BIT(10),
},
};
static const struct sirfsoc_padmux cko1_padmux = {
.muxmask_counts = ARRAY_SIZE(cko1_muxmask),
.muxmask = cko1_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = 0,
};
static const unsigned cko1_pins[] = { 42 };
static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
{
.group = 1,
.mask = BIT(10),
},
};
static const struct sirfsoc_padmux i2s_mclk_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
.muxmask = i2s_mclk_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = BIT(3),
};
static const unsigned i2s_mclk_pins[] = { 42 };
static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
{
.group = 1,
.mask = BIT(19),
},
};
static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
.muxmask = i2s_ext_clk_input_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(2),
.funcval = BIT(2),
};
static const unsigned i2s_ext_clk_input_pins[] = { 51 };
static const struct sirfsoc_muxmask i2s_muxmask[] = {
{
.group = 1,
.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
},
};
static const struct sirfsoc_padmux i2s_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
.muxmask = i2s_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
};
static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
{
.group = 1,
.mask = BIT(11) | BIT(12) | BIT(14),
},
};
static const struct sirfsoc_padmux i2s_no_din_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
.muxmask = i2s_no_din_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
};
static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
{
.group = 1,
.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
| BIT(23) | BIT(28),
},
};
static const struct sirfsoc_padmux i2s_6chn_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
.muxmask = i2s_6chn_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(9),
.funcval = BIT(1) | BIT(9),
};
static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60 };
static const struct sirfsoc_muxmask ac97_muxmask[] = {
{
.group = 1,
.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
},
};
static const struct sirfsoc_padmux ac97_padmux = {
.muxmask_counts = ARRAY_SIZE(ac97_muxmask),
.muxmask = ac97_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(8),
.funcval = 0,
};
static const unsigned ac97_pins[] = { 43, 44, 45, 46 };
static const struct sirfsoc_muxmask spi1_muxmask[] = {
{
.group = 1,
.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
},
};
static const struct sirfsoc_padmux spi1_padmux = {
.muxmask_counts = ARRAY_SIZE(spi1_muxmask),
.muxmask = spi1_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(8),
.funcval = BIT(8),
};
static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
{
.group = 0,
.mask = BIT(27) | BIT(28) | BIT(29),
},
};
static const struct sirfsoc_padmux sdmmc1_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
.muxmask = sdmmc1_muxmask,
};
static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
static const struct sirfsoc_muxmask gps_muxmask[] = {
{
.group = 0,
.mask = BIT(24) | BIT(25) | BIT(26),
},
};
static const struct sirfsoc_padmux gps_padmux = {
.muxmask_counts = ARRAY_SIZE(gps_muxmask),
.muxmask = gps_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(12) | BIT(13) | BIT(14),
.funcval = BIT(12),
};
static const unsigned gps_pins[] = { 24, 25, 26 };
static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
{
.group = 0,
.mask = BIT(24) | BIT(25) | BIT(26),
},
};
static const struct sirfsoc_padmux sdmmc5_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
.muxmask = sdmmc5_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13) | BIT(14),
.funcval = BIT(13) | BIT(14),
};
static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
static const struct sirfsoc_muxmask usp0_muxmask[] = {
{
.group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
},
};
static const struct sirfsoc_padmux usp0_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_muxmask),
.muxmask = usp0_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
.funcval = 0,
};
static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
{
.group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
},
};
static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
.muxmask = usp0_only_utfs_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(6),
.funcval = 0,
};
static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
{
.group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
},
};
static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
.muxmask = usp0_only_urfs_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(9),
.funcval = 0,
};
static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
{
.group = 1,
.mask = BIT(20) | BIT(21),
},
};
static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
.muxmask = usp0_uart_nostreamctrl_muxmask,
};
static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
static const struct sirfsoc_muxmask usp1_muxmask[] = {
{
.group = 1,
.mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
},
};
static const struct sirfsoc_padmux usp1_padmux = {
.muxmask_counts = ARRAY_SIZE(usp1_muxmask),
.muxmask = usp1_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
.funcval = 0,
};
static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
{
.group = 1,
.mask = BIT(25) | BIT(26),
},
};
static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
.muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
.muxmask = usp1_uart_nostreamctrl_muxmask,
};
static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
static const struct sirfsoc_muxmask usp2_muxmask[] = {
{
.group = 1,
.mask = BIT(29) | BIT(30) | BIT(31),
}, {
.group = 2,
.mask = BIT(0) | BIT(1),
},
};
static const struct sirfsoc_padmux usp2_padmux = {
.muxmask_counts = ARRAY_SIZE(usp2_muxmask),
.muxmask = usp2_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13) | BIT(14),
.funcval = 0,
};
static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
{
.group = 1,
.mask = BIT(30) | BIT(31),
},
};
static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
.muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
.muxmask = usp2_uart_nostreamctrl_muxmask,
};
static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
static const struct sirfsoc_muxmask nand_muxmask[] = {
{
.group = 2,
.mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
},
};
static const struct sirfsoc_padmux nand_padmux = {
.muxmask_counts = ARRAY_SIZE(nand_muxmask),
.muxmask = nand_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = 0,
};
static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
static const struct sirfsoc_padmux sdmmc0_padmux = {
.muxmask_counts = 0,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = 0,
};
static const unsigned sdmmc0_pins[] = { };
static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
{
.group = 2,
.mask = BIT(2) | BIT(3),
},
};
static const struct sirfsoc_padmux sdmmc2_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
.muxmask = sdmmc2_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = BIT(5),
};
static const unsigned sdmmc2_pins[] = { 66, 67 };
static const struct sirfsoc_muxmask cko0_muxmask[] = {
{
.group = 2,
.mask = BIT(14),
},
};
static const struct sirfsoc_padmux cko0_padmux = {
.muxmask_counts = ARRAY_SIZE(cko0_muxmask),
.muxmask = cko0_muxmask,
};
static const unsigned cko0_pins[] = { 78 };
static const struct sirfsoc_muxmask vip_muxmask[] = {
{
.group = 2,
.mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
| BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
BIT(25),
},
};
static const struct sirfsoc_padmux vip_padmux = {
.muxmask_counts = ARRAY_SIZE(vip_muxmask),
.muxmask = vip_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(0),
.funcval = 0,
};
static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
88, 89 };
static const struct sirfsoc_muxmask i2c0_muxmask[] = {
{
.group = 2,
.mask = BIT(26) | BIT(27),
},
};
static const struct sirfsoc_padmux i2c0_padmux = {
.muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
.muxmask = i2c0_muxmask,
};
static const unsigned i2c0_pins[] = { 90, 91 };
static const struct sirfsoc_muxmask i2c1_muxmask[] = {
{
.group = 0,
.mask = BIT(13) | BIT(15),
},
};
static const struct sirfsoc_padmux i2c1_padmux = {
.muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
.muxmask = i2c1_muxmask,
};
static const unsigned i2c1_pins[] = { 13, 15 };
static const struct sirfsoc_muxmask viprom_muxmask[] = {
{
.group = 2,
.mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
| BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
BIT(25),
}, {
.group = 0,
.mask = BIT(12),
},
};
static const struct sirfsoc_padmux viprom_padmux = {
.muxmask_counts = ARRAY_SIZE(viprom_muxmask),
.muxmask = viprom_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(0),
.funcval = BIT(0),
};
static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
87, 88, 89 };
static const struct sirfsoc_muxmask pwm0_muxmask[] = {
{
.group = 0,
.mask = BIT(4),
},
};
static const struct sirfsoc_padmux pwm0_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
.muxmask = pwm0_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(12),
.funcval = 0,
};
static const unsigned pwm0_pins[] = { 4 };
static const struct sirfsoc_muxmask pwm1_muxmask[] = {
{
.group = 0,
.mask = BIT(5),
},
};
static const struct sirfsoc_padmux pwm1_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
.muxmask = pwm1_muxmask,
};
static const unsigned pwm1_pins[] = { 5 };
static const struct sirfsoc_muxmask pwm2_muxmask[] = {
{
.group = 0,
.mask = BIT(6),
},
};
static const struct sirfsoc_padmux pwm2_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
.muxmask = pwm2_muxmask,
};
static const unsigned pwm2_pins[] = { 6 };
static const struct sirfsoc_muxmask pwm3_muxmask[] = {
{
.group = 0,
.mask = BIT(7),
},
};
static const struct sirfsoc_padmux pwm3_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
.muxmask = pwm3_muxmask,
};
static const unsigned pwm3_pins[] = { 7 };
static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
{
.group = 0,
.mask = BIT(8),
},
};
static const struct sirfsoc_padmux warm_rst_padmux = {
.muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
.muxmask = warm_rst_muxmask,
};
static const unsigned warm_rst_pins[] = { 8 };
static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
{
.group = 1,
.mask = BIT(22),
},
};
static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
.muxmask = usb0_utmi_drvbus_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(6),
.funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
};
static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
{
.group = 1,
.mask = BIT(27),
},
};
static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
.muxmask = usb1_utmi_drvbus_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
};
static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
.muxmask_counts = 0,
.ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
.funcmask = BIT(2),
.funcval = BIT(2),
};
static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
.muxmask_counts = 0,
.ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
.funcmask = BIT(2),
.funcval = 0,
};
static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
{
.group = 0,
.mask = BIT(9) | BIT(10) | BIT(11),
},
};
static const struct sirfsoc_padmux pulse_count_padmux = {
.muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
.muxmask = pulse_count_muxmask,
};
static const unsigned pulse_count_pins[] = { 9, 10, 11 };
static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
usp0_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
usp1_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
usp2_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
};
static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
static const char * const lcdromgrp[] = { "lcdromgrp" };
static const char * const uart0grp[] = { "uart0grp" };
static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
static const char * const uart1grp[] = { "uart1grp" };
static const char * const uart2grp[] = { "uart2grp" };
static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
static const char * const usp0grp[] = { "usp0grp" };
static const char * const usp0_uart_nostreamctrl_grp[] = {
"usp0_uart_nostreamctrl_grp"
};
static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
static const char * const usp1grp[] = { "usp1grp" };
static const char * const usp1_uart_nostreamctrl_grp[] = {
"usp1_uart_nostreamctrl_grp"
};
static const char * const usp2grp[] = { "usp2grp" };
static const char * const usp2_uart_nostreamctrl_grp[] = {
"usp2_uart_nostreamctrl_grp"
};
static const char * const i2c0grp[] = { "i2c0grp" };
static const char * const i2c1grp[] = { "i2c1grp" };
static const char * const pwm0grp[] = { "pwm0grp" };
static const char * const pwm1grp[] = { "pwm1grp" };
static const char * const pwm2grp[] = { "pwm2grp" };
static const char * const pwm3grp[] = { "pwm3grp" };
static const char * const vipgrp[] = { "vipgrp" };
static const char * const vipromgrp[] = { "vipromgrp" };
static const char * const warm_rstgrp[] = { "warm_rstgrp" };
static const char * const cko0grp[] = { "cko0grp" };
static const char * const cko1grp[] = { "cko1grp" };
static const char * const sdmmc0grp[] = { "sdmmc0grp" };
static const char * const sdmmc1grp[] = { "sdmmc1grp" };
static const char * const sdmmc2grp[] = { "sdmmc2grp" };
static const char * const sdmmc3grp[] = { "sdmmc3grp" };
static const char * const sdmmc4grp[] = { "sdmmc4grp" };
static const char * const sdmmc5grp[] = { "sdmmc5grp" };
static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
static const char * const
uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const pulse_countgrp[] = { "pulse_countgrp" };
static const char * const i2smclkgrp[] = { "i2smclkgrp" };
static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
static const char * const i2sgrp[] = { "i2sgrp" };
static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
static const char * const ac97grp[] = { "ac97grp" };
static const char * const nandgrp[] = { "nandgrp" };
static const char * const spi0grp[] = { "spi0grp" };
static const char * const spi1grp[] = { "spi1grp" };
static const char * const gpsgrp[] = { "gpsgrp" };
static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
usp0_only_utfs_grp, usp0_only_utfs_padmux),
SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
usp0_only_urfs_grp, usp0_only_urfs_padmux),
SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
i2s_ext_clk_input_padmux),
SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
};
struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
(struct pinctrl_pin_desc *)sirfsoc_pads,
ARRAY_SIZE(sirfsoc_pads),
(struct sirfsoc_pin_group *)sirfsoc_pin_groups,
ARRAY_SIZE(sirfsoc_pin_groups),
(struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
ARRAY_SIZE(sirfsoc_pmx_functions),
};
drivers/pinctrl/sirf/pinctrl-sirf.c deleted 100644 → 0
View file @ 484c58d6
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* pinmux driver for CSR SiRFprimaII
*
* Authors:
* Rongjun Ying <rongjun.ying@csr.com>
* Yuping Luo <yuping.luo@csr.com>
* Barry Song <baohua.song@csr.com>
*
* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
* company.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/of_gpio.h>
#include "pinctrl-sirf.h"
#define DRIVER_NAME "pinmux-sirf"
struct sirfsoc_gpio_bank {
int id;
int parent_irq;
spinlock_t lock;
};
struct sirfsoc_gpio_chip {
struct of_mm_gpio_chip chip;
struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
spinlock_t lock;
};
static struct sirfsoc_pin_group *sirfsoc_pin_groups;
static int sirfsoc_pingrp_cnt;
static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
{
return sirfsoc_pingrp_cnt;
}
static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return sirfsoc_pin_groups[selector].name;
}
static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
unsigned selector,
const unsigned **pins,
unsigned *num_pins)
{
*pins = sirfsoc_pin_groups[selector].pins;
*num_pins = sirfsoc_pin_groups[selector].num_pins;
return 0;
}
static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned offset)
{
seq_printf(s, " " DRIVER_NAME);
}
static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps)
{
struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
struct device_node *np;
struct property *prop;
const char *function, *group;
int ret, index = 0, count = 0;
/* calculate number of maps required */
for_each_child_of_node(np_config, np) {
ret = of_property_read_string(np, "sirf,function", &function);
if (ret < 0) {
of_node_put(np);
return ret;
}
ret = of_property_count_strings(np, "sirf,pins");
if (ret < 0) {
of_node_put(np);
return ret;
}
count += ret;
}
if (!count) {
dev_err(spmx->dev, "No child nodes passed via DT\n");
return -ENODEV;
}
*map = kcalloc(count, sizeof(**map), GFP_KERNEL);
if (!*map)
return -ENOMEM;
for_each_child_of_node(np_config, np) {
of_property_read_string(np, "sirf,function", &function);
of_property_for_each_string(np, "sirf,pins", prop, group) {
(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[index].data.mux.group = group;
(*map)[index].data.mux.function = function;
index++;
}
}
*num_maps = count;
return 0;
}
static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
kfree(map);
}
static const struct pinctrl_ops sirfsoc_pctrl_ops = {
.get_groups_count = sirfsoc_get_groups_count,
.get_group_name = sirfsoc_get_group_name,
.get_group_pins = sirfsoc_get_group_pins,
.pin_dbg_show = sirfsoc_pin_dbg_show,
.dt_node_to_map = sirfsoc_dt_node_to_map,
.dt_free_map = sirfsoc_dt_free_map,
};
static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
static int sirfsoc_pmxfunc_cnt;
static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
unsigned selector, bool enable)
{
int i;
const struct sirfsoc_padmux *mux =
sirfsoc_pmx_functions[selector].padmux;
const struct sirfsoc_muxmask *mask = mux->muxmask;
for (i = 0; i < mux->muxmask_counts; i++) {
u32 muxval;
muxval = readl(spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(mask[i].group));
if (enable)
muxval = muxval & ~mask[i].mask;
else
muxval = muxval | mask[i].mask;
writel(muxval, spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(mask[i].group));
}
if (mux->funcmask && enable) {
u32 func_en_val;
func_en_val =
readl(spmx->rsc_virtbase + mux->ctrlreg);
func_en_val =
(func_en_val & ~mux->funcmask) | (mux->funcval);
writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
}
}
static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
unsigned selector,
unsigned group)
{
struct sirfsoc_pmx *spmx;
spmx = pinctrl_dev_get_drvdata(pmxdev);
sirfsoc_pinmux_endisable(spmx, selector, true);
return 0;
}
static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
{
return sirfsoc_pmxfunc_cnt;
}
static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return sirfsoc_pmx_functions[selector].name;
}
static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = sirfsoc_pmx_functions[selector].groups;
*num_groups = sirfsoc_pmx_functions[selector].num_groups;
return 0;
}
static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
struct pinctrl_gpio_range *range, unsigned offset)
{
struct sirfsoc_pmx *spmx;
int group = range->id;
u32 muxval;
spmx = pinctrl_dev_get_drvdata(pmxdev);
muxval = readl(spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(group));
muxval = muxval | (1 << (offset - range->pin_base));
writel(muxval, spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(group));
return 0;
}
static const struct pinmux_ops sirfsoc_pinmux_ops = {
.set_mux = sirfsoc_pinmux_set_mux,
.get_functions_count = sirfsoc_pinmux_get_funcs_count,
.get_function_name = sirfsoc_pinmux_get_func_name,
.get_function_groups = sirfsoc_pinmux_get_groups,
.gpio_request_enable = sirfsoc_pinmux_request_gpio,
};
static struct pinctrl_desc sirfsoc_pinmux_desc = {
.name = DRIVER_NAME,
.pctlops = &sirfsoc_pctrl_ops,
.pmxops = &sirfsoc_pinmux_ops,
.owner = THIS_MODULE,
};
static void __iomem *sirfsoc_rsc_of_iomap(void)
{
const struct of_device_id rsc_ids[] = {
{ .compatible = "sirf,prima2-rsc" },
{}
};
struct device_node *np;
np = of_find_matching_node(NULL, rsc_ids);
if (!np)
panic("unable to find compatible rsc node in dtb\n");
return of_iomap(np, 0);
}
static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
const struct of_phandle_args *gpiospec,
u32 *flags)
{
if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
return -EINVAL;
if (flags)
*flags = gpiospec->args[1];
return gpiospec->args[0];
}
static const struct of_device_id pinmux_ids[] = {
{ .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
{ .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
{}
};
static int sirfsoc_pinmux_probe(struct platform_device *pdev)
{
int ret;
struct sirfsoc_pmx *spmx;
struct device_node *np = pdev->dev.of_node;
const struct sirfsoc_pinctrl_data *pdata;
/* Create state holders etc for this driver */
spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
if (!spmx)
return -ENOMEM;
spmx->dev = &pdev->dev;
platform_set_drvdata(pdev, spmx);
spmx->gpio_virtbase = of_iomap(np, 0);
if (!spmx->gpio_virtbase) {
dev_err(&pdev->dev, "can't map gpio registers\n");
return -ENOMEM;
}
spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
if (!spmx->rsc_virtbase) {
ret = -ENOMEM;
dev_err(&pdev->dev, "can't map rsc registers\n");
goto out_no_rsc_remap;
}
pdata = of_match_node(pinmux_ids, np)->data;
sirfsoc_pin_groups = pdata->grps;
sirfsoc_pingrp_cnt = pdata->grps_cnt;
sirfsoc_pmx_functions = pdata->funcs;
sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
sirfsoc_pinmux_desc.pins = pdata->pads;
sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
/* Now register the pin controller and all pins it handles */
spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
if (IS_ERR(spmx->pmx)) {
dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
ret = PTR_ERR(spmx->pmx);
goto out_no_pmx;
}
dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
return 0;
out_no_pmx:
iounmap(spmx->rsc_virtbase);
out_no_rsc_remap:
iounmap(spmx->gpio_virtbase);
return ret;
}
#ifdef CONFIG_PM_SLEEP
static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
{
int i, j;
struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
SIRFSOC_GPIO_CTRL(i, j));
}
spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
SIRFSOC_GPIO_INT_STATUS(i));
spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(i));
}
spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
for (i = 0; i < 3; i++)
spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
return 0;
}
static int sirfsoc_pinmux_resume_noirq(struct device *dev)
{
int i, j;
struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
SIRFSOC_GPIO_CTRL(i, j));
}
writel(spmx->ints_regs[i], spmx->gpio_virtbase +
SIRFSOC_GPIO_INT_STATUS(i));
writel(spmx->paden_regs[i], spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(i));
}
writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
for (i = 0; i < 3; i++)
writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
return 0;
}
static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
.suspend_noirq = sirfsoc_pinmux_suspend_noirq,
.resume_noirq = sirfsoc_pinmux_resume_noirq,
.freeze_noirq = sirfsoc_pinmux_suspend_noirq,
.restore_noirq = sirfsoc_pinmux_resume_noirq,
};
#endif
static struct platform_driver sirfsoc_pinmux_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = pinmux_ids,
#ifdef CONFIG_PM_SLEEP
.pm = &sirfsoc_pinmux_pm_ops,
#endif
},
.probe = sirfsoc_pinmux_probe,
};
static int __init sirfsoc_pinmux_init(void)
{
return platform_driver_register(&sirfsoc_pinmux_driver);
}
arch_initcall(sirfsoc_pinmux_init);
static inline struct sirfsoc_gpio_bank *
sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
{
return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
}
static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
{
return offset % SIRFSOC_GPIO_BANK_SIZE;
}
static void sirfsoc_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
u32 val, offset;
unsigned long flags;
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
spin_lock_irqsave(&sgpio->lock, flags);
val = readl(sgpio->chip.regs + offset);
writel(val, sgpio->chip.regs + offset);
spin_unlock_irqrestore(&sgpio->lock, flags);
}
static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
struct sirfsoc_gpio_bank *bank,
int idx)
{
u32 val, offset;
unsigned long flags;
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
spin_lock_irqsave(&sgpio->lock, flags);
val = readl(sgpio->chip.regs + offset);
val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
writel(val, sgpio->chip.regs + offset);
spin_unlock_irqrestore(&sgpio->lock, flags);
}
static void sirfsoc_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
__sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
}
static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
u32 val, offset;
unsigned long flags;
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
spin_lock_irqsave(&sgpio->lock, flags);
val = readl(sgpio->chip.regs + offset);
val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
writel(val, sgpio->chip.regs + offset);
spin_unlock_irqrestore(&sgpio->lock, flags);
}
static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
u32 val, offset;
unsigned long flags;
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
spin_lock_irqsave(&sgpio->lock, flags);
val = readl(sgpio->chip.regs + offset);
val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
switch (type) {
case IRQ_TYPE_NONE:
break;
case IRQ_TYPE_EDGE_RISING:
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
break;
case IRQ_TYPE_EDGE_FALLING:
val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
break;
case IRQ_TYPE_EDGE_BOTH:
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
break;
case IRQ_TYPE_LEVEL_LOW:
val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
break;
case IRQ_TYPE_LEVEL_HIGH:
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
break;
}
writel(val, sgpio->chip.regs + offset);
spin_unlock_irqrestore(&sgpio->lock, flags);
return 0;
}
static struct irq_chip sirfsoc_irq_chip = {
.name = "sirf-gpio-irq",
.irq_ack = sirfsoc_gpio_irq_ack,
.irq_mask = sirfsoc_gpio_irq_mask,
.irq_unmask = sirfsoc_gpio_irq_unmask,
.irq_set_type = sirfsoc_gpio_irq_type,
};
static void sirfsoc_gpio_handle_irq(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
struct sirfsoc_gpio_bank *bank;
u32 status, ctrl;
int idx = 0;
struct irq_chip *chip = irq_desc_get_chip(desc);
int i;
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
bank = &sgpio->sgpio_bank[i];
if (bank->parent_irq == irq)
break;
}
BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
chained_irq_enter(chip, desc);
status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
if (!status) {
printk(KERN_WARNING
"%s: gpio id %d status %#x no interrupt is flagged\n",
__func__, bank->id, status);
handle_bad_irq(desc);
return;
}
while (status) {
ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
/*
* Here we must check whether the corresponding GPIO's interrupt
* has been enabled, otherwise just skip it
*/
if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
pr_debug("%s: gpio id %d idx %d happens\n",
__func__, bank->id, idx);
generic_handle_irq(irq_find_mapping(gc->irq.domain, idx +
bank->id * SIRFSOC_GPIO_BANK_SIZE));
}
idx++;
status = status >> 1;
}
chained_irq_exit(chip, desc);
}
static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
unsigned ctrl_offset)
{
u32 val;
val = readl(sgpio->chip.regs + ctrl_offset);
val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
writel(val, sgpio->chip.regs + ctrl_offset);
}
static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
unsigned long flags;
if (pinctrl_gpio_request(chip->base + offset))
return -ENODEV;
spin_lock_irqsave(&bank->lock, flags);
/*
* default status:
* set direction as input and mask irq
*/
sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
__sirfsoc_gpio_irq_mask(sgpio, bank, offset);
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
{
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
__sirfsoc_gpio_irq_mask(sgpio, bank, offset);
sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
spin_unlock_irqrestore(&bank->lock, flags);
pinctrl_gpio_free(chip->base + offset);
}
static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
int idx = sirfsoc_gpio_to_bankoff(gpio);
unsigned long flags;
unsigned offset;
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
spin_lock_irqsave(&bank->lock, flags);
sirfsoc_gpio_set_input(sgpio, offset);
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
struct sirfsoc_gpio_bank *bank,
unsigned offset,
int value)
{
u32 out_ctrl;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
out_ctrl = readl(sgpio->chip.regs + offset);
if (value)
out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
else
out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
writel(out_ctrl, sgpio->chip.regs + offset);
spin_unlock_irqrestore(&bank->lock, flags);
}
static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
int idx = sirfsoc_gpio_to_bankoff(gpio);
u32 offset;
unsigned long flags;
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
spin_lock_irqsave(&sgpio->lock, flags);
sirfsoc_gpio_set_output(sgpio, bank, offset, value);
spin_unlock_irqrestore(&sgpio->lock, flags);
return 0;
}
static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
{
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
u32 val;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
spin_unlock_irqrestore(&bank->lock, flags);
return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
}
static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
int value)
{
struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
u32 ctrl;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
if (value)
ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
else
ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
spin_unlock_irqrestore(&bank->lock, flags);
}
static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
const u32 *pullups)
{
int i, n;
const unsigned long *p = (const unsigned long *)pullups;
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
for_each_set_bit(n, p + i, BITS_PER_LONG) {
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
u32 val = readl(sgpio->chip.regs + offset);
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
writel(val, sgpio->chip.regs + offset);
}
}
}
static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
const u32 *pulldowns)
{
int i, n;
const unsigned long *p = (const unsigned long *)pulldowns;
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
for_each_set_bit(n, p + i, BITS_PER_LONG) {
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
u32 val = readl(sgpio->chip.regs + offset);
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
writel(val, sgpio->chip.regs + offset);
}
}
}
static int sirfsoc_gpio_probe(struct device_node *np)
{
int i, err = 0;
struct sirfsoc_gpio_chip *sgpio;
struct sirfsoc_gpio_bank *bank;
void __iomem *regs;
struct platform_device *pdev;
struct gpio_irq_chip *girq;
u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
pdev = of_find_device_by_node(np);
if (!pdev)
return -ENODEV;
sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
if (!sgpio) {
err = -ENOMEM;
goto out_put_device;
}
spin_lock_init(&sgpio->lock);
regs = of_iomap(np, 0);
if (!regs) {
err = -ENOMEM;
goto out_put_device;
}
sgpio->chip.gc.request = sirfsoc_gpio_request;
sgpio->chip.gc.free = sirfsoc_gpio_free;
sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
sgpio->chip.gc.get = sirfsoc_gpio_get_value;
sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
sgpio->chip.gc.set = sirfsoc_gpio_set_value;
sgpio->chip.gc.base = 0;
sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
sgpio->chip.gc.label = kasprintf(GFP_KERNEL, "%pOF", np);
sgpio->chip.gc.of_node = np;
sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
sgpio->chip.gc.of_gpio_n_cells = 2;
sgpio->chip.gc.parent = &pdev->dev;
sgpio->chip.regs = regs;
girq = &sgpio->chip.gc.irq;
girq->chip = &sirfsoc_irq_chip;
girq->parent_handler = sirfsoc_gpio_handle_irq;
girq->num_parents = SIRFSOC_GPIO_NO_OF_BANKS;
girq->parents = devm_kcalloc(&pdev->dev, SIRFSOC_GPIO_NO_OF_BANKS,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents) {
err = -ENOMEM;
goto out_put_device;
}
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
bank = &sgpio->sgpio_bank[i];
spin_lock_init(&bank->lock);
bank->parent_irq = platform_get_irq(pdev, i);
if (bank->parent_irq < 0) {
err = bank->parent_irq;
goto out;
}
girq->parents[i] = bank->parent_irq;
}
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
err = gpiochip_add_data(&sgpio->chip.gc, sgpio);
if (err) {
dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n",
np, err);
goto out;
}
err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
if (err) {
dev_err(&pdev->dev,
"could not add gpiochip pin range\n");
goto out_no_range;
}
if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
SIRFSOC_GPIO_NO_OF_BANKS))
sirfsoc_gpio_set_pullup(sgpio, pullups);
if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
SIRFSOC_GPIO_NO_OF_BANKS))
sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
return 0;
out_no_range:
gpiochip_remove(&sgpio->chip.gc);
out:
iounmap(regs);
out_put_device:
put_device(&pdev->dev);
return err;
}
static int __init sirfsoc_gpio_init(void)
{
struct device_node *np;
np = of_find_matching_node(NULL, pinmux_ids);
if (!np)
return -ENODEV;
return sirfsoc_gpio_probe(np);
}
subsys_initcall(sirfsoc_gpio_init);
drivers/pinctrl/sirf/pinctrl-sirf.h deleted 100644 → 0
View file @ 484c58d6
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* pinmux driver shared headfile for CSR SiRFsoc
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#ifndef __PINMUX_SIRF_H__
#define __PINMUX_SIRF_H__
#define SIRFSOC_NUM_PADS 622
#define SIRFSOC_RSC_USB_UART_SHARE 0
#define SIRFSOC_RSC_PIN_MUX 0x4
#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
#define SIRFSOC_GPIO_DSP_EN0 (0x80)
#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
#define SIRFSOC_GPIO_CTL_DSP_INT 0x400
#define SIRFSOC_GPIO_NO_OF_BANKS 5
#define SIRFSOC_GPIO_BANK_SIZE 32
#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
/**
* @dev: a pointer back to containing device
* @virtbase: the offset to the controller in virtual memory
*/
struct sirfsoc_pmx {
struct device *dev;
struct pinctrl_dev *pmx;
void __iomem *gpio_virtbase;
void __iomem *rsc_virtbase;
u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE];
u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS];
u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS];
u32 dspen_regs;
u32 rsc_regs[3];
};
/* SIRFSOC_GPIO_PAD_EN set */
struct sirfsoc_muxmask {
unsigned long group;
unsigned long mask;
};
struct sirfsoc_padmux {
unsigned long muxmask_counts;
const struct sirfsoc_muxmask *muxmask;
/* RSC_PIN_MUX set */
unsigned long ctrlreg;
unsigned long funcmask;
unsigned long funcval;
};
/**
* struct sirfsoc_pin_group - describes a SiRFprimaII pin group
* @name: the name of this specific pin group
* @pins: an array of discrete physical pins used in this group, taken
* from the driver-local pin enumeration space
* @num_pins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
*/
struct sirfsoc_pin_group {
const char *name;
const unsigned int *pins;
const unsigned num_pins;
};
#define SIRFSOC_PIN_GROUP(n, p) \
{ \
.name = n, \
.pins = p, \
.num_pins = ARRAY_SIZE(p), \
}
struct sirfsoc_pmx_func {
const char *name;
const char * const *groups;
const unsigned num_groups;
const struct sirfsoc_padmux *padmux;
};
#define SIRFSOC_PMX_FUNCTION(n, g, m) \
{ \
.name = n, \
.groups = g, \
.num_groups = ARRAY_SIZE(g), \
.padmux = &m, \
}
struct sirfsoc_pinctrl_data {
struct pinctrl_pin_desc *pads;
int pads_cnt;
struct sirfsoc_pin_group *grps;
int grps_cnt;
struct sirfsoc_pmx_func *funcs;
int funcs_cnt;
};
extern struct sirfsoc_pinctrl_data prima2_pinctrl_data;
extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data;
#endif
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