Commit c61c15e0 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "ARM64 DT updates are fairly small this time, only two new SoCs and a
  handful of new machines get added, all of them similar to other
  hardware we already support.

  New SoC:

   - HiSilicon Kirin960/Hi3660 and HiKey960 development board

   - NXP LS1012a with three reference boards:
        http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/qoriq-layerscape-arm-processors/qoriq-layerscape-1012a-low-power-communication-processor:LS1012A

  New development board:

   - Banana Pi M64, based on Allwinner A64:
        http://www.banana-pi.org/m64.html

   - SolidRun MACCHIATOBin based on Marvell Armada 8K:
        https://www.solid-run.com/marvell-armada-family/armada-8040-community-board/

   - Broadcom BCM958712DxXMC NorthStar2 reference board (another one)

  A lot of platforms improve support for existing machines by adding
  extra devices for which a binding and driver is availabe:

  Allwinner:
   - MMC, USB

  ARM Juno:
   - Coresight, STM

  Broadcom:
   - NS2 GICv2m irqchip and PCIe

  Marvell:
   - Armada 3700 SPI, I2C, ethernet switch

  Mediatek:
   - MT8173 thermal

  NXP i.MX:
   - LS1046A thermal

  Qualcomm:
   - coresight on MSM8916, HDMI, WCNSS, SCM

  Renesas:
   - r8a779[56] thermal, powerdomain, ethernet, sound, pwm, can, can fd

  Rockchip:
   - thermal, eDP, pinctrl enhancements

  Samsung:
   - TM2 touchkey, Exynos5433 HDMI and power management improvements

  UniPhier:
   - SD reset, eMMC controller

  ZTE:
   - oppv2 cpufreq"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (110 commits)
  arm64: dts: qcom: Add msm8916 CoreSight components
  arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon
  arm64: allwinner: add BananaPi-M64 support
  arm64: allwinner: a64: add UART1 pin nodes
  arm64: allwinner: pine64: add MMC support
  arm64: allwinner: a64: Increase the MMC max frequency
  arm64: allwinner: a64: Add MMC pinctrl nodes
  arm64: allwinner: a64: Add MMC nodes
  dt-bindings: clockgen: Add compatible string for LS1012A
  Documentation: DT: add LS1012A compatible for SCFG and DCFG
  Documentation: DT: Add entry for FSL LS1012A RDB, FRDM, QDS boards
  arm64: dts: marvell: add generic-ahci compatibles for CP110 ahci
  arm64: tegra: Use symbolic reset identifiers
  arm64: dts: r8a7796: Mark EthernetAVB device node disabled
  arm64: dts: r8a7795: Mark EthernetAVB device node disabled
  arm64: dts: r8a7795: tidyup audma definition order
  arm64: dts: r8a7796: Link ARM GIC to clock and clock domain
  arm64: dts: r8a7795: Link ARM GIC to clock and clock domain
  arm64: dts: r8a7796: Add R-Car Gen3 thermal support
  arm64: dts: r8a7795: Add R-Car Gen3 thermal support
  ...
parents 195849ea cbab3197
......@@ -158,6 +158,7 @@ nodes to be present and contain the properties described below.
"arm,cortex-a53"
"arm,cortex-a57"
"arm,cortex-a72"
"arm,cortex-a73"
"arm,cortex-m0"
"arm,cortex-m0+"
"arm,cortex-m1"
......
......@@ -108,7 +108,7 @@ status.
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-scfg",
The following <chip>s are known to be supported:
ls1021a, ls1043a, ls1046a, ls2080a.
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
- reg: should contain base address and length of SCFG memory-mapped registers
......@@ -126,7 +126,7 @@ core start address and release the secondary core from holdoff and startup.
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
ls1021a, ls1043a, ls1046a, ls2080a.
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
- reg : should contain base address and length of DCFG memory-mapped registers
......@@ -139,6 +139,22 @@ Example:
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
----------------------------------------------------------------
LS1012A SoC
Required root node properties:
- compatible = "fsl,ls1012a";
LS1012A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
LS1012A ARMv8 based FRDM Board
Required root node properties:
- compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
LS1012A ARMv8 based QDS Board
Required root node properties:
- compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
LS1043A SoC
Required root node properties:
- compatible = "fsl,ls1043a";
......
Hisilicon Platforms Device Tree Bindings
----------------------------------------------------
Hi3660 SoC
Required root node properties:
- compatible = "hisilicon,hi3660";
Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";
......
......@@ -75,7 +75,7 @@ Boards:
compatible = "renesas,rskrza1", "renesas,r7s72100"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795";
- Salvator-X
- Salvator-X (RTP0RC7796SIPB0011S)
compatible = "renesas,salvator-x", "renesas,r8a7796";
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
......
......@@ -31,6 +31,7 @@ Required properties:
* "fsl,t4240-clockgen"
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
* "fsl,ls1012a-clockgen"
* "fsl,ls1021a-clockgen"
* "fsl,ls1043a-clockgen"
* "fsl,ls1046a-clockgen"
......
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
always := $(dtb-y)
......
/*
* Copyright (c) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "BananaPi-M64";
compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c1_pins {
bias-pull-up;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
bus-width = <4>;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
non-removable;
status = "okay";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};
......@@ -44,6 +44,8 @@
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Pine64";
compatible = "pine64,pine64", "allwinner,sun50i-a64";
......@@ -55,11 +57,16 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
&ehci1 {
status = "okay";
};
......@@ -72,3 +79,33 @@ &i2c1 {
&i2c1_pins {
bias-pull-up;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
bus-width = <4>;
status = "okay";
};
&ohci1 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usb_otg {
dr_mode = "host";
status = "okay";
};
&usbphy {
status = "okay";
};
......@@ -42,8 +42,9 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
/ {
interrupt-parent = <&gic>;
......@@ -120,6 +121,105 @@ soc {
#size-cells = <1>;
ranges;
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <150000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@1c10000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <150000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@1c11000 {
compatible = "allwinner,sun50i-a64-emmc";
reg = <0x01c11000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <200000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@01c19400 {
compatible = "allwinner,sun50i-a64-usb-phy";
reg = <0x01c19400 0x14>,
<0x01c1b800 0x4>;
reg-names = "phy_ctrl",
"pmu1";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_BUS_EHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>,
<&ccu RST_BUS_EHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ohci1: usb@01c1b400 {
compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
reg = <0x01c1b400 0x100>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ccu: clock@01c20000 {
compatible = "allwinner,sun50i-a64-ccu";
reg = <0x01c20000 0x400>;
......@@ -146,10 +246,45 @@ i2c1_pins: i2c1_pins {
function = "i2c1";
};
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
bias-pull-up;
};
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
bias-pull-up;
};
mmc2_pins: mmc2-pins {
pins = "PC1", "PC5", "PC6", "PC8", "PC9",
"PC10","PC11", "PC12", "PC13",
"PC14", "PC15", "PC16";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
};
uart1_pins: uart1_pins {
pins = "PG6", "PG7";
function = "uart1";
};
uart1_rts_cts_pins: uart1_rts_cts_pins {
pins = "PG8", "PG9";
function = "uart1";
};
};
uart0: serial@1c28000 {
......
#include "juno-clocks.dtsi"
/ {
/*
* Devices shared by all Juno boards
*/
dma-ranges = <0 0 0 0 0x100 0>;
memtimer: timer@2a810000 {
compatible = "arm,armv7-timer-mem";
......@@ -48,6 +52,7 @@ smmu_etr: iommu@2b600000 {
#iommu-cells = <1>;
#global-interrupts = <1>;
dma-coherent;
power-domains = <&scpi_devpd 0>;
status = "disabled";
};
......@@ -83,7 +88,7 @@ timer {
* The actual size is just 4K though 64K is reserved. Access to the
* unmapped reserved region results in a DECERR response.
*/
etf@20010000 {
etf@20010000 { /* etf0 */
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x20010000 0 0x1000>;
......@@ -97,7 +102,7 @@ ports {
/* input port */
port@0 {
reg = <0>;
etf_in_port: endpoint {
etf0_in_port: endpoint {
slave-mode;
remote-endpoint = <&main_funnel_out_port>;
};
......@@ -106,8 +111,7 @@ etf_in_port: endpoint {
/* output port */
port@1 {
reg = <0>;
etf_out_port: endpoint {
remote-endpoint = <&replicator_in_port0>;
etf0_out_port: endpoint {
};
};
};
......@@ -128,7 +132,8 @@ tpiu_in_port: endpoint {
};
};
main-funnel@20040000 {
/* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
main_funnel: funnel@20040000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x20040000 0 0x1000>;
......@@ -139,13 +144,15 @@ ports {
#address-cells = <1>;
#size-cells = <0>;
/* output port */
port@0 {
reg = <0>;
main_funnel_out_port: endpoint {
remote-endpoint = <&etf_in_port>;
remote-endpoint = <&etf0_in_port>;
};
};
/* input ports */
port@1 {
reg = <0>;
main_funnel_in_port0: endpoint {
......@@ -161,7 +168,6 @@ main_funnel_in_port1: endpoint {
remote-endpoint = <&cluster1_funnel_out_port>;
};
};
};
};
......@@ -181,6 +187,21 @@ etr_in_port: endpoint {
};
};
stm@20100000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x20100000 0 0x1000>,
<0 0x28000000 0 0x1000000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
stm_out_port: endpoint {
};
};
};
etm0: etm@22040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22040000 0 0x1000>;
......@@ -195,7 +216,7 @@ cluster0_etm0_out_port: endpoint {
};
};
cluster0-funnel@220c0000 {
funnel@220c0000 { /* cluster0 funnel */
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x220c0000 0 0x1000>;
......@@ -259,7 +280,7 @@ cluster1_etm0_out_port: endpoint {
};
};
cluster1-funnel@230c0000 {
funnel@230c0000 { /* cluster1 funnel */
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x230c0000 0 0x1000>;
......@@ -382,7 +403,6 @@ port@2 {
reg = <0>;
replicator_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etf_out_port>;
};
};
};
......@@ -507,8 +527,6 @@ gpu1_thermal_zone: gpu1 {
};
};
/include/ "juno-clocks.dtsi"
smmu_dma: iommu@7fb00000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x7fb00000 0x0 0x10000>;
......@@ -719,3 +737,4 @@ site2: tlx@60000000 {
interrupt-map-mask = <0 0>;
interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
};
};
......@@ -6,7 +6,7 @@
* This file is licensed under a dual GPLv2 or BSD license.
*
*/
/ {
/* SoC fixed clocks */
soc_uartclk: refclk7273800hz {
compatible = "fixed-clock";
......@@ -42,3 +42,4 @@ soc_faxiclk: refclk400mhz {
clock-frequency = <400000000>;
clock-output-names = "faxi_clk";
};
};
/ {
funnel@20130000 { /* cssys1 */
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x20130000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* output port */
port@0 {
reg = <0>;
csys1_funnel_out_port: endpoint {
remote-endpoint = <&etf1_in_port>;
};
};
/* input port */
port@1 {
reg = <0>;
csys1_funnel_in_port0: endpoint {
slave-mode;
};
};
};
};
etf@20140000 { /* etf1 */
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x20140000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* input port */
port@0 {
reg = <0>;
etf1_in_port: endpoint {
slave-mode;
remote-endpoint = <&csys1_funnel_out_port>;
};
};
/* output port */
port@1 {
reg = <0>;
etf1_out_port: endpoint {
remote-endpoint = <&csys2_funnel_in_port1>;
};
};
};
};
funnel@20150000 { /* cssys2 */
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x20150000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* output port */
port@0 {
reg = <0>;
csys2_funnel_out_port: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
};
/* input ports */
port@1 {
reg = <0>;
csys2_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etf0_out_port>;
};
};
port@2 {
reg = <1>;
csys2_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&etf1_out_port>;
};
};
};
};
};
......@@ -131,13 +131,6 @@ ethernet@2,00000000 {
vddvario-supply = <&mb_fixed_3v3>;
};
usb@5,00000000 {
compatible = "nxp,usb-isp1763";
reg = <5 0x00000000 0x20000>;
bus-width = <16>;
interrupts = <4>;
};
iofpga@3,00000000 {
compatible = "simple-bus";
#address-cells = <1>;
......
......@@ -9,6 +9,8 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "juno-base.dtsi"
#include "juno-cs-r1r2.dtsi"
/ {
model = "ARM Juno development board (r1)";
......@@ -176,8 +178,6 @@ pmu_a53 {
<&A53_2>,
<&A53_3>;
};
#include "juno-base.dtsi"
};
&memtimer {
......@@ -227,3 +227,15 @@ &gpu0_thermal_zone {
&gpu1_thermal_zone {
status = "okay";
};
&etf0_out_port {
remote-endpoint = <&csys2_funnel_in_port0>;
};
&replicator_in_port0 {
remote-endpoint = <&csys2_funnel_out_port>;
};
&stm_out_port {
remote-endpoint = <&csys1_funnel_in_port0>;
};
......@@ -9,6 +9,8 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "juno-base.dtsi"
#include "juno-cs-r1r2.dtsi"
/ {
model = "ARM Juno development board (r2)";
......@@ -176,8 +178,6 @@ pmu_a53 {
<&A53_2>,
<&A53_3>;
};
#include "juno-base.dtsi"
};
&memtimer {
......@@ -227,3 +227,15 @@ &gpu0_thermal_zone {
&gpu1_thermal_zone {
status = "okay";
};
&etf0_out_port {
remote-endpoint = <&csys2_funnel_in_port0>;
};
&replicator_in_port0 {
remote-endpoint = <&csys2_funnel_out_port>;
};
&stm_out_port {
remote-endpoint = <&csys1_funnel_in_port0>;
};
......@@ -9,6 +9,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "juno-base.dtsi"
/ {
model = "ARM Juno development board (r0)";
......@@ -176,8 +177,6 @@ pmu_a53 {
<&A53_2>,
<&A53_3>;
};
#include "juno-base.dtsi"
};
&etm0 {
......@@ -203,3 +202,27 @@ &etm4 {
&etm5 {
cpu = <&A53_3>;
};
&etf0_out_port {
remote-endpoint = <&replicator_in_port0>;
};
&replicator_in_port0 {
remote-endpoint = <&etf0_out_port>;
};
&stm_out_port {
remote-endpoint = <&main_funnel_in_port2>;
};
&main_funnel {
ports {
port@3 {
reg = <2>;
main_funnel_in_port2: endpoint {
slave-mode;
remote-endpoint = <&stm_out_port>;
};
};
};
};
dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb
dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb
always := $(dtb-y)
......
......@@ -76,6 +76,10 @@ &pcie4 {
status = "ok";
};
&pcie8 {
status = "ok";
};
&i2c0 {
status = "ok";
};
......
/*
* BSD LICENSE
*
* Copyright(c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "ns2.dtsi"
/ {
model = "Broadcom NS2 XMC";
compatible = "brcm,ns2-xmc", "brcm,ns2";
aliases {
serial0 = &uart3;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs = "earlycon=uart8250,mmio32,0x66130000";
};
memory {
device_type = "memory";
reg = <0x000000000 0x80000000 0x00000001 0x00000000>;
};
};
&enet {
status = "ok";
};
&i2c0 {
status = "ok";
};
&i2c1 {
status = "ok";
};
&mdio_mux_iproc {
mdio@10 {
gphy0: eth-phy@10 {
reg = <0x10>;
};
};
};
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <16>;
brcm,nand-oob-sector-size = <16>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "nboot";
reg = <0x00000000 0x00280000>; /* 2.5MB */
read-only;
};
partition@280000 {
label = "nenv";
reg = <0x00280000 0x00040000>; /* 0.25MB */
read-only;
};
partition@2c0000 {
label = "ndtb";
reg = <0x002c0000 0x00040000>; /* 0.25MB */
read-only;
};
partition@300000 {
label = "nsystem";
reg = <0x00300000 0x03d00000>; /* 61MB */
read-only;
};
partition@4000000 {
label = "nrootfs";
reg = <0x04000000 0x06400000>; /* 100MB */
};
partition@0a400000{
label = "ncustfs";
reg = <0x0a400000 0x35c00000>; /* 860MB */
};
};
};
&pci_phy0 {
status = "ok";
};
&pcie0 {
status = "ok";
};
&pcie8 {
status = "ok";
};
&sata_phy0 {
status = "ok";
};
&sata_phy1 {
status = "ok";
};
&sata {
status = "ok";
};
&qspi {
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
spi-max-frequency = <62500000>;
m25p,default-addr-width = <3>;
reg = <0x0 0x0>;
partition@0 {
label = "bl0";
reg = <0x00000000 0x00080000>; /* 512KB */
};
partition@80000 {
label = "fip";
reg = <0x00080000 0x00150000>; /* 1344KB */
};
partition@1e0000 {
label = "env";
reg = <0x001e0000 0x00010000>;/* 64KB */
};
partition@1f0000 {
label = "dtb";
reg = <0x001f0000 0x00010000>; /* 64KB */
};
partition@200000 {
label = "kernel";
reg = <0x00200000 0x00e00000>; /* 14MB */
};
partition@1000000 {
label = "rootfs";
reg = <0x01000000 0x01000000>; /* 16MB */
};
};
};
&uart3 {
status = "ok";
};
......@@ -30,6 +30,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/memreserve/ 0x81000000 0x00200000;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/bcm-ns2.h>
......@@ -115,7 +117,7 @@ pcie0: pcie@20020000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_NONE>;
linux,pci-domain = <0>;
......@@ -136,18 +138,7 @@ pcie0: pcie@20020000 {
phys = <&pci_phy0>;
phy-names = "pcie-phy";
msi-parent = <&msi0>;
msi0: msi@20020000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
<GIC_SPI 278 IRQ_TYPE_NONE>,
<GIC_SPI 279 IRQ_TYPE_NONE>,
<GIC_SPI 280 IRQ_TYPE_NONE>;
brcm,num-eq-region = <1>;
brcm,num-msi-msg-region = <1>;
};
msi-parent = <&v2m0>;
};
pcie4: pcie@50020000 {
......@@ -156,7 +147,7 @@ pcie4: pcie@50020000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_NONE>;
linux,pci-domain = <4>;
......@@ -177,16 +168,24 @@ pcie4: pcie@50020000 {
phys = <&pci_phy1>;
phy-names = "pcie-phy";
msi-parent = <&msi4>;
msi4: msi@50020000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
<GIC_SPI 302 IRQ_TYPE_NONE>,
<GIC_SPI 303 IRQ_TYPE_NONE>,
<GIC_SPI 304 IRQ_TYPE_NONE>;
msi-parent = <&v2m0>;
};
pcie8: pcie@60c00000 {
compatible = "brcm,iproc-pcie-paxc";
reg = <0 0x60c00000 0 0x1000>;
linux,pci-domain = <8>;
bus-range = <0x0 0x1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>;
status = "disabled";
msi-parent = <&v2m0>;
};
soc: soc {
......@@ -331,6 +330,82 @@ gic: interrupt-controller@65210000 {
<0x65260000 0x1000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_HIGH)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x652e0000 0x80000>;
v2m0: v2m@00000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x00000 0x1000>;
arm,msi-base-spi = <72>;
arm,msi-num-spis = <16>;
};
v2m1: v2m@10000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x10000 0x1000>;
arm,msi-base-spi = <88>;
arm,msi-num-spis = <16>;
};
v2m2: v2m@20000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x20000 0x1000>;
arm,msi-base-spi = <104>;
arm,msi-num-spis = <16>;
};
v2m3: v2m@30000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x30000 0x1000>;
arm,msi-base-spi = <120>;
arm,msi-num-spis = <16>;
};
v2m4: v2m@40000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x40000 0x1000>;
arm,msi-base-spi = <136>;
arm,msi-num-spis = <16>;
};
v2m5: v2m@50000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x50000 0x1000>;
arm,msi-base-spi = <152>;
arm,msi-num-spis = <16>;
};
v2m6: v2m@60000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x60000 0x1000>;
arm,msi-base-spi = <168>;
arm,msi-num-spis = <16>;
};
v2m7: v2m@70000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x70000 0x1000>;
arm,msi-base-spi = <184>;
arm,msi-num-spis = <16>;
};
};
cci@65590000 {
......
/*
* Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* Chanwoo Choi <cw00.choi@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&soc {
bus_g2d_400: bus0 {
compatible = "samsung,exynos-bus";
clocks = <&cmu_top CLK_ACLK_G2D_400>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_400_opp_table>;
status = "disabled";
};
bus_g2d_266: bus1 {
compatible = "samsung,exynos-bus";
clocks = <&cmu_top CLK_ACLK_G2D_266>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_266_opp_table>;
status = "disabled";
};
bus_gscl: bus2 {
compatible = "samsung,exynos-bus";
clocks = <&cmu_top CLK_ACLK_GSCL_333>;
clock-names = "bus";
operating-points-v2 = <&bus_gscl_opp_table>;
status = "disabled";
};
bus_hevc: bus3 {
compatible = "samsung,exynos-bus";
clocks = <&cmu_top CLK_ACLK_HEVC_400>;
clock-names = "bus";
operating-points-v2 = <&bus_hevc_opp_table>;
status = "disabled";
};
bus_jpeg: bus4 {
compatible = "samsung,exynos-bus";
clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_400_opp_table>;
status = "disabled";
};
bus_mfc: bus5 {
compatible = "samsung,exynos-bus";
clocks = <&cmu_top CLK_ACLK_MFC_400>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_400_opp_table>;
status = "disabled";
};
bus_mscl: bus6 {
compatible = "samsung,exynos-bus";
clocks = <&cmu_top CLK_ACLK_MSCL_400>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_400_opp_table>;
status = "disabled";
};
bus_noc0: bus7 {
compatible = "samsung,exynos-bus";
clocks = <&cmu_top CLK_ACLK_BUS0_400>;
clock-names = "bus";
operating-points-v2 = <&bus_hevc_opp_table>;
status = "disabled";
};
bus_noc1: bus8 {
compatible = "samsung,exynos-bus";
clocks = <&cmu_top CLK_ACLK_BUS1_400>;
clock-names = "bus";
operating-points-v2 = <&bus_hevc_opp_table>;
status = "disabled";
};
bus_noc2: bus9 {
compatible = "samsung,exynos-bus";
clocks = <&cmu_mif CLK_ACLK_BUS2_400>;
clock-names = "bus";
operating-points-v2 = <&bus_noc2_opp_table>;
status = "disabled";
};
bus_g2d_400_opp_table: opp_table2 {
compatible = "operating-points-v2";
opp-shared;
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1075000>;
};
opp@267000000 {
opp-hz = /bits/ 64 <267000000>;
opp-microvolt = <1000000>;
};
opp@200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <975000>;
};
opp@160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <962500>;
};
opp@134000000 {
opp-hz = /bits/ 64 <134000000>;
opp-microvolt = <950000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <937500>;
};
};
bus_g2d_266_opp_table: opp_table3 {
compatible = "operating-points-v2";
opp@267000000 {
opp-hz = /bits/ 64 <267000000>;
};
opp@200000000 {
opp-hz = /bits/ 64 <200000000>;
};
opp@160000000 {
opp-hz = /bits/ 64 <160000000>;
};
opp@134000000 {
opp-hz = /bits/ 64 <134000000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
};
};
bus_gscl_opp_table: opp_table4 {
compatible = "operating-points-v2";
opp@333000000 {
opp-hz = /bits/ 64 <333000000>;
};
opp@222000000 {
opp-hz = /bits/ 64 <222000000>;
};
opp@166500000 {
opp-hz = /bits/ 64 <166500000>;
};
};
bus_hevc_opp_table: opp_table5 {
compatible = "operating-points-v2";
opp-shared;
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
};
opp@267000000 {
opp-hz = /bits/ 64 <267000000>;
};
opp@200000000 {
opp-hz = /bits/ 64 <200000000>;
};
opp@160000000 {
opp-hz = /bits/ 64 <160000000>;
};
opp@134000000 {
opp-hz = /bits/ 64 <134000000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
};
};
bus_noc2_opp_table: opp_table6 {
compatible = "operating-points-v2";
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
};
opp@200000000 {
opp-hz = /bits/ 64 <200000000>;
};
opp@134000000 {
opp-hz = /bits/ 64 <134000000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
};
};
};
This diff is collapsed.
......@@ -11,23 +11,13 @@
* published by the Free Software Foundation.
*/
#include "exynos5433-tm2.dts"
#include "exynos5433-tm2-common.dtsi"
/ {
model = "Samsung TM2E board";
compatible = "samsung,tm2e", "samsung,exynos5433";
};
&ldo23_reg {
regulator-name = "CAM_SEN_CORE_1.025V_AP";
regulator-max-microvolt = <1050000>;
};
&ldo25_reg {
regulator-name = "UNUSED_LDO25";
regulator-always-off;
};
&ldo31_reg {
regulator-name = "TSP_VDD_1.8V_AP";
regulator-min-microvolt = <1800000>;
......
......@@ -299,7 +299,7 @@ cmu_peric: clock-controller@14c80000 {
#clock-cells = <1>;
};
cmu_peris: clock-controller@0x10040000 {
cmu_peris: clock-controller@10040000 {
compatible = "samsung,exynos5433-cmu-peris";
reg = <0x10040000 0x1000>;
#clock-cells = <1>;
......@@ -599,6 +599,30 @@ mct@101c0000 {
clock-names = "fin_pll", "mct";
};
ppmu_d0_cpu: ppmu@10480000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x10480000 0x2000>;
status = "disabled";
};
ppmu_d0_general: ppmu@10490000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x10490000 0x2000>;
status = "disabled";
};
ppmu_d1_cpu: ppmu@104b0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104b0000 0x2000>;
status = "disabled";
};
ppmu_d1_general: ppmu@104c0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104c0000 0x2000>;
status = "disabled";
};
pinctrl_alive: pinctrl@10580000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
......@@ -682,7 +706,7 @@ gic: interrupt-controller@11001000 {
interrupts = <GIC_PPI 9 0xf04>;
};
mipi_phy: video-phy@105c0710 {
mipi_phy: video-phy {
compatible = "samsung,exynos5433-mipi-video-phy";
#phy-cells = <1>;
samsung,pmu-syscon = <&pmu_system_controller>;
......@@ -727,6 +751,29 @@ decon_to_mic: endpoint {
};
};
decon_tv: decon@13880000 {
compatible = "samsung,exynos5433-decon-tv";
reg = <0x13880000 0x20b8>;
clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
<&cmu_disp CLK_ACLK_DECON_TV>,
<&cmu_disp CLK_ACLK_SMMU_TV0X>,
<&cmu_disp CLK_ACLK_XIU_TV0X>,
<&cmu_disp CLK_PCLK_SMMU_TV0X>,
<&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
<&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
"aclk_xiu_decon0x", "pclk_smmu_decon0x",
"sclk_decon_vclk", "sclk_decon_eclk";
samsung,disp-sysreg = <&syscon_disp>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
iommu-names = "m0", "m1";
};
dsi: dsi@13900000 {
compatible = "samsung,exynos5433-mipi-dsi";
reg = <0x13900000 0xC0>;
......@@ -790,6 +837,35 @@ mic_to_dsi: endpoint {
};
};
hdmi: hdmi@13970000 {
compatible = "samsung,exynos5433-hdmi";
reg = <0x13970000 0x70000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_disp CLK_PCLK_HDMI>,
<&cmu_disp CLK_PCLK_HDMIPHY>,
<&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
<&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
<&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
<&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
<&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
<&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
<&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
clock-names = "hdmi_pclk", "hdmi_i_pclk",
"i_tmds_clk", "i_pixel_clk",
"tmds_clko", "tmds_clko_user",
"pixel_clko", "pixel_clko_user",
"oscclk", "i_spdif_clk";
phy = <&hdmiphy>;
ddc = <&hsi2c_11>;
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,sysreg-phandle = <&syscon_disp>;
status = "disabled";
};
hdmiphy: hdmiphy@13af0000 {
reg = <0x13af0000 0x80>;
};
syscon_disp: syscon@13b80000 {
compatible = "syscon";
reg = <0x13b80000 0x1010>;
......@@ -868,7 +944,7 @@ mfc: codec@152E0000 {
iommu-names = "left", "right";
};
sysmmu_decon0x: sysmmu@0x13a00000 {
sysmmu_decon0x: sysmmu@13a00000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13a00000 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
......@@ -878,7 +954,7 @@ sysmmu_decon0x: sysmmu@0x13a00000 {
#iommu-cells = <0>;
};
sysmmu_decon1x: sysmmu@0x13a10000 {
sysmmu_decon1x: sysmmu@13a10000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13a10000 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
......@@ -888,7 +964,27 @@ sysmmu_decon1x: sysmmu@0x13a10000 {
#iommu-cells = <0>;
};
sysmmu_gscl0: sysmmu@0x13C80000 {
sysmmu_tv0x: sysmmu@13a20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13a20000 0x1000>;
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk";
clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
<&cmu_disp CLK_ACLK_SMMU_TV0X>;
#iommu-cells = <0>;
};
sysmmu_tv1x: sysmmu@13a30000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13a30000 0x1000>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk";
clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
<&cmu_disp CLK_ACLK_SMMU_TV1X>;
#iommu-cells = <0>;
};
sysmmu_gscl0: sysmmu@13c80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13C80000 0x1000>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
......@@ -898,7 +994,7 @@ sysmmu_gscl0: sysmmu@0x13C80000 {
#iommu-cells = <0>;
};
sysmmu_gscl1: sysmmu@0x13C90000 {
sysmmu_gscl1: sysmmu@13c90000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13C90000 0x1000>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
......@@ -908,7 +1004,7 @@ sysmmu_gscl1: sysmmu@0x13C90000 {
#iommu-cells = <0>;
};
sysmmu_gscl2: sysmmu@0x13CA0000 {
sysmmu_gscl2: sysmmu@13ca0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13CA0000 0x1000>;
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
......@@ -918,7 +1014,7 @@ sysmmu_gscl2: sysmmu@0x13CA0000 {
#iommu-cells = <0>;
};
sysmmu_jpeg: sysmmu@0x15060000 {
sysmmu_jpeg: sysmmu@15060000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x15060000 0x1000>;
interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
......@@ -928,7 +1024,7 @@ sysmmu_jpeg: sysmmu@0x15060000 {
#iommu-cells = <0>;
};
sysmmu_mfc_0: sysmmu@0x15200000 {
sysmmu_mfc_0: sysmmu@15200000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x15200000 0x1000>;
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
......@@ -938,7 +1034,7 @@ sysmmu_mfc_0: sysmmu@0x15200000 {
#iommu-cells = <0>;
};
sysmmu_mfc_1: sysmmu@0x15210000 {
sysmmu_mfc_1: sysmmu@15210000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x15210000 0x1000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1261,7 +1357,7 @@ hsi2c_11: hsi2c@14df0000 {
status = "disabled";
};
usbdrd30: usb@15400000 {
usbdrd30: usbdrd {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
<&cmu_fsys CLK_SCLK_USBDRD30>;
......@@ -1308,7 +1404,7 @@ usbhost30_phy: phy@15580000 {
status = "disabled";
};
usbhost30: usb@15a00000 {
usbhost30: usbhost {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
<&cmu_fsys CLK_SCLK_USBHOST30>;
......@@ -1398,6 +1494,8 @@ pdma1: pdma@15600000 {
audio-subsystem@11400000 {
compatible = "samsung,exynos5433-lpass";
reg = <0x11400000 0x100>, <0x11500000 0x08>;
clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
clock-names = "sfr0_ctrl";
samsung,pmu-syscon = <&pmu_system_controller>;
#address-cells = <1>;
#size-cells = <1>;
......@@ -1458,5 +1556,6 @@ timer: timer {
};
};
#include "exynos5433-bus.dtsi"
#include "exynos5433-pinctrl.dtsi"
#include "exynos5433-tmu.dtsi"
......@@ -497,49 +497,49 @@ sd0_clk: sd0-clk {
samsung,pins = "gpr0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
samsung,pin-drv = <4>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpr0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
samsung,pin-drv = <4>;
};
sd0_ds: sd0-ds {
samsung,pins = "gpr0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <3>;
samsung,pin-drv = <4>;
};
sd0_qrdy: sd0-qrdy {
samsung,pins = "gpr0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <3>;
samsung,pin-drv = <4>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpr1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
samsung,pin-drv = <4>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
samsung,pin-drv = <4>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
samsung,pin-drv = <4>;
};
sd1_clk: sd1-clk {
......
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
......
/*
* Device Tree file for Freescale LS1012A Freedom Board.
*
* Copyright 2016, Freescale Semiconductor
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "fsl-ls1012a.dtsi"
/ {
model = "LS1012A Freedom Board";
compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker Ext",
"Line", "Line In Jack";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"Speaker Ext", "LINE_OUT";
simple-audio-card,cpu {
sound-dai = <&sai2>;
frame-master;
bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&codec>;
frame-master;
bitclock-master;
system-clock-frequency = <25000000>;
};
};
};
&duart0 {
status = "okay";
};
&i2c0 {
status = "okay";
codec: sgtl5000@a {
#sound-dai-cells = <0>;
compatible = "fsl,sgtl5000";
reg = <0xa>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_1p8v>;
clocks = <&sys_mclk>;
};
};
&sai2 {
status = "okay";
};
/*
* Device Tree file for Freescale LS1012A QDS Board.
*
* Copyright 2016, Freescale Semiconductor
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "fsl-ls1012a.dtsi"
/ {
model = "LS1012A QDS Board";
compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker Ext",
"Line", "Line In Jack";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"Speaker Ext", "LINE_OUT";
simple-audio-card,cpu {
sound-dai = <&sai2>;
frame-master;
bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&codec>;
frame-master;
bitclock-master;
system-clock-frequency = <24576000>;
};
};
};
&duart0 {
status = "okay";
};
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
codec: sgtl5000@a {
#sound-dai-cells = <0>;
compatible = "fsl,sgtl5000";
reg = <0xa>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&sys_mclk>;
};
};
};
};
&sai2 {
status = "okay";
};
/*
* Device Tree file for Freescale LS1012A RDB Board.
*
* Copyright 2016, Freescale Semiconductor
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "fsl-ls1012a.dtsi"
/ {
model = "LS1012A RDB Board";
compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
};
&duart0 {
status = "okay";
};
&i2c0 {
status = "okay";
};
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......@@ -45,6 +45,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1046a";
......@@ -67,6 +68,7 @@ cpu0: cpu@0 {
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
......@@ -279,6 +281,84 @@ clockgen: clocking@1ee1000 {
clocks = <&sysclk>;
};
tmu: tmu@1f00000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f00000 0x0 0x10000>;
interrupts = <0 33 0x4>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
fsl,tmu-calibration =
/* Calibration data group 1 */
<0x00000000 0x00000026
0x00000001 0x0000002d
0x00000002 0x00000032
0x00000003 0x00000039
0x00000004 0x0000003f
0x00000005 0x00000046
0x00000006 0x0000004d
0x00000007 0x00000054
0x00000008 0x0000005a
0x00000009 0x00000061
0x0000000a 0x0000006a
0x0000000b 0x00000071
/* Calibration data group 2 */
0x00010000 0x00000025
0x00010001 0x0000002c
0x00010002 0x00000035
0x00010003 0x0000003d
0x00010004 0x00000045
0x00010005 0x0000004e
0x00010006 0x00000057
0x00010007 0x00000061
0x00010008 0x0000006b
0x00010009 0x00000076
/* Calibration data group 3 */
0x00020000 0x00000029
0x00020001 0x00000033
0x00020002 0x0000003d
0x00020003 0x00000049
0x00020004 0x00000056
0x00020005 0x00000061
0x00020006 0x0000006d
/* Calibration data group 4 */
0x00030000 0x00000021
0x00030001 0x0000002a
0x00030002 0x0000003c
0x00030003 0x0000004e>;
big-endian;
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
dspi: dspi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
......
......@@ -102,7 +102,6 @@ pca9547@75 {
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
......
dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
......
/*
* dts file for Hisilicon HiKey960 Development Board
*
* Copyright (C) 2016, Hisilicon Ltd.
*
*/
/dts-v1/;
#include "hi3660.dtsi"
/ {
model = "HiKey960";
compatible = "hisilicon,hi3660";
aliases {
serial5 = &uart5; /* console UART */
};
chosen {
stdout-path = "serial5:115200n8";
};
memory@0 {
device_type = "memory";
/* rewrite this at bootloader */
reg = <0x0 0x0 0x0 0x0>;
};
};
&uart5 {
status = "okay";
};
This diff is collapsed.
......@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
......
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......@@ -74,13 +74,14 @@ cpm_syscon0: system-controller@440000 {
"cpm-gop-dp", "none", "cpm-pcie_x10",
"cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
"cpm-sata", "cpm-sata-usb", "cpm-main",
"cpm-sd-mmc", "none", "none",
"cpm-sd-mmc-gop", "none", "none",
"cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
};
cpm_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci";
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 15>;
......
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......@@ -277,6 +277,8 @@ &rcar_sound {
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
......
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