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Commit c7a72805 authored by Balsam CHIHI's avatar Balsam CHIHI Committed by AngeloGioacchino Del Regno
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arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones 

Add thermal nodes and thermal zones for the mt8192.

The mt8192 SoC has several hotspots around the CPUs.
Specify the targeted temperature threshold to apply the mitigation
and define the associated cooling devices.
Signed-off-by: default avatarBalsam CHIHI <bchihi@baylibre.com>
Reviewed-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
[bero@baylibre.com: cosmetic changes, reduce lvts_ap size]
Signed-off-by: default avatarBernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: default avatarAlexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent 89ce5a09
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arch/arm64/boot/dts/mediatek/mt8192.dtsi
View file @ c7a72805
......@@ -14,6 +14,8 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
#include <dt-bindings/reset/mt8192-resets.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
/ {
compatible = "mediatek,mt8192";
......@@ -72,6 +74,7 @@ cpu0: cpu@0 {
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <427>;
#cooling-cells = <2>;
};
cpu1: cpu@100 {
......@@ -90,6 +93,7 @@ cpu1: cpu@100 {
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <427>;
#cooling-cells = <2>;
};
cpu2: cpu@200 {
......@@ -108,6 +112,7 @@ cpu2: cpu@200 {
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <427>;
#cooling-cells = <2>;
};
cpu3: cpu@300 {
......@@ -126,6 +131,7 @@ cpu3: cpu@300 {
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <427>;
#cooling-cells = <2>;
};
cpu4: cpu@400 {
......@@ -144,6 +150,7 @@ cpu4: cpu@400 {
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
cpu5: cpu@500 {
......@@ -162,6 +169,7 @@ cpu5: cpu@500 {
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
cpu6: cpu@600 {
......@@ -180,6 +188,7 @@ cpu6: cpu@600 {
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
cpu7: cpu@700 {
......@@ -198,6 +207,7 @@ cpu7: cpu@700 {
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
cpu-map {
......@@ -788,6 +798,17 @@ spi0: spi@1100a000 {
status = "disabled";
};
lvts_ap: thermal-sensor@1100b000 {
compatible = "mediatek,mt8192-lvts-ap";
reg = <0 0x1100b000 0 0xc00>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_THERM>;
resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>;
nvmem-cells = <&lvts_e_data1>;
nvmem-cell-names = "lvts-calib-data-1";
#thermal-sensor-cells = <1>;
};
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
......@@ -1114,6 +1135,17 @@ nor_flash: spi@11234000 {
status = "disabled";
};
lvts_mcu: thermal-sensor@11278000 {
compatible = "mediatek,mt8192-lvts-mcu";
reg = <0 0x11278000 0 0x1000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_THERM>;
resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
nvmem-cells = <&lvts_e_data1>;
nvmem-cell-names = "lvts-calib-data-1";
#thermal-sensor-cells = <1>;
};
efuse: efuse@11c10000 {
compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
reg = <0 0x11c10000 0 0x1000>;
......@@ -1899,4 +1931,426 @@ larb2: larb@1f002000 {
power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
};
};
thermal_zones: thermal-zones {
cpu0-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>;
trips {
cpu0_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu0_alert>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu1-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>;
trips {
cpu1_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_alert>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>;
trips {
cpu2_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_alert>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu3-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>;
trips {
cpu3_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_alert>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu4-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>;
trips {
cpu4_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu4_alert>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu5-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>;
trips {
cpu5_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu5_alert>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu6-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>;
trips {
cpu6_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu6_alert>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu7-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>;
trips {
cpu7_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu7_alert>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
vpu0-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_VPU0>;
trips {
vpu0_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
vpu0_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
vpu1-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_VPU1>;
trips {
vpu1_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
vpu1_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
gpu0-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_GPU0>;
trips {
gpu0_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
gpu0_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
gpu1-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_GPU1>;
trips {
gpu1_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
gpu1_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
infra-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_INFRA>;
trips {
infra_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
infra_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cam-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_CAM>;
trips {
cam_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cam_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
md0-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_MD0>;
trips {
md0_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
md0_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
md1-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_MD1>;
trips {
md1_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
md1_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
md2-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_MD2>;
trips {
md2_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
md2_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
};
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