Commit c7fbd415 authored by Peter De Schrijver's avatar Peter De Schrijver

clk: tegra124: remove gr2d and gr3d clocks

Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the
vic03 and gpu clocks respectively.
Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
parent a9952a76
...@@ -769,10 +769,8 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { ...@@ -769,10 +769,8 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true }, [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
[tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true }, [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
[tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true }, [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
[tegra_clk_gr2d] = { .dt_id = TEGRA124_CLK_GR_2D, .present = true },
[tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true }, [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
[tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true }, [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
[tegra_clk_gr3d] = { .dt_id = TEGRA124_CLK_GR_3D, .present = true },
[tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true }, [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
[tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true }, [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
[tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true }, [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
......
...@@ -36,10 +36,10 @@ ...@@ -36,10 +36,10 @@
#define TEGRA124_CLK_PWM 17 #define TEGRA124_CLK_PWM 17
#define TEGRA124_CLK_I2S2 18 #define TEGRA124_CLK_I2S2 18
/* 20 (register bit affects vi and vi_sensor) */ /* 20 (register bit affects vi and vi_sensor) */
#define TEGRA124_CLK_GR_2D 21 /* 21 */
#define TEGRA124_CLK_USBD 22 #define TEGRA124_CLK_USBD 22
#define TEGRA124_CLK_ISP 23 #define TEGRA124_CLK_ISP 23
#define TEGRA124_CLK_GR_3D 24 /* 26 */
/* 25 */ /* 25 */
#define TEGRA124_CLK_DISP2 26 #define TEGRA124_CLK_DISP2 26
#define TEGRA124_CLK_DISP1 27 #define TEGRA124_CLK_DISP1 27
......
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