Commit c81611c4 authored by Ian Campbell's avatar Ian Campbell Committed by Konrad Rzeszutek Wilk

xen: event channel arrays are xen_ulong_t and not unsigned long

On ARM we want these to be the same size on 32- and 64-bit.

This is an ABI change on ARM. X86 does not change.
Signed-off-by: default avatarIan Campbell <ian.campbell@citrix.com>
Cc: Jan Beulich <JBeulich@suse.com>
Cc: Keir (Xen.org) <keir@xen.org>
Cc: Tim Deegan <tim@xen.org>
Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: xen-devel@lists.xen.org
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
parent 76eaca03
...@@ -15,4 +15,26 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) ...@@ -15,4 +15,26 @@ static inline int xen_irqs_disabled(struct pt_regs *regs)
return raw_irqs_disabled_flags(regs->ARM_cpsr); return raw_irqs_disabled_flags(regs->ARM_cpsr);
} }
/*
* We cannot use xchg because it does not support 8-byte
* values. However it is safe to use {ldr,dtd}exd directly because all
* platforms which Xen can run on support those instructions.
*/
static inline xen_ulong_t xchg_xen_ulong(xen_ulong_t *ptr, xen_ulong_t val)
{
xen_ulong_t oldval;
unsigned int tmp;
wmb();
asm volatile("@ xchg_xen_ulong\n"
"1: ldrexd %0, %H0, [%3]\n"
" strexd %1, %2, %H2, [%3]\n"
" teq %1, #0\n"
" bne 1b"
: "=&r" (oldval), "=&r" (tmp)
: "r" (val), "r" (ptr)
: "memory", "cc");
return oldval;
}
#endif /* _ASM_ARM_XEN_EVENTS_H */ #endif /* _ASM_ARM_XEN_EVENTS_H */
...@@ -16,4 +16,7 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) ...@@ -16,4 +16,7 @@ static inline int xen_irqs_disabled(struct pt_regs *regs)
return raw_irqs_disabled_flags(regs->flags); return raw_irqs_disabled_flags(regs->flags);
} }
/* No need for a barrier -- XCHG is a barrier on x86. */
#define xchg_xen_ulong(ptr, val) xchg((ptr), (val))
#endif /* _ASM_X86_XEN_EVENTS_H */ #endif /* _ASM_X86_XEN_EVENTS_H */
This diff is collapsed.
...@@ -285,7 +285,7 @@ DEFINE_GUEST_HANDLE_STRUCT(multicall_entry); ...@@ -285,7 +285,7 @@ DEFINE_GUEST_HANDLE_STRUCT(multicall_entry);
* Event channel endpoints per domain: * Event channel endpoints per domain:
* 1024 if a long is 32 bits; 4096 if a long is 64 bits. * 1024 if a long is 32 bits; 4096 if a long is 64 bits.
*/ */
#define NR_EVENT_CHANNELS (sizeof(unsigned long) * sizeof(unsigned long) * 64) #define NR_EVENT_CHANNELS (sizeof(xen_ulong_t) * sizeof(xen_ulong_t) * 64)
struct vcpu_time_info { struct vcpu_time_info {
/* /*
...@@ -341,7 +341,7 @@ struct vcpu_info { ...@@ -341,7 +341,7 @@ struct vcpu_info {
*/ */
uint8_t evtchn_upcall_pending; uint8_t evtchn_upcall_pending;
uint8_t evtchn_upcall_mask; uint8_t evtchn_upcall_mask;
unsigned long evtchn_pending_sel; xen_ulong_t evtchn_pending_sel;
struct arch_vcpu_info arch; struct arch_vcpu_info arch;
struct pvclock_vcpu_time_info time; struct pvclock_vcpu_time_info time;
}; /* 64 bytes (x86) */ }; /* 64 bytes (x86) */
...@@ -384,8 +384,8 @@ struct shared_info { ...@@ -384,8 +384,8 @@ struct shared_info {
* per-vcpu selector word to be set. Each bit in the selector covers a * per-vcpu selector word to be set. Each bit in the selector covers a
* 'C long' in the PENDING bitfield array. * 'C long' in the PENDING bitfield array.
*/ */
unsigned long evtchn_pending[sizeof(unsigned long) * 8]; xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8];
unsigned long evtchn_mask[sizeof(unsigned long) * 8]; xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8];
/* /*
* Wallclock time: updated only by control software. Guests should base * Wallclock time: updated only by control software. Guests should base
......
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