Commit c911171a authored by Olof Johansson's avatar Olof Johansson

Merge tag 'mvebu-dt64-4.14-4' of git://git.infradead.org/linux-mvebu into next/dt64

mvebu dt64 for 4.14 (part 4)

Adding more resources on the network controller ppv2.2 on Armada 7K/8K
allowing to use last improvement introduced in the driver.

Also enabling more network ports on the mcbin (A8K base board)

* tag 'mvebu-dt64-4.14-4' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: mcbin: enable more networking ports
  arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node
  arm64: dts: marvell: add TX interrupts for PPv2.2
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ed09f6d0 72af17b9
...@@ -202,6 +202,30 @@ cpm_sdhci_pins: sdhci-pins { ...@@ -202,6 +202,30 @@ cpm_sdhci_pins: sdhci-pins {
}; };
}; };
&cpm_xmdio {
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
phy8: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cpm_ethernet {
status = "okay";
};
&cpm_eth0 {
status = "okay";
phy = <&phy0>;
phy-mode = "10gbase-kr";
};
&cpm_sata0 { &cpm_sata0 {
/* CPM Lane 0 - U29 */ /* CPM Lane 0 - U29 */
status = "okay"; status = "okay";
...@@ -231,6 +255,12 @@ &cps_ethernet { ...@@ -231,6 +255,12 @@ &cps_ethernet {
status = "okay"; status = "okay";
}; };
&cps_eth0 {
status = "okay";
phy = <&phy8>;
phy-mode = "10gbase-kr";
};
&cps_eth1 { &cps_eth1 {
/* CPS Lane 0 - J5 (Gigabit RJ45) */ /* CPS Lane 0 - J5 (Gigabit RJ45) */
status = "okay"; status = "okay";
......
...@@ -65,25 +65,44 @@ cpm_ethernet: ethernet@0 { ...@@ -65,25 +65,44 @@ cpm_ethernet: ethernet@0 {
reg = <0x0 0x100000>, <0x129000 0xb000>; reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>; clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk"; clock-names = "pp_clk", "gop_clk", "mg_clk";
marvell,system-controller = <&cpm_syscon0>;
status = "disabled"; status = "disabled";
dma-coherent; dma-coherent;
cpm_eth0: eth0 { cpm_eth0: eth0 {
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>; interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
port-id = <0>; port-id = <0>;
gop-port-id = <0>; gop-port-id = <0>;
status = "disabled"; status = "disabled";
}; };
cpm_eth1: eth1 { cpm_eth1: eth1 {
interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>; interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
port-id = <1>; port-id = <1>;
gop-port-id = <2>; gop-port-id = <2>;
status = "disabled"; status = "disabled";
}; };
cpm_eth2: eth2 { cpm_eth2: eth2 {
interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>; interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
port-id = <2>; port-id = <2>;
gop-port-id = <3>; gop-port-id = <3>;
status = "disabled"; status = "disabled";
......
...@@ -65,25 +65,44 @@ cps_ethernet: ethernet@0 { ...@@ -65,25 +65,44 @@ cps_ethernet: ethernet@0 {
reg = <0x0 0x100000>, <0x129000 0xb000>; reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>; clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk"; clock-names = "pp_clk", "gop_clk", "mg_clk";
marvell,system-controller = <&cps_syscon0>;
status = "disabled"; status = "disabled";
dma-coherent; dma-coherent;
cps_eth0: eth0 { cps_eth0: eth0 {
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>; interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
port-id = <0>; port-id = <0>;
gop-port-id = <0>; gop-port-id = <0>;
status = "disabled"; status = "disabled";
}; };
cps_eth1: eth1 { cps_eth1: eth1 {
interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>; interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
port-id = <1>; port-id = <1>;
gop-port-id = <2>; gop-port-id = <2>;
status = "disabled"; status = "disabled";
}; };
cps_eth2: eth2 { cps_eth2: eth2 {
interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>; interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
port-id = <2>; port-id = <2>;
gop-port-id = <3>; gop-port-id = <3>;
status = "disabled"; status = "disabled";
......
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