Commit cc1daf0b authored by Marc Zyngier's avatar Marc Zyngier

KVM: arm/arm64: vgic-v2: Only wipe LRs on vcpu exit

So far, we're always writing all possible LRs, setting the empty
ones with a zero value. This is obvious doing a lot of work for
nothing, and we're better off clearing those we've actually
dirtied on the exit path (it is very rare to inject more than one
interrupt at a time anyway).
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent d6400d77
...@@ -99,6 +99,7 @@ static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base) ...@@ -99,6 +99,7 @@ static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
} }
cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4)); cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
writel_relaxed(0, base + GICH_LR0 + (i * 4));
} }
} }
...@@ -156,12 +157,11 @@ void __hyp_text __vgic_v2_restore_state(struct kvm_vcpu *vcpu) ...@@ -156,12 +157,11 @@ void __hyp_text __vgic_v2_restore_state(struct kvm_vcpu *vcpu)
writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR); writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
writel_relaxed(cpu_if->vgic_apr, base + GICH_APR); writel_relaxed(cpu_if->vgic_apr, base + GICH_APR);
for (i = 0; i < nr_lr; i++) { for (i = 0; i < nr_lr; i++) {
u32 val = 0; if (!(live_lrs & (1UL << i)))
continue;
if (live_lrs & (1UL << i))
val = cpu_if->vgic_lr[i];
writel_relaxed(val, base + GICH_LR0 + (i * 4)); writel_relaxed(cpu_if->vgic_lr[i],
base + GICH_LR0 + (i * 4));
} }
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment