Commit cc74613b authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'pinctrl-v4.14-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "Two small things and a slightly larger thing in the Intel Cherryview.

   - Fix two build problems

   - Fix a regression on the Intel Cherryview interrupt path"

* tag 'pinctrl-v4.14-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: cherryview: fix issues caused by dynamic gpio irqs mapping
  pinctrl/amd: Fix build dependency on pinmux code
  pinctrl: bcm2835: fix build warning in bcm2835_gpio_irq_handle_bank
parents ce386181 845e405e
...@@ -100,6 +100,7 @@ config PINCTRL_AMD ...@@ -100,6 +100,7 @@ config PINCTRL_AMD
tristate "AMD GPIO pin control" tristate "AMD GPIO pin control"
depends on GPIOLIB depends on GPIOLIB
select GPIOLIB_IRQCHIP select GPIOLIB_IRQCHIP
select PINMUX
select PINCONF select PINCONF
select GENERIC_PINCONF select GENERIC_PINCONF
help help
......
...@@ -373,16 +373,12 @@ static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, ...@@ -373,16 +373,12 @@ static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
unsigned long events; unsigned long events;
unsigned offset; unsigned offset;
unsigned gpio; unsigned gpio;
unsigned int type;
events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
events &= mask; events &= mask;
events &= pc->enabled_irq_map[bank]; events &= pc->enabled_irq_map[bank];
for_each_set_bit(offset, &events, 32) { for_each_set_bit(offset, &events, 32) {
gpio = (32 * bank) + offset; gpio = (32 * bank) + offset;
/* FIXME: no clue why the code looks up the type here */
type = pc->irq_type[gpio];
generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain, generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain,
gpio)); gpio));
} }
......
...@@ -1577,6 +1577,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) ...@@ -1577,6 +1577,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
struct gpio_chip *chip = &pctrl->chip; struct gpio_chip *chip = &pctrl->chip;
bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
int ret, i, offset; int ret, i, offset;
int irq_base;
*chip = chv_gpio_chip; *chip = chv_gpio_chip;
...@@ -1622,7 +1623,18 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) ...@@ -1622,7 +1623,18 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
/* Clear all interrupts */ /* Clear all interrupts */
chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, if (!need_valid_mask) {
irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
chip->ngpio, NUMA_NO_NODE);
if (irq_base < 0) {
dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
return irq_base;
}
} else {
irq_base = 0;
}
ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, irq_base,
handle_bad_irq, IRQ_TYPE_NONE); handle_bad_irq, IRQ_TYPE_NONE);
if (ret) { if (ret) {
dev_err(pctrl->dev, "failed to add IRQ chip\n"); dev_err(pctrl->dev, "failed to add IRQ chip\n");
......
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