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Commit ce689628 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'samsung-clk-6.10-2' of... 

Merge tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung clk driver updates from Krzysztof Kozlowski:

 - Allow choice of manual or firmware-driven control over PLLs, needed
   to fully implement CPU clock controllers on Exynos850
 - Correct PLL clock IDs on ExynosAutov9
 - Propagate certain clock rates to allow setting proper SPI clock
   rates on Google GS101
 - Add HSI0 and HSI2 clock controllers for Google GS101
 - Mark certain Google GS101 clocks critical
 - Convert old S3C64xx clock controller bindings to DT schema

* tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: gs101: drop unused HSI2 clock parent data
  clk: samsung: gs101: mark some apm UASC and XIU clocks critical
  clk: samsung: gs101: add support for cmu_hsi2
  clk: samsung: gs101: add support for cmu_hsi0
  dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
  dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit
  clk: samsung: gs101: propagate PERIC1 USI SPI clock rate
  clk: samsung: gs101: propagate PERIC0 USI SPI clock rate
  clk: samsung: exynosautov9: fix wrong pll clock id value
  dt-bindings: clock: samsung,s3c6400-clock: convert to DT Schema
  clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1
  clk: samsung: Implement manual PLL control for ARM64 SoCs
parents 4cece764 7c18b0a5
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Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
View file @ ce689628
...@@ -30,16 +30,18 @@ properties: ...@@ -30,16 +30,18 @@ properties:
- google,gs101-cmu-top - google,gs101-cmu-top
- google,gs101-cmu-apm - google,gs101-cmu-apm
- google,gs101-cmu-misc - google,gs101-cmu-misc
- google,gs101-cmu-hsi0
- google,gs101-cmu-hsi2
- google,gs101-cmu-peric0 - google,gs101-cmu-peric0
- google,gs101-cmu-peric1 - google,gs101-cmu-peric1
clocks: clocks:
minItems: 1 minItems: 1
maxItems: 3 maxItems: 5
clock-names: clock-names:
minItems: 1 minItems: 1
maxItems: 3 maxItems: 5
"#clock-cells": "#clock-cells":
const: 1 const: 1
...@@ -72,6 +74,55 @@ allOf: ...@@ -72,6 +74,55 @@ allOf:
items: items:
- const: oscclk - const: oscclk
- if:
properties:
compatible:
contains:
const: google,gs101-cmu-hsi0
then:
properties:
clocks:
items:
- description: External reference clock (24.576 MHz)
- description: HSI0 bus clock (from CMU_TOP)
- description: DPGTC (from CMU_TOP)
- description: USB DRD controller clock (from CMU_TOP)
- description: USB Display Port debug clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: dpgtc
- const: usb31drd
- const: usbdpdbg
- if:
properties:
compatible:
contains:
enum:
- google,gs101-cmu-hsi2
then:
properties:
clocks:
items:
- description: External reference clock (24.576 MHz)
- description: High Speed Interface bus clock (from CMU_TOP)
- description: High Speed Interface pcie clock (from CMU_TOP)
- description: High Speed Interface ufs clock (from CMU_TOP)
- description: High Speed Interface mmc clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: pcie
- const: ufs
- const: mmc
- if: - if:
properties: properties:
compatible: compatible:
......
Documentation/devicetree/bindings/clock/samsung,s3c6400-clock.yaml 0 → 100644
View file @ ce689628
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,s3c6400-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C6400 SoC clock controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names and/or provided as clock inputs to this clock controller:
- "fin_pll" - PLL input clock (xtal/extclk) - required,
- "xusbxti" - USB xtal - required,
- "iiscdclk0" - I2S0 codec clock - optional,
- "iiscdclk1" - I2S1 codec clock - optional,
- "iiscdclk2" - I2S2 codec clock - optional,
- "pcmcdclk0" - PCM0 codec clock - optional,
- "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
All available clocks are defined as preprocessor macros in
include/dt-bindings/clock/samsung,s3c64xx-clock.h header.
properties:
compatible:
enum:
- samsung,s3c6400-clock
- samsung,s3c6410-clock
reg:
maxItems: 1
clocks:
maxItems: 1
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
clock-controller@7e00f000 {
compatible = "samsung,s3c6410-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
};
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt deleted 100644 → 0
View file @ 4cece764
* Samsung S3C64xx Clock Controller
The S3C64xx clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to all SoCs in
the S3C64xx family.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
- "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular S3C64xx SoC and this is specified where applicable.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "fin_pll" - PLL input clock (xtal/extclk) - required,
- "xusbxti" - USB xtal - required,
- "iiscdclk0" - I2S0 codec clock - optional,
- "iiscdclk1" - I2S1 codec clock - optional,
- "iiscdclk2" - I2S2 codec clock - optional,
- "pcmcdclk0" - PCM0 codec clock - optional,
- "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
Example: Clock controller node:
clock: clock-controller@7e00f000 {
compatible = "samsung,s3c6410-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
};
Example: Required external clocks:
fin_pll: clock-fin-pll {
compatible = "fixed-clock";
clock-output-names = "fin_pll";
clock-frequency = <12000000>;
#clock-cells = <0>;
};
xusbxti: clock-xusbxti {
compatible = "fixed-clock";
clock-output-names = "xusbxti";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
uart0: serial@7f005000 {
compatible = "samsung,s3c6400-uart";
reg = <0x7f005000 0x100>;
interrupt-parent = <&vic1>;
interrupts = <5>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
<&clock SCLK_UART>;
};
drivers/clk/samsung/clk-exynos-arm64.c
View file @ ce689628
...@@ -17,10 +17,17 @@ ...@@ -17,10 +17,17 @@
#include "clk-exynos-arm64.h" #include "clk-exynos-arm64.h"
/* PLL register bits */
#define PLL_CON1_MANUAL BIT(1)
/* Gate register bits */ /* Gate register bits */
#define GATE_MANUAL BIT(20) #define GATE_MANUAL BIT(20)
#define GATE_ENABLE_HWACG BIT(28) #define GATE_ENABLE_HWACG BIT(28)
/* PLL_CONx_PLL register offsets range */
#define PLL_CON_OFF_START 0x100
#define PLL_CON_OFF_END 0x600
/* Gate register offsets range */ /* Gate register offsets range */
#define GATE_OFF_START 0x2000 #define GATE_OFF_START 0x2000
#define GATE_OFF_END 0x2fff #define GATE_OFF_END 0x2fff
...@@ -38,17 +45,36 @@ struct exynos_arm64_cmu_data { ...@@ -38,17 +45,36 @@ struct exynos_arm64_cmu_data {
struct samsung_clk_provider *ctx; struct samsung_clk_provider *ctx;
}; };
/* Check if the register offset is a GATE register */
static bool is_gate_reg(unsigned long off)
{
return off >= GATE_OFF_START && off <= GATE_OFF_END;
}
/* Check if the register offset is a PLL_CONx register */
static bool is_pll_conx_reg(unsigned long off)
{
return off >= PLL_CON_OFF_START && off <= PLL_CON_OFF_END;
}
/* Check if the register offset is a PLL_CON1 register */
static bool is_pll_con1_reg(unsigned long off)
{
return is_pll_conx_reg(off) && (off & 0xf) == 0x4 && !(off & 0x10);
}
/** /**
* exynos_arm64_init_clocks - Set clocks initial configuration * exynos_arm64_init_clocks - Set clocks initial configuration
* @np: CMU device tree node with "reg" property (CMU addr) * @np: CMU device tree node with "reg" property (CMU addr)
* @reg_offs: Register offsets array for clocks to init * @cmu: CMU data
* @reg_offs_len: Number of register offsets in reg_offs array
* *
* Set manual control mode for all gate clocks. * Set manual control mode for all gate and PLL clocks.
*/ */
static void __init exynos_arm64_init_clocks(struct device_node *np, static void __init exynos_arm64_init_clocks(struct device_node *np,
const unsigned long *reg_offs, size_t reg_offs_len) const struct samsung_cmu_info *cmu)
{ {
const unsigned long *reg_offs = cmu->clk_regs;
size_t reg_offs_len = cmu->nr_clk_regs;
void __iomem *reg_base; void __iomem *reg_base;
size_t i; size_t i;
...@@ -60,15 +86,15 @@ static void __init exynos_arm64_init_clocks(struct device_node *np, ...@@ -60,15 +86,15 @@ static void __init exynos_arm64_init_clocks(struct device_node *np,
void __iomem *reg = reg_base + reg_offs[i]; void __iomem *reg = reg_base + reg_offs[i];
u32 val; u32 val;
/* Modify only gate clock registers */ if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) {
if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END) writel(PLL_CON1_MANUAL, reg);
continue; } else if (is_gate_reg(reg_offs[i])) {
val = readl(reg); val = readl(reg);
val |= GATE_MANUAL; val |= GATE_MANUAL;
val &= ~GATE_ENABLE_HWACG; val &= ~GATE_ENABLE_HWACG;
writel(val, reg); writel(val, reg);
} }
}
iounmap(reg_base); iounmap(reg_base);
} }
...@@ -177,7 +203,7 @@ void __init exynos_arm64_register_cmu(struct device *dev, ...@@ -177,7 +203,7 @@ void __init exynos_arm64_register_cmu(struct device *dev,
pr_err("%s: could not enable bus clock %s; err = %d\n", pr_err("%s: could not enable bus clock %s; err = %d\n",
__func__, cmu->clk_name, err); __func__, cmu->clk_name, err);
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs); exynos_arm64_init_clocks(np, cmu);
samsung_cmu_register_one(np, cmu); samsung_cmu_register_one(np, cmu);
} }
...@@ -224,7 +250,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev, ...@@ -224,7 +250,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev,
__func__, cmu->clk_name, ret); __func__, cmu->clk_name, ret);
if (set_manual) if (set_manual)
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs); exynos_arm64_init_clocks(np, cmu);
reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base)) if (IS_ERR(reg_base))
......
drivers/clk/samsung/clk-exynos850.c
View file @ ce689628
...@@ -14,13 +14,16 @@ ...@@ -14,13 +14,16 @@
#include <dt-bindings/clock/exynos850.h> #include <dt-bindings/clock/exynos850.h>
#include "clk.h" #include "clk.h"
#include "clk-cpu.h"
#include "clk-exynos-arm64.h" #include "clk-exynos-arm64.h"
/* NOTE: Must be equal to the last clock ID increased by one */ /* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1) #define CLKS_NR_TOP (CLK_DOUT_CPUCL1_SWITCH + 1)
#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1) #define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1) #define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1) #define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
#define CLKS_NR_CPUCL0 (CLK_CLUSTER0_SCLK + 1)
#define CLKS_NR_CPUCL1 (CLK_CLUSTER1_SCLK + 1)
#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1) #define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1) #define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1) #define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
...@@ -47,6 +50,10 @@ ...@@ -47,6 +50,10 @@
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1024
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1028
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG 0x102c
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1030
#define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
...@@ -69,6 +76,10 @@ ...@@ -69,6 +76,10 @@
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1830
#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1834
#define CLK_CON_DIV_CLKCMU_CPUCL1_DBG 0x1838
#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
#define CLK_CON_DIV_CLKCMU_DPU 0x1840 #define CLK_CON_DIV_CLKCMU_DPU 0x1840
#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
...@@ -97,6 +108,10 @@ ...@@ -97,6 +108,10 @@
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG 0x202c
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2030
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG 0x2034
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2038
#define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
...@@ -130,6 +145,10 @@ static const unsigned long top_clk_regs[] __initconst = { ...@@ -130,6 +145,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_DPU, CLK_CON_MUX_MUX_CLKCMU_DPU,
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
...@@ -152,6 +171,10 @@ static const unsigned long top_clk_regs[] __initconst = { ...@@ -152,6 +171,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_CLKCMU_CORE_CCI, CLK_CON_DIV_CLKCMU_CORE_CCI,
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
CLK_CON_DIV_CLKCMU_CORE_SSS, CLK_CON_DIV_CLKCMU_CORE_SSS,
CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
CLK_CON_DIV_CLKCMU_CPUCL1_DBG,
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
CLK_CON_DIV_CLKCMU_DPU, CLK_CON_DIV_CLKCMU_DPU,
CLK_CON_DIV_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_G3D_SWITCH,
CLK_CON_DIV_CLKCMU_HSI_BUS, CLK_CON_DIV_CLKCMU_HSI_BUS,
...@@ -180,6 +203,10 @@ static const unsigned long top_clk_regs[] __initconst = { ...@@ -180,6 +203,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG,
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG,
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_DPU, CLK_CON_GAT_GATE_CLKCMU_DPU,
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
...@@ -234,6 +261,14 @@ PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", ...@@ -234,6 +261,14 @@ PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
"oscclk", "oscclk" }; "oscclk", "oscclk" };
PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
"dout_shared0_div4", "dout_shared1_div4" }; "dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
PNAME(mout_cpucl0_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
"dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_cpucl0_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
PNAME(mout_cpucl1_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
"dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_cpucl1_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" }; "dout_shared0_div3", "dout_shared1_div3" };
...@@ -300,6 +335,18 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = { ...@@ -300,6 +335,18 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
/* CPUCL0 */
MUX(CLK_MOUT_CPUCL0_DBG, "mout_cpucl0_dbg", mout_cpucl0_dbg_p,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0, 1),
MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cpucl0_switch", mout_cpucl0_switch_p,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
/* CPUCL1 */
MUX(CLK_MOUT_CPUCL1_DBG, "mout_cpucl1_dbg", mout_cpucl1_dbg_p,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG, 0, 1),
MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cpucl1_switch", mout_cpucl1_switch_p,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
/* DPU */ /* DPU */
MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
...@@ -378,6 +425,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { ...@@ -378,6 +425,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
/* CPUCL0 */
DIV(CLK_DOUT_CPUCL0_DBG, "dout_cpucl0_dbg", "gout_cpucl0_dbg",
CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cpucl0_switch", "gout_cpucl0_switch",
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
/* CPUCL1 */
DIV(CLK_DOUT_CPUCL1_DBG, "dout_cpucl1_dbg", "gout_cpucl1_dbg",
CLK_CON_DIV_CLKCMU_CPUCL1_DBG, 0, 3),
DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cpucl1_switch", "gout_cpucl1_switch",
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
/* DPU */ /* DPU */
DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
CLK_CON_DIV_CLKCMU_DPU, 0, 4), CLK_CON_DIV_CLKCMU_DPU, 0, 4),
...@@ -442,6 +501,18 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { ...@@ -442,6 +501,18 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud", GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0), CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
/* CPUCL0 */
GATE(CLK_GOUT_CPUCL0_DBG, "gout_cpucl0_dbg", "mout_cpucl0_dbg",
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 21, 0, 0),
GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cpucl0_switch", "mout_cpucl0_switch",
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
/* CPUCL1 */
GATE(CLK_GOUT_CPUCL1_DBG, "gout_cpucl1_dbg", "mout_cpucl1_dbg",
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG, 21, 0, 0),
GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cpucl1_switch", "mout_cpucl1_switch",
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
/* DPU */ /* DPU */
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
...@@ -1030,6 +1101,373 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = { ...@@ -1030,6 +1101,373 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
.clk_name = "gout_clkcmu_cmgp_bus", .clk_name = "gout_clkcmu_cmgp_bus",
}; };
/* ---- CMU_CPUCL0 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_CPUCL0 (0x10900000) */
#define PLL_LOCKTIME_PLL_CPUCL0 0x0000
#define PLL_CON0_PLL_CPUCL0 0x0100
#define PLL_CON1_PLL_CPUCL0 0x0104
#define PLL_CON3_PLL_CPUCL0 0x010c
#define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0610
#define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL 0x100c
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1808
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG 0x180c
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
#define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF 0x1814
#define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU 0x1818
#define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK 0x181c
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK 0x2000
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK 0x2004
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK 0x2008
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK 0x200c
#define CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK 0x2010
#define CLK_CON_GAT_GATE_CLK_CPUCL0_CPU 0x2020
static const unsigned long cpucl0_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_CPUCL0,
PLL_CON0_PLL_CPUCL0,
PLL_CON1_PLL_CPUCL0,
PLL_CON3_PLL_CPUCL0,
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL,
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG,
CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF,
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU,
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK,
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK,
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK,
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK,
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK,
CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK,
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU,
};
/* List of parent clocks for Muxes in CMU_CPUCL0 */
PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_cpucl0_switch" };
PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_cpucl0_dbg" };
PNAME(mout_cpucl0_pll_p) = { "mout_pll_cpucl0",
"mout_cpucl0_switch_user" };
static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
PLL_35XX_RATE(26 * MHZ, 2210000000U, 255, 3, 0),
PLL_35XX_RATE(26 * MHZ, 2106000000U, 243, 3, 0),
PLL_35XX_RATE(26 * MHZ, 2002000000U, 231, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1846000000U, 213, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1742000000U, 201, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1586000000U, 183, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1456000000U, 168, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1300000000U, 150, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1157000000U, 267, 3, 1),
PLL_35XX_RATE(26 * MHZ, 1053000000U, 243, 3, 1),
PLL_35XX_RATE(26 * MHZ, 949000000U, 219, 3, 1),
PLL_35XX_RATE(26 * MHZ, 806000000U, 186, 3, 1),
PLL_35XX_RATE(26 * MHZ, 650000000U, 150, 3, 1),
PLL_35XX_RATE(26 * MHZ, 546000000U, 252, 3, 2),
PLL_35XX_RATE(26 * MHZ, 442000000U, 204, 3, 2),
PLL_35XX_RATE(26 * MHZ, 351000000U, 162, 3, 2),
PLL_35XX_RATE(26 * MHZ, 247000000U, 114, 3, 2),
PLL_35XX_RATE(26 * MHZ, 182000000U, 168, 3, 3),
PLL_35XX_RATE(26 * MHZ, 130000000U, 120, 3, 3),
};
static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
PLL(pll_0822x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
};
static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
MUX_F(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
PLL_CON0_PLL_CPUCL0, 4, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX_F(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user",
mout_cpucl0_switch_user_p,
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1,
CLK_SET_RATE_PARENT, 0),
MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user",
mout_cpucl0_dbg_user_p,
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
MUX_F(CLK_MOUT_CPUCL0_PLL, "mout_cpucl0_pll", mout_cpucl0_pll_p,
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
DIV_F(CLK_DOUT_CPUCL0_CPU, "dout_cpucl0_cpu", "mout_cpucl0_pll",
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 1,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CPUCL0_CMUREF, "dout_cpucl0_cmuref", "dout_cpucl0_cpu",
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0, 3,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CPUCL0_PCLK, "dout_cpucl0_pclk", "dout_cpucl0_cpu",
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
/* EMBEDDED_CMU_CPUCL0 */
DIV_F(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk", "gout_cluster0_cpu",
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER0_PCLKDBG, "dout_cluster0_pclkdbg",
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
};
static const struct samsung_gate_clock cpucl0_gate_clks[] __initconst = {
GATE(CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK, "gout_cpucl0_cmu_cpucl0_pclk",
"dout_cpucl0_pclk",
CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
/* EMBEDDED_CMU_CPUCL0 */
GATE(CLK_GOUT_CLUSTER0_CPU, "gout_cluster0_cpu", "dout_cpucl0_cpu",
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER0_SCLK, "gout_cluster0_sclk", "gout_cluster0_cpu",
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER0_ATCLK, "gout_cluster0_atclk",
"dout_cluster0_atclk",
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER0_PERIPHCLK, "gout_cluster0_periphclk",
"dout_cluster0_periphclk",
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER0_PCLK, "gout_cluster0_pclk",
"dout_cluster0_pclkdbg",
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
};
/*
* Each parameter is going to be written into the corresponding DIV register. So
* the actual divider value for each parameter will be 1/(param+1). All these
* parameters must be in the range of 0..15, as the divider range for all of
* these DIV clocks is 1..16. The default values for these dividers is
* (1, 3, 3, 1).
*/
#define E850_CPU_DIV0(aclk, atclk, pclkdbg, periphclk) \
(((aclk) << 16) | ((atclk) << 12) | ((pclkdbg) << 8) | \
((periphclk) << 4))
static const struct exynos_cpuclk_cfg_data exynos850_cluster_clk_d[] __initconst
= {
{ 2210000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 2106000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 2002000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1846000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1742000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1586000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1456000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1300000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1157000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1053000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 949000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 806000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 650000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 546000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 442000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 351000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 247000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 182000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 130000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 0 }
};
static const struct samsung_cpu_clock cpucl0_cpu_clks[] __initconst = {
CPU_CLK(CLK_CLUSTER0_SCLK, "cluster0_clk", CLK_MOUT_PLL_CPUCL0,
CLK_MOUT_CPUCL0_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL0,
exynos850_cluster_clk_d),
};
static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
.pll_clks = cpucl0_pll_clks,
.nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
.mux_clks = cpucl0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
.div_clks = cpucl0_div_clks,
.nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
.gate_clks = cpucl0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cpucl0_gate_clks),
.cpu_clks = cpucl0_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(cpucl0_cpu_clks),
.nr_clk_ids = CLKS_NR_CPUCL0,
.clk_regs = cpucl0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
.clk_name = "dout_cpucl0_switch",
.manual_plls = true,
};
static void __init exynos850_cmu_cpucl0_init(struct device_node *np)
{
exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
}
/* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
CLK_OF_DECLARE(exynos850_cmu_cpucl0, "samsung,exynos850-cmu-cpucl0",
exynos850_cmu_cpucl0_init);
/* ---- CMU_CPUCL1 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_CPUCL1 (0x10800000) */
#define PLL_LOCKTIME_PLL_CPUCL1 0x0000
#define PLL_CON0_PLL_CPUCL1 0x0100
#define PLL_CON1_PLL_CPUCL1 0x0104
#define PLL_CON3_PLL_CPUCL1 0x010c
#define PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
#define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL 0x1000
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1808
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG 0x180c
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
#define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF 0x1814
#define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU 0x1818
#define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK 0x181c
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK 0x2000
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK 0x2004
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK 0x2008
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK 0x200c
#define CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK 0x2010
#define CLK_CON_GAT_GATE_CLK_CPUCL1_CPU 0x2020
static const unsigned long cpucl1_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_CPUCL1,
PLL_CON0_PLL_CPUCL1,
PLL_CON1_PLL_CPUCL1,
PLL_CON3_PLL_CPUCL1,
PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER,
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL,
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG,
CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF,
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU,
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK,
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK,
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK,
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK,
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK,
CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK,
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
};
/* List of parent clocks for Muxes in CMU_CPUCL0 */
PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_cpucl1_switch" };
PNAME(mout_cpucl1_dbg_user_p) = { "oscclk", "dout_cpucl1_dbg" };
PNAME(mout_cpucl1_pll_p) = { "mout_pll_cpucl1",
"mout_cpucl1_switch_user" };
static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
PLL(pll_0822x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
};
static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
MUX_F(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
PLL_CON0_PLL_CPUCL1, 4, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX_F(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user",
mout_cpucl1_switch_user_p,
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1,
CLK_SET_RATE_PARENT, 0),
MUX(CLK_MOUT_CPUCL1_DBG_USER, "mout_cpucl1_dbg_user",
mout_cpucl1_dbg_user_p,
PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER, 4, 1),
MUX_F(CLK_MOUT_CPUCL1_PLL, "mout_cpucl1_pll", mout_cpucl1_pll_p,
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
DIV_F(CLK_DOUT_CPUCL1_CPU, "dout_cpucl1_cpu", "mout_cpucl1_pll",
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0, 1,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CPUCL1_CMUREF, "dout_cpucl1_cmuref", "dout_cpucl1_cpu",
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0, 3,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CPUCL1_PCLK, "dout_cpucl1_pclk", "dout_cpucl1_cpu",
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
/* EMBEDDED_CMU_CPUCL1 */
DIV_F(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk", "gout_cluster1_cpu",
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER1_PCLKDBG, "dout_cluster1_pclkdbg",
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
};
static const struct samsung_gate_clock cpucl1_gate_clks[] __initconst = {
GATE(CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK, "gout_cpucl1_cmu_cpucl1_pclk",
"dout_cpucl1_pclk",
CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
/* EMBEDDED_CMU_CPUCL1 */
GATE(CLK_GOUT_CLUSTER1_CPU, "gout_cluster1_cpu", "dout_cpucl1_cpu",
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER1_SCLK, "gout_cluster1_sclk", "gout_cluster1_cpu",
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER1_ATCLK, "gout_cluster1_atclk",
"dout_cluster1_atclk",
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER1_PERIPHCLK, "gout_cluster1_periphclk",
"dout_cluster1_periphclk",
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER1_PCLK, "gout_cluster1_pclk",
"dout_cluster1_pclkdbg",
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cpu_clock cpucl1_cpu_clks[] __initconst = {
CPU_CLK(CLK_CLUSTER1_SCLK, "cluster1_clk", CLK_MOUT_PLL_CPUCL1,
CLK_MOUT_CPUCL1_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL1,
exynos850_cluster_clk_d),
};
static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
.pll_clks = cpucl1_pll_clks,
.nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
.mux_clks = cpucl1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
.div_clks = cpucl1_div_clks,
.nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
.gate_clks = cpucl1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cpucl1_gate_clks),
.cpu_clks = cpucl1_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(cpucl1_cpu_clks),
.nr_clk_ids = CLKS_NR_CPUCL1,
.clk_regs = cpucl1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
.clk_name = "dout_cpucl1_switch",
.manual_plls = true,
};
static void __init exynos850_cmu_cpucl1_init(struct device_node *np)
{
exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
}
/* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
CLK_OF_DECLARE(exynos850_cmu_cpucl1, "samsung,exynos850-cmu-cpucl1",
exynos850_cmu_cpucl1_init);
/* ---- CMU_G3D ------------------------------------------------------------- */ /* ---- CMU_G3D ------------------------------------------------------------- */
/* Register Offset definitions for CMU_G3D (0x11400000) */ /* Register Offset definitions for CMU_G3D (0x11400000) */
......
drivers/clk/samsung/clk-exynosautov9.c
View file @ ce689628
...@@ -352,13 +352,13 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = { ...@@ -352,13 +352,13 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
/* CMU_TOP_PURECLKCOMP */ /* CMU_TOP_PURECLKCOMP */
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared1_pll", "oscclk", PLL(pll_0822x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL), PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared2_pll", "oscclk", PLL(pll_0822x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL), PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared3_pll", "oscclk", PLL(pll_0822x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL), PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared4_pll", "oscclk", PLL(pll_0822x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL), PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
}; };
......
drivers/clk/samsung/clk-gs101.c
View file @ ce689628
...@@ -15,10 +15,13 @@ ...@@ -15,10 +15,13 @@
#include "clk.h" #include "clk.h"
#include "clk-exynos-arm64.h" #include "clk-exynos-arm64.h"
#include "clk-pll.h"
/* NOTE: Must be equal to the last clock ID increased by one */ /* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)
#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_P_HSI0_ACLK + 1)
#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
...@@ -1893,16 +1896,16 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = { ...@@ -1893,16 +1896,16 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
GATE(CLK_GOUT_APM_UASC_P_APM_ACLK, GATE(CLK_GOUT_APM_UASC_P_APM_ACLK,
"gout_apm_uasc_p_apm_aclk", "gout_apm_func", "gout_apm_uasc_p_apm_aclk", "gout_apm_func",
CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, 0, 0), CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_APM_UASC_P_APM_PCLK, GATE(CLK_GOUT_APM_UASC_P_APM_PCLK,
"gout_apm_uasc_p_apm_pclk", "gout_apm_func", "gout_apm_uasc_p_apm_pclk", "gout_apm_func",
CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0), CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_APM_WDT_APM_PCLK, GATE(CLK_GOUT_APM_WDT_APM_PCLK,
"gout_apm_wdt_apm_pclk", "gout_apm_func", "gout_apm_wdt_apm_pclk", "gout_apm_func",
CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0), CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0),
GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK, GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK,
"gout_apm_xiu_dp_apm_aclk", "gout_apm_func", "gout_apm_xiu_dp_apm_aclk", "gout_apm_func",
CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0), CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
}; };
static const struct samsung_cmu_info apm_cmu_info __initconst = { static const struct samsung_cmu_info apm_cmu_info __initconst = {
...@@ -1919,6 +1922,958 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = { ...@@ -1919,6 +1922,958 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs), .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
}; };
/* ---- CMU_HSI0 ------------------------------------------------------------ */
/* Register Offset definitions for CMU_HSI0 (0x11000000) */
#define PLL_LOCKTIME_PLL_USB 0x0004
#define PLL_CON0_PLL_USB 0x0140
#define PLL_CON1_PLL_USB 0x0144
#define PLL_CON2_PLL_USB 0x0148
#define PLL_CON3_PLL_USB 0x014c
#define PLL_CON4_PLL_USB 0x0150
#define PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER 0x0600
#define PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER 0x0604
#define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0610
#define PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER 0x0614
#define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0620
#define PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER 0x0624
#define PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER 0x0630
#define PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER 0x0634
#define PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER 0x0640
#define PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER 0x0644
#define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0650
#define PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0654
#define PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0660
#define PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0664
#define HSI0_CMU_HSI0_CONTROLLER_OPTION 0x0800
#define CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0 0x0810
#define CLK_CON_MUX_MUX_CLK_HSI0_BUS 0x1000
#define CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF 0x1004
#define CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD 0x1008
#define CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD 0x1800
#define CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000
#define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26 0x2004
#define CLK_CON_GAT_CLK_HSI0_ALT 0x2008
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x200c
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2010
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x2014
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK 0x2018
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK 0x201c
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK 0x2020
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK 0x2024
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK 0x2028
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x202c
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2030
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK 0x2034
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK 0x2038
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK 0x203c
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK 0x2040
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK 0x2044
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2048
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK 0x204c
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK 0x2050
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2054
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2058
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK 0x205c
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK 0x2060
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK 0x2064
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK 0x2068
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x206c
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2070
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26 0x2074
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2078
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x207c
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x2080
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2084
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK 0x2088
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK 0x208c
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK 0x2090
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK 0x2094
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK 0x2098
#define DMYQCH_CON_USB31DRD_QCH 0x3000
#define DMYQCH_CON_USB31DRD_QCH_REF 0x3004
#define PCH_CON_LHM_AXI_G_ETR_HSI0_PCH 0x3008
#define PCH_CON_LHM_AXI_P_AOCHSI0_PCH 0x300c
#define PCH_CON_LHM_AXI_P_HSI0_PCH 0x3010
#define PCH_CON_LHS_ACEL_D_HSI0_PCH 0x3014
#define PCH_CON_LHS_AXI_D_HSI0AOC_PCH 0x3018
#define QCH_CON_DP_LINK_QCH_GTC_CLK 0x301c
#define QCH_CON_DP_LINK_QCH_PCLK 0x3020
#define QCH_CON_D_TZPC_HSI0_QCH 0x3024
#define QCH_CON_ETR_MIU_QCH_ACLK 0x3028
#define QCH_CON_ETR_MIU_QCH_PCLK 0x302c
#define QCH_CON_GPC_HSI0_QCH 0x3030
#define QCH_CON_HSI0_CMU_HSI0_QCH 0x3034
#define QCH_CON_LHM_AXI_G_ETR_HSI0_QCH 0x3038
#define QCH_CON_LHM_AXI_P_AOCHSI0_QCH 0x303c
#define QCH_CON_LHM_AXI_P_HSI0_QCH 0x3040
#define QCH_CON_LHS_ACEL_D_HSI0_QCH 0x3044
#define QCH_CON_LHS_AXI_D_HSI0AOC_QCH 0x3048
#define QCH_CON_PPMU_HSI0_AOC_QCH 0x304c
#define QCH_CON_PPMU_HSI0_BUS0_QCH 0x3050
#define QCH_CON_SSMT_USB_QCH 0x3054
#define QCH_CON_SYSMMU_USB_QCH 0x3058
#define QCH_CON_SYSREG_HSI0_QCH 0x305c
#define QCH_CON_UASC_HSI0_CTRL_QCH 0x3060
#define QCH_CON_UASC_HSI0_LINK_QCH 0x3064
#define QCH_CON_USB31DRD_QCH_APB 0x3068
#define QCH_CON_USB31DRD_QCH_DBG 0x306c
#define QCH_CON_USB31DRD_QCH_PCS 0x3070
#define QCH_CON_USB31DRD_QCH_SLV_CTRL 0x3074
#define QCH_CON_USB31DRD_QCH_SLV_LINK 0x3078
#define QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0 0x3c00
static const unsigned long hsi0_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_USB,
PLL_CON0_PLL_USB,
PLL_CON1_PLL_USB,
PLL_CON2_PLL_USB,
PLL_CON3_PLL_USB,
PLL_CON4_PLL_USB,
PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER,
PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER,
PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER,
PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER,
PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER,
PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER,
PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER,
PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER,
PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER,
PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER,
PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER,
HSI0_CMU_HSI0_CONTROLLER_OPTION,
CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0,
CLK_CON_MUX_MUX_CLK_HSI0_BUS,
CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF,
CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD,
CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD,
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26,
CLK_CON_GAT_CLK_HSI0_ALT,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK,
DMYQCH_CON_USB31DRD_QCH,
DMYQCH_CON_USB31DRD_QCH_REF,
PCH_CON_LHM_AXI_G_ETR_HSI0_PCH,
PCH_CON_LHM_AXI_P_AOCHSI0_PCH,
PCH_CON_LHM_AXI_P_HSI0_PCH,
PCH_CON_LHS_ACEL_D_HSI0_PCH,
PCH_CON_LHS_AXI_D_HSI0AOC_PCH,
QCH_CON_DP_LINK_QCH_GTC_CLK,
QCH_CON_DP_LINK_QCH_PCLK,
QCH_CON_D_TZPC_HSI0_QCH,
QCH_CON_ETR_MIU_QCH_ACLK,
QCH_CON_ETR_MIU_QCH_PCLK,
QCH_CON_GPC_HSI0_QCH,
QCH_CON_HSI0_CMU_HSI0_QCH,
QCH_CON_LHM_AXI_G_ETR_HSI0_QCH,
QCH_CON_LHM_AXI_P_AOCHSI0_QCH,
QCH_CON_LHM_AXI_P_HSI0_QCH,
QCH_CON_LHS_ACEL_D_HSI0_QCH,
QCH_CON_LHS_AXI_D_HSI0AOC_QCH,
QCH_CON_PPMU_HSI0_AOC_QCH,
QCH_CON_PPMU_HSI0_BUS0_QCH,
QCH_CON_SSMT_USB_QCH,
QCH_CON_SYSMMU_USB_QCH,
QCH_CON_SYSREG_HSI0_QCH,
QCH_CON_UASC_HSI0_CTRL_QCH,
QCH_CON_UASC_HSI0_LINK_QCH,
QCH_CON_USB31DRD_QCH_APB,
QCH_CON_USB31DRD_QCH_DBG,
QCH_CON_USB31DRD_QCH_PCS,
QCH_CON_USB31DRD_QCH_SLV_CTRL,
QCH_CON_USB31DRD_QCH_SLV_LINK,
QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0,
};
/* List of parent clocks for Muxes in CMU_HSI0 */
PNAME(mout_pll_usb_p) = { "oscclk", "fout_usb_pll" };
PNAME(mout_hsi0_alt_user_p) = { "oscclk",
"gout_hsi0_clk_hsi0_alt" };
PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" };
PNAME(mout_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" };
PNAME(mout_hsi0_tcxo_user_p) = { "oscclk", "tcxo_hsi1_hsi0" };
PNAME(mout_hsi0_usb20_user_p) = { "oscclk", "usb20phy_phy_clock" };
PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk",
"dout_cmu_hsi0_usb31drd" };
PNAME(mout_hsi0_usbdpdbg_user_p) = { "oscclk",
"dout_cmu_hsi0_usbdpdbg" };
PNAME(mout_hsi0_bus_p) = { "mout_hsi0_bus_user",
"mout_hsi0_alt_user" };
PNAME(mout_hsi0_usb20_ref_p) = { "fout_usb_pll",
"mout_hsi0_tcxo_user" };
PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll",
"mout_hsi0_usb31drd_user",
"dout_hsi0_usb31drd",
"fout_usb_pll" };
static const struct samsung_pll_rate_table cmu_hsi0_usb_pll_rates[] __initconst = {
PLL_35XX_RATE(24576000, 19200000, 150, 6, 5),
{ /* sentinel */ }
};
static const struct samsung_pll_clock cmu_hsi0_pll_clks[] __initconst = {
PLL(pll_0518x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
PLL_LOCKTIME_PLL_USB, PLL_CON3_PLL_USB,
cmu_hsi0_usb_pll_rates),
};
static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
MUX(CLK_MOUT_PLL_USB,
"mout_pll_usb", mout_pll_usb_p,
PLL_CON0_PLL_USB, 4, 1),
MUX(CLK_MOUT_HSI0_ALT_USER,
"mout_hsi0_alt_user", mout_hsi0_alt_user_p,
PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER, 4, 1),
MUX(CLK_MOUT_HSI0_BUS_USER,
"mout_hsi0_bus_user", mout_hsi0_bus_user_p,
PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER, 4, 1),
MUX(CLK_MOUT_HSI0_DPGTC_USER,
"mout_hsi0_dpgtc_user", mout_hsi0_dpgtc_user_p,
PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 4, 1),
MUX(CLK_MOUT_HSI0_TCXO_USER,
"mout_hsi0_tcxo_user", mout_hsi0_tcxo_user_p,
PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER, 4, 1),
MUX(CLK_MOUT_HSI0_USB20_USER,
"mout_hsi0_usb20_user", mout_hsi0_usb20_user_p,
PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER, 4, 1),
MUX(CLK_MOUT_HSI0_USB31DRD_USER,
"mout_hsi0_usb31drd_user", mout_hsi0_usb31drd_user_p,
PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, 4, 1),
MUX(CLK_MOUT_HSI0_USBDPDBG_USER,
"mout_hsi0_usbdpdbg_user", mout_hsi0_usbdpdbg_user_p,
PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER, 4, 1),
MUX(CLK_MOUT_HSI0_BUS,
"mout_hsi0_bus", mout_hsi0_bus_p,
CLK_CON_MUX_MUX_CLK_HSI0_BUS, 0, 1),
MUX(CLK_MOUT_HSI0_USB20_REF,
"mout_hsi0_usb20_ref", mout_hsi0_usb20_ref_p,
CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, 0, 1),
MUX(CLK_MOUT_HSI0_USB31DRD,
"mout_hsi0_usb31drd", mout_hsi0_usb31drd_p,
CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 0, 2),
};
static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
DIV(CLK_DOUT_HSI0_USB31DRD,
"dout_hsi0_usb31drd", "mout_hsi0_usb20_user",
CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 0, 3),
};
static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = {
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI0_PCLK,
"gout_hsi0_hsi0_pclk", "mout_hsi0_bus",
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26,
"gout_hsi0_usb31drd_i_usb31drd_suspend_clk_26",
"mout_hsi0_usb20_ref",
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26,
21, 0, 0),
GATE(CLK_GOUT_HSI0_CLK_HSI0_ALT,
"gout_hsi0_clk_hsi0_alt", "ioclk_clk_hsi0_alt",
CLK_CON_GAT_CLK_HSI0_ALT, 21, 0, 0),
GATE(CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK,
"gout_hsi0_dp_link_i_dp_gtc_clk", "mout_hsi0_dpgtc_user",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_DP_LINK_I_PCLK,
"gout_hsi0_dp_link_i_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK,
"gout_hsi0_d_tzpc_hsi0_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_ETR_MIU_I_ACLK,
"gout_hsi0_etr_miu_i_aclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_HSI0_ETR_MIU_I_PCLK,
"gout_hsi0_etr_miu_i_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI0_GPC_HSI0_PCLK,
"gout_hsi0_gpc_hsi0_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK,
"gout_hsi0_lhm_axi_g_etr_hsi0_i_clk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK,
"gout_hsi0_lhm_axi_p_aochsi0_i_clk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK,
21, 0, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK,
"gout_hsi0_lhm_axi_p_hsi0_i_clk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
21, CLK_IGNORE_UNUSED, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK,
"gout_hsi0_lhs_acel_d_hsi0_i_clk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK,
"gout_hsi0_lhs_axi_d_hsi0aoc_i_clk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK,
"gout_hsi0_ppmu_hsi0_aoc_aclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK,
"gout_hsi0_ppmu_hsi0_aoc_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK,
"gout_hsi0_ppmu_hsi0_bus0_aclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK,
"gout_hsi0_ppmu_hsi0_bus0_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK,
"gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
21, 0, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI0_SSMT_USB_ACLK,
"gout_hsi0_ssmt_usb_aclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK,
21, CLK_IGNORE_UNUSED, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI0_SSMT_USB_PCLK,
"gout_hsi0_ssmt_usb_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK,
21, CLK_IGNORE_UNUSED, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2,
"gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK,
"gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK,
"gout_hsi0_uasc_hsi0_ctrl_aclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK,
"gout_hsi0_uasc_hsi0_ctrl_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK,
"gout_hsi0_uasc_hsi0_link_aclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK,
"gout_hsi0_uasc_hsi0_link_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL,
"gout_hsi0_usb31drd_aclk_phyctrl", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
21, 0, 0),
GATE(CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY,
"gout_hsi0_usb31drd_bus_clk_early", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
21, 0, 0),
GATE(CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26,
"gout_hsi0_usb31drd_i_usb20_phy_refclk_26", "mout_hsi0_usb20_ref",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26,
21, 0, 0),
GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40,
"gout_hsi0_usb31drd_i_usb31drd_ref_clk_40", "mout_hsi0_usb31drd",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
21, 0, 0),
GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL,
"gout_hsi0_usb31drd_i_usbdpphy_ref_soc_pll",
"mout_hsi0_usbdpdbg_user",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
21, 0, 0),
GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK,
"gout_hsi0_usb31drd_i_usbdpphy_scl_apb_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK,
"gout_hsi0_usb31drd_i_usbpcs_apb_clk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK,
"gout_hsi0_usb31drd_usbdpphy_i_aclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK,
"gout_hsi0_usb31drd_usbdpphy_udbg_i_apb_pclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK,
21, 0, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK,
"gout_hsi0_xiu_d0_hsi0_aclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK,
21, CLK_IGNORE_UNUSED, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK,
"gout_hsi0_xiu_d1_hsi0_aclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK,
21, CLK_IGNORE_UNUSED, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI0_XIU_P_HSI0_ACLK,
"gout_hsi0_xiu_p_hsi0_aclk", "mout_hsi0_bus",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK,
21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = {
FRATE(0, "tcxo_hsi1_hsi0", NULL, 0, 26000000),
FRATE(0, "usb20phy_phy_clock", NULL, 0, 120000000),
/* until we implement APMGSA */
FRATE(0, "ioclk_clk_hsi0_alt", NULL, 0, 213000000),
};
static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
.pll_clks = cmu_hsi0_pll_clks,
.nr_pll_clks = ARRAY_SIZE(cmu_hsi0_pll_clks),
.mux_clks = hsi0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
.div_clks = hsi0_div_clks,
.nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
.gate_clks = hsi0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(hsi0_gate_clks),
.fixed_clks = hsi0_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(hsi0_fixed_clks),
.nr_clk_ids = CLKS_NR_HSI0,
.clk_regs = hsi0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
.clk_name = "bus",
};
/* ---- CMU_HSI2 ------------------------------------------------------------ */
/* Register Offset definitions for CMU_HSI2 (0x14400000) */
#define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
#define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
#define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
#define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
#define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
#define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
#define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
#define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
#define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK 0x2068
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK 0x206c
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK 0x2070
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK 0x2074
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK 0x2078
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK 0x207c
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK 0x2080
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK 0x2084
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK 0x2088
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK 0x208c
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK 0x2090
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK 0x2094
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK 0x2098
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK 0x209c
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK 0x20a0
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK 0x20a4
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2 0x20a8
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK 0x20ac
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK 0x20b0
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK 0x20b4
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK 0x20b8
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK 0x20bc
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK 0x20c0
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK 0x20c4
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK 0x20c8
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK 0x20cc
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x20d0
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x20d4
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x20d8
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK 0x20dc
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK 0x20e0
#define DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1 0x3000
#define PCH_CON_LHM_AXI_P_HSI2_PCH 0x3008
#define PCH_CON_LHS_ACEL_D_HSI2_PCH 0x300c
#define QCH_CON_D_TZPC_HSI2_QCH 0x3010
#define QCH_CON_GPC_HSI2_QCH 0x3014
#define QCH_CON_GPIO_HSI2_QCH 0x3018
#define QCH_CON_HSI2_CMU_HSI2_QCH 0x301c
#define QCH_CON_LHM_AXI_P_HSI2_QCH 0x3020
#define QCH_CON_LHS_ACEL_D_HSI2_QCH 0x3024
#define QCH_CON_MMC_CARD_QCH 0x3028
#define QCH_CON_PCIE_GEN4_1_QCH_APB_1 0x302c
#define QCH_CON_PCIE_GEN4_1_QCH_APB_2 0x3030
#define QCH_CON_PCIE_GEN4_1_QCH_AXI_1 0x3034
#define QCH_CON_PCIE_GEN4_1_QCH_AXI_2 0x3038
#define QCH_CON_PCIE_GEN4_1_QCH_DBG_1 0x303c
#define QCH_CON_PCIE_GEN4_1_QCH_DBG_2 0x3040
#define QCH_CON_PCIE_GEN4_1_QCH_PCS_APB 0x3044
#define QCH_CON_PCIE_GEN4_1_QCH_PMA_APB 0x3048
#define QCH_CON_PCIE_GEN4_1_QCH_UDBG 0x304c
#define QCH_CON_PCIE_IA_GEN4A_1_QCH 0x3050
#define QCH_CON_PCIE_IA_GEN4B_1_QCH 0x3054
#define QCH_CON_PPMU_HSI2_QCH 0x3058
#define QCH_CON_QE_MMC_CARD_HSI2_QCH 0x305c
#define QCH_CON_QE_PCIE_GEN4A_HSI2_QCH 0x3060
#define QCH_CON_QE_PCIE_GEN4B_HSI2_QCH 0x3064
#define QCH_CON_QE_UFS_EMBD_HSI2_QCH 0x3068
#define QCH_CON_SSMT_HSI2_QCH 0x306c
#define QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH 0x3070
#define QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH 0x3074
#define QCH_CON_SYSMMU_HSI2_QCH 0x3078
#define QCH_CON_SYSREG_HSI2_QCH 0x307c
#define QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH 0x3080
#define QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH 0x3084
#define QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH 0x3088
#define QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH 0x308c
#define QCH_CON_UFS_EMBD_QCH 0x3090
#define QCH_CON_UFS_EMBD_QCH_FMP 0x3094
#define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00
static const unsigned long cmu_hsi2_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER,
PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER,
PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER,
PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER,
PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
HSI2_CMU_HSI2_CONTROLLER_OPTION,
CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0,
CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1,
PCH_CON_LHM_AXI_P_HSI2_PCH,
PCH_CON_LHS_ACEL_D_HSI2_PCH,
QCH_CON_D_TZPC_HSI2_QCH,
QCH_CON_GPC_HSI2_QCH,
QCH_CON_GPIO_HSI2_QCH,
QCH_CON_HSI2_CMU_HSI2_QCH,
QCH_CON_LHM_AXI_P_HSI2_QCH,
QCH_CON_LHS_ACEL_D_HSI2_QCH,
QCH_CON_MMC_CARD_QCH,
QCH_CON_PCIE_GEN4_1_QCH_APB_1,
QCH_CON_PCIE_GEN4_1_QCH_APB_2,
QCH_CON_PCIE_GEN4_1_QCH_AXI_1,
QCH_CON_PCIE_GEN4_1_QCH_AXI_2,
QCH_CON_PCIE_GEN4_1_QCH_DBG_1,
QCH_CON_PCIE_GEN4_1_QCH_DBG_2,
QCH_CON_PCIE_GEN4_1_QCH_PCS_APB,
QCH_CON_PCIE_GEN4_1_QCH_PMA_APB,
QCH_CON_PCIE_GEN4_1_QCH_UDBG,
QCH_CON_PCIE_IA_GEN4A_1_QCH,
QCH_CON_PCIE_IA_GEN4B_1_QCH,
QCH_CON_PPMU_HSI2_QCH,
QCH_CON_QE_MMC_CARD_HSI2_QCH,
QCH_CON_QE_PCIE_GEN4A_HSI2_QCH,
QCH_CON_QE_PCIE_GEN4B_HSI2_QCH,
QCH_CON_QE_UFS_EMBD_HSI2_QCH,
QCH_CON_SSMT_HSI2_QCH,
QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH,
QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH,
QCH_CON_SYSMMU_HSI2_QCH,
QCH_CON_SYSREG_HSI2_QCH,
QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH,
QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH,
QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH,
QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH,
QCH_CON_UFS_EMBD_QCH,
QCH_CON_UFS_EMBD_QCH_FMP,
QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2,
};
PNAME(mout_hsi2_bus_user_p) = { "oscclk", "dout_cmu_hsi2_bus" };
PNAME(mout_hsi2_mmc_card_user_p) = { "oscclk", "dout_cmu_hsi2_mmc_card" };
PNAME(mout_hsi2_pcie_user_p) = { "oscclk", "dout_cmu_hsi2_pcie" };
PNAME(mout_hsi2_ufs_embd_user_p) = { "oscclk", "dout_cmu_hsi2_ufs_embd" };
static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
MUX(CLK_MOUT_HSI2_BUS_USER, "mout_hsi2_bus_user", mout_hsi2_bus_user_p,
PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 4, 1),
MUX(CLK_MOUT_HSI2_MMC_CARD_USER, "mout_hsi2_mmc_card_user",
mout_hsi2_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
4, 1),
MUX(CLK_MOUT_HSI2_PCIE_USER, "mout_hsi2_pcie_user",
mout_hsi2_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
4, 1),
MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_hsi2_ufs_embd_user",
mout_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
4, 1),
};
static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN,
"gout_hsi2_pcie_gen4_1_pcie_003_phy_refclk_in",
"mout_hsi2_pcie_user",
CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN,
"gout_hsi2_pcie_gen4_1_pcie_004_phy_refclk_in",
"mout_hsi2_pcie_user",
CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK,
"gout_hsi2_ssmt_pcie_ia_gen4a_1_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK,
"gout_hsi2_ssmt_pcie_ia_gen4a_1_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK,
"gout_hsi2_ssmt_pcie_ia_gen4b_1_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK,
"gout_hsi2_ssmt_pcie_ia_gen4b_1_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK,
"gout_hsi2_d_tzpc_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_GPC_HSI2_PCLK,
"gout_hsi2_gpc_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK,
"gout_hsi2_gpio_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 21,
CLK_IGNORE_UNUSED, 0),
/* Disabling this clock makes the system hang. Mark the clock as critical. */
GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK,
"gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
21, CLK_IS_CRITICAL, 0),
/* Disabling this clock makes the system hang. Mark the clock as critical. */
GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK,
"gout_hsi2_lhm_axi_p_hsi2_i_clk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
21, CLK_IS_CRITICAL, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK,
"gout_hsi2_lhs_acel_d_hsi2_i_clk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK,
"gout_hsi2_mmc_card_i_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_MMC_CARD_SDCLKIN,
"gout_hsi2_mmc_card_sdclkin", "mout_hsi2_mmc_card_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG,
"gout_hsi2_pcie_gen4_1_pcie_003_dbi_aclk_ug", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG,
"gout_hsi2_pcie_gen4_1_pcie_003_mstr_aclk_ug",
"mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG,
"gout_hsi2_pcie_gen4_1_pcie_003_slv_aclk_ug", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK,
"gout_hsi2_pcie_gen4_1_pcie_003_i_driver_apb_clk",
"mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG,
"gout_hsi2_pcie_gen4_1_pcie_004_dbi_aclk_ug", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG,
"gout_hsi2_pcie_gen4_1_pcie_004_mstr_aclk_ug",
"mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG,
"gout_hsi2_pcie_gen4_1_pcie_004_slv_aclk_ug", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK,
"gout_hsi2_pcie_gen4_1_pcie_004_i_driver_apb_clk",
"mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK,
"gout_hsi2_pcie_gen4_1_pcs_pma_phy_udbg_i_apb_pclk",
"mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK,
"gout_hsi2_pcie_gen4_1_pcs_pma_pipe_pal_pcie_i_apb_pclk",
"mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK,
"gout_hsi2_pcie_gen4_1_pcs_pma_pciephy210x2_qch_i_apb_pclk",
"mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK,
"gout_hsi2_pcie_ia_gen4a_1_i_clk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK,
"gout_hsi2_pcie_ia_gen4b_1_i_clk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PPMU_HSI2_ACLK,
"gout_hsi2_ppmu_hsi2_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_PPMU_HSI2_PCLK,
"gout_hsi2_ppmu_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK,
"gout_hsi2_qe_mmc_card_hsi2_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK,
"gout_hsi2_qe_mmc_card_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK,
"gout_hsi2_qe_pcie_gen4a_hsi2_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK,
"gout_hsi2_qe_pcie_gen4a_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK,
"gout_hsi2_qe_pcie_gen4b_hsi2_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK,
"gout_hsi2_qe_pcie_gen4b_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK,
"gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK,
"gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK,
"gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK,
"gout_hsi2_clk_hsi2_oscclk_clk", "oscclk",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
21, 0, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK,
"gout_hsi2_ssmt_hsi2_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
21, CLK_IGNORE_UNUSED, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK,
"gout_hsi2_ssmt_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
21, CLK_IGNORE_UNUSED, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2,
"gout_hsi2_sysmmu_hsi2_clk_s2", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK,
"gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK,
"gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK,
"gout_hsi2_uasc_pcie_gen4a_dbi_1_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK,
"gout_hsi2_uasc_pcie_gen4a_slv_1_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK,
"gout_hsi2_uasc_pcie_gen4a_slv_1_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK,
"gout_hsi2_uasc_pcie_gen4b_dbi_1_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK,
"gout_hsi2_uasc_pcie_gen4b_dbi_1_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK,
"gout_hsi2_uasc_pcie_gen4b_slv_1_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK,
"gout_hsi2_uasc_pcie_gen4b_slv_1_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK,
"gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO,
"gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
21, 0, 0),
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK,
"gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
21, 0, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK,
"gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
21, CLK_IGNORE_UNUSED, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK,
"gout_hsi2_xiu_p_hsi2_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
.mux_clks = hsi2_mux_clks,
.nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks),
.gate_clks = hsi2_gate_clks,
.nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks),
.nr_clk_ids = CLKS_NR_HSI2,
.clk_regs = cmu_hsi2_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cmu_hsi2_clk_regs),
.clk_name = "bus",
};
/* ---- CMU_MISC ------------------------------------------------------------ */ /* ---- CMU_MISC ------------------------------------------------------------ */
/* Register Offset definitions for CMU_MISC (0x10010000) */ /* Register Offset definitions for CMU_MISC (0x10010000) */
...@@ -2763,31 +3718,31 @@ static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { ...@@ -2763,31 +3718,31 @@ static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIC0_USI0_UART_USER, MUX(CLK_MOUT_PERIC0_USI0_UART_USER,
"mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI14_USI_USER, nMUX(CLK_MOUT_PERIC0_USI14_USI_USER,
"mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI1_USI_USER, nMUX(CLK_MOUT_PERIC0_USI1_USI_USER,
"mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI2_USI_USER, nMUX(CLK_MOUT_PERIC0_USI2_USI_USER,
"mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI3_USI_USER, nMUX(CLK_MOUT_PERIC0_USI3_USI_USER,
"mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI4_USI_USER, nMUX(CLK_MOUT_PERIC0_USI4_USI_USER,
"mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI5_USI_USER, nMUX(CLK_MOUT_PERIC0_USI5_USI_USER,
"mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI6_USI_USER, nMUX(CLK_MOUT_PERIC0_USI6_USI_USER,
"mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI7_USI_USER, nMUX(CLK_MOUT_PERIC0_USI7_USI_USER,
"mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI8_USI_USER, nMUX(CLK_MOUT_PERIC0_USI8_USI_USER,
"mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1),
}; };
...@@ -2798,33 +3753,42 @@ static const struct samsung_div_clock peric0_div_clks[] __initconst = { ...@@ -2798,33 +3753,42 @@ static const struct samsung_div_clock peric0_div_clks[] __initconst = {
DIV(CLK_DOUT_PERIC0_USI0_UART, DIV(CLK_DOUT_PERIC0_USI0_UART,
"dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4),
DIV(CLK_DOUT_PERIC0_USI14_USI, DIV_F(CLK_DOUT_PERIC0_USI14_USI,
"dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4,
DIV(CLK_DOUT_PERIC0_USI1_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI1_USI,
"dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4,
DIV(CLK_DOUT_PERIC0_USI2_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI2_USI,
"dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4,
DIV(CLK_DOUT_PERIC0_USI3_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI3_USI,
"dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4,
DIV(CLK_DOUT_PERIC0_USI4_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI4_USI,
"dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4,
DIV(CLK_DOUT_PERIC0_USI5_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI5_USI,
"dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4,
DIV(CLK_DOUT_PERIC0_USI6_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI6_USI,
"dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4,
DIV(CLK_DOUT_PERIC0_USI7_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI7_USI,
"dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4,
DIV(CLK_DOUT_PERIC0_USI8_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI8_USI,
"dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
}; };
static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
...@@ -2857,11 +3821,11 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { ...@@ -2857,11 +3821,11 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0,
"gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1,
"gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10,
"gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
...@@ -2889,27 +3853,27 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { ...@@ -2889,27 +3853,27 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2,
"gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3,
"gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4,
"gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5,
"gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6,
"gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7,
"gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8,
"gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
...@@ -2990,7 +3954,7 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { ...@@ -2990,7 +3954,7 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2,
"gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
/* Disabling this clock makes the system hang. Mark the clock as critical. */ /* Disabling this clock makes the system hang. Mark the clock as critical. */
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0,
"gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user",
...@@ -3230,22 +4194,22 @@ static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { ...@@ -3230,22 +4194,22 @@ static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIC1_I3C_USER, MUX(CLK_MOUT_PERIC1_I3C_USER,
"mout_peric1_i3c_user", mout_peric1_nonbususer_p, "mout_peric1_i3c_user", mout_peric1_nonbususer_p,
PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1),
MUX(CLK_MOUT_PERIC1_USI0_USI_USER, nMUX(CLK_MOUT_PERIC1_USI0_USI_USER,
"mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p, "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC1_USI10_USI_USER, nMUX(CLK_MOUT_PERIC1_USI10_USI_USER,
"mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p, "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC1_USI11_USI_USER, nMUX(CLK_MOUT_PERIC1_USI11_USI_USER,
"mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p, "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC1_USI12_USI_USER, nMUX(CLK_MOUT_PERIC1_USI12_USI_USER,
"mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p, "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC1_USI13_USI_USER, nMUX(CLK_MOUT_PERIC1_USI13_USI_USER,
"mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p, "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC1_USI9_USI_USER, nMUX(CLK_MOUT_PERIC1_USI9_USI_USER,
"mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p, "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1), PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
}; };
...@@ -3253,24 +4217,30 @@ static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { ...@@ -3253,24 +4217,30 @@ static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
static const struct samsung_div_clock peric1_div_clks[] __initconst = { static const struct samsung_div_clock peric1_div_clks[] __initconst = {
DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user", DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user",
CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
DIV(CLK_DOUT_PERIC1_USI0_USI, DIV_F(CLK_DOUT_PERIC1_USI0_USI,
"dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user", "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4,
DIV(CLK_DOUT_PERIC1_USI10_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI10_USI,
"dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4,
DIV(CLK_DOUT_PERIC1_USI11_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI11_USI,
"dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4,
DIV(CLK_DOUT_PERIC1_USI12_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI12_USI,
"dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4,
DIV(CLK_DOUT_PERIC1_USI13_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI13_USI,
"dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user", "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4,
DIV(CLK_DOUT_PERIC1_USI9_USI, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI9_USI,
"dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user", "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4), CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
}; };
static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
...@@ -3305,27 +4275,27 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { ...@@ -3305,27 +4275,27 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1, GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,
"gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi", "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2, GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,
"gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi", "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3, GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,
"gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi", "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4, GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,
"gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi", "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5, GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,
"gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi", "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6, GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,
"gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi", "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
21, 0, 0), 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8, GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,
"gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c", "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
...@@ -3426,6 +4396,12 @@ static const struct of_device_id gs101_cmu_of_match[] = { ...@@ -3426,6 +4396,12 @@ static const struct of_device_id gs101_cmu_of_match[] = {
{ {
.compatible = "google,gs101-cmu-apm", .compatible = "google,gs101-cmu-apm",
.data = &apm_cmu_info, .data = &apm_cmu_info,
}, {
.compatible = "google,gs101-cmu-hsi0",
.data = &hsi0_cmu_info,
}, {
.compatible = "google,gs101-cmu-hsi2",
.data = &hsi2_cmu_info,
}, { }, {
.compatible = "google,gs101-cmu-peric0", .compatible = "google,gs101-cmu-peric0",
.data = &peric0_cmu_info, .data = &peric0_cmu_info,
......
drivers/clk/samsung/clk.h
View file @ ce689628
...@@ -133,7 +133,7 @@ struct samsung_mux_clock { ...@@ -133,7 +133,7 @@ struct samsung_mux_clock {
.name = cname, \ .name = cname, \
.parent_names = pnames, \ .parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \ .num_parents = ARRAY_SIZE(pnames), \
.flags = (f) | CLK_SET_RATE_NO_REPARENT, \ .flags = f, \
.offset = o, \ .offset = o, \
.shift = s, \ .shift = s, \
.width = w, \ .width = w, \
...@@ -141,9 +141,16 @@ struct samsung_mux_clock { ...@@ -141,9 +141,16 @@ struct samsung_mux_clock {
} }
#define MUX(_id, cname, pnames, o, s, w) \ #define MUX(_id, cname, pnames, o, s, w) \
__MUX(_id, cname, pnames, o, s, w, 0, 0) __MUX(_id, cname, pnames, o, s, w, CLK_SET_RATE_NO_REPARENT, 0)
#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \ #define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
__MUX(_id, cname, pnames, o, s, w, (f) | CLK_SET_RATE_NO_REPARENT, mf)
/* Used by MUX clocks where reparenting on clock rate change is allowed. */
#define nMUX(_id, cname, pnames, o, s, w) \
__MUX(_id, cname, pnames, o, s, w, 0, 0)
#define nMUX_F(_id, cname, pnames, o, s, w, f, mf) \
__MUX(_id, cname, pnames, o, s, w, f, mf) __MUX(_id, cname, pnames, o, s, w, f, mf)
/** /**
...@@ -330,6 +337,7 @@ struct samsung_clock_reg_cache { ...@@ -330,6 +337,7 @@ struct samsung_clock_reg_cache {
* @suspend_regs: list of clock registers to set before suspend * @suspend_regs: list of clock registers to set before suspend
* @nr_suspend_regs: count of clock registers in @suspend_regs * @nr_suspend_regs: count of clock registers in @suspend_regs
* @clk_name: name of the parent clock needed for CMU register access * @clk_name: name of the parent clock needed for CMU register access
* @manual_plls: Enable manual control for PLL clocks
*/ */
struct samsung_cmu_info { struct samsung_cmu_info {
const struct samsung_pll_clock *pll_clks; const struct samsung_pll_clock *pll_clks;
...@@ -354,6 +362,9 @@ struct samsung_cmu_info { ...@@ -354,6 +362,9 @@ struct samsung_cmu_info {
const struct samsung_clk_reg_dump *suspend_regs; const struct samsung_clk_reg_dump *suspend_regs;
unsigned int nr_suspend_regs; unsigned int nr_suspend_regs;
const char *clk_name; const char *clk_name;
/* ARM64 Exynos CMUs */
bool manual_plls;
}; };
struct samsung_clk_provider *samsung_clk_init(struct device *dev, struct samsung_clk_provider *samsung_clk_init(struct device *dev,
......
include/dt-bindings/clock/google,gs101.h
View file @ ce689628
...@@ -313,6 +313,122 @@ ...@@ -313,6 +313,122 @@
#define CLK_APM_PLL_DIV4_APM 70 #define CLK_APM_PLL_DIV4_APM 70
#define CLK_APM_PLL_DIV16_APM 71 #define CLK_APM_PLL_DIV16_APM 71
/* CMU_HSI0 */
#define CLK_FOUT_USB_PLL 1
#define CLK_MOUT_PLL_USB 2
#define CLK_MOUT_HSI0_ALT_USER 3
#define CLK_MOUT_HSI0_BUS_USER 4
#define CLK_MOUT_HSI0_DPGTC_USER 5
#define CLK_MOUT_HSI0_TCXO_USER 6
#define CLK_MOUT_HSI0_USB20_USER 7
#define CLK_MOUT_HSI0_USB31DRD_USER 8
#define CLK_MOUT_HSI0_USBDPDBG_USER 9
#define CLK_MOUT_HSI0_BUS 10
#define CLK_MOUT_HSI0_USB20_REF 11
#define CLK_MOUT_HSI0_USB31DRD 12
#define CLK_DOUT_HSI0_USB31DRD 13
#define CLK_GOUT_HSI0_PCLK 14
#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26 15
#define CLK_GOUT_HSI0_CLK_HSI0_ALT 16
#define CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK 17
#define CLK_GOUT_HSI0_DP_LINK_I_PCLK 18
#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 19
#define CLK_GOUT_HSI0_ETR_MIU_I_ACLK 20
#define CLK_GOUT_HSI0_ETR_MIU_I_PCLK 21
#define CLK_GOUT_HSI0_GPC_HSI0_PCLK 22
#define CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK 23
#define CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK 24
#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK 25
#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK 26
#define CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK 27
#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK 28
#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK 29
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK 30
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK 31
#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 32
#define CLK_GOUT_HSI0_SSMT_USB_ACLK 33
#define CLK_GOUT_HSI0_SSMT_USB_PCLK 34
#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 35
#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 36
#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK 37
#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK 38
#define CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK 39
#define CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK 40
#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 41
#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 42
#define CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26 43
#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40 44
#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL 45
#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK 46
#define CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK 47
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK 48
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK 49
#define CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK 50
#define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK 51
#define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK 52
/* CMU_HSI2 */
#define CLK_MOUT_HSI2_BUS_USER 1
#define CLK_MOUT_HSI2_MMC_CARD_USER 2
#define CLK_MOUT_HSI2_PCIE_USER 3
#define CLK_MOUT_HSI2_UFS_EMBD_USER 4
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN 5
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN 6
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK 7
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK 8
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK 9
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK 10
#define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK 11
#define CLK_GOUT_HSI2_GPC_HSI2_PCLK 12
#define CLK_GOUT_HSI2_GPIO_HSI2_PCLK 13
#define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK 14
#define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK 15
#define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK 16
#define CLK_GOUT_HSI2_MMC_CARD_I_ACLK 17
#define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN 18
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG 19
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG 20
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG 21
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK 22
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG 23
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG 24
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG 25
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK 26
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK 27
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK 28
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK 29
#define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK 30
#define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK 31
#define CLK_GOUT_HSI2_PPMU_HSI2_ACLK 32
#define CLK_GOUT_HSI2_PPMU_HSI2_PCLK 33
#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK 34
#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK 35
#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK 36
#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK 37
#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK 38
#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK 39
#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK 40
#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK 41
#define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK 42
#define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK 43
#define CLK_GOUT_HSI2_SSMT_HSI2_ACLK 44
#define CLK_GOUT_HSI2_SSMT_HSI2_PCLK 45
#define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 46
#define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK 47
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK 48
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK 49
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK 50
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK 51
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK 52
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK 53
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK 54
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK 55
#define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK 56
#define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO 57
#define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK 58
#define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK 59
#define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK 60
/* CMU_MISC */ /* CMU_MISC */
#define CLK_MOUT_MISC_BUS_USER 1 #define CLK_MOUT_MISC_BUS_USER 1
#define CLK_MOUT_MISC_SSS_USER 2 #define CLK_MOUT_MISC_SSS_USER 2
......
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