Commit ce9564cf authored by Chris Morgan's avatar Chris Morgan Committed by Robert Foss

drm/bridge: chrontel-ch7033: Add byteswap order setting

Add the option to set the byteswap order in the devicetree. For the
official HDMI DIP for the NTC CHIP the byteswap order needs to be
RGB, however the driver sets it as BGR. With this patch the driver
will remain at BGR unless manually specified via devicetree.
Signed-off-by: default avatarChris Morgan <macromorgan@hotmail.com>
Reviewed-by: default avatarRobert Foss <robert.foss@linaro.org>
Signed-off-by: default avatarRobert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220902153906.31000-3-macroalpha82@gmail.com
parent a4be7143
...@@ -68,6 +68,7 @@ enum { ...@@ -68,6 +68,7 @@ enum {
BYTE_SWAP_GBR = 3, BYTE_SWAP_GBR = 3,
BYTE_SWAP_BRG = 4, BYTE_SWAP_BRG = 4,
BYTE_SWAP_BGR = 5, BYTE_SWAP_BGR = 5,
BYTE_SWAP_MAX = 6,
}; };
/* Page 0, Register 0x19 */ /* Page 0, Register 0x19 */
...@@ -355,6 +356,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge, ...@@ -355,6 +356,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
int hsynclen = mode->hsync_end - mode->hsync_start; int hsynclen = mode->hsync_end - mode->hsync_start;
int vbporch = mode->vsync_start - mode->vdisplay; int vbporch = mode->vsync_start - mode->vdisplay;
int vsynclen = mode->vsync_end - mode->vsync_start; int vsynclen = mode->vsync_end - mode->vsync_start;
u8 byte_swap;
int ret;
/* /*
* Page 4 * Page 4
...@@ -398,7 +401,15 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge, ...@@ -398,7 +401,15 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
regmap_write(priv->regmap, 0x15, vbporch); regmap_write(priv->regmap, 0x15, vbporch);
regmap_write(priv->regmap, 0x16, vsynclen); regmap_write(priv->regmap, 0x16, vsynclen);
/* Input color swap. */ /* Input color swap. Byte order is optional and will default to
* BYTE_SWAP_BGR to preserve backwards compatibility with existing
* driver.
*/
ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap",
&byte_swap);
if (!ret && byte_swap < BYTE_SWAP_MAX)
regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap);
else
regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
/* Input clock and sync polarity. */ /* Input clock and sync polarity. */
......
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