Commit ced9541c authored by Mark Brown's avatar Mark Brown

Merge remote-tracking branches 'asoc/topic/sunxi', 'asoc/topic/symmetry',...

Merge remote-tracking branches 'asoc/topic/sunxi', 'asoc/topic/symmetry', 'asoc/topic/tas5720', 'asoc/topic/tas6424' and 'asoc/topic/tfa9879' into asoc-next
......@@ -8,6 +8,7 @@ Required properties:
- compatible: should be one of the following:
- "allwinner,sun4i-a10-i2s"
- "allwinner,sun6i-a31-i2s"
- "allwinner,sun8i-a83t-i2s"
- "allwinner,sun8i-h3-i2s"
- reg: physical base address of the controller and length of memory mapped
region.
......@@ -23,6 +24,7 @@ Required properties:
Required properties for the following compatibles:
- "allwinner,sun6i-a31-i2s"
- "allwinner,sun8i-a83t-i2s"
- "allwinner,sun8i-h3-i2s"
- resets: phandle to the reset line for this codec
......
......@@ -6,10 +6,12 @@ audio playback. For more product information please see the links below:
http://www.ti.com/product/TAS5720L
http://www.ti.com/product/TAS5720M
http://www.ti.com/product/TAS5722L
Required properties:
- compatible : "ti,tas5720"
- compatible : "ti,tas5720",
"ti,tas5722"
- reg : I2C slave address
- dvdd-supply : phandle to a 3.3-V supply for the digital circuitry
- pvdd-supply : phandle to a supply used for the Class-D amp and the analog
......
......@@ -6,15 +6,15 @@ Required properties:
- reg : the I2C address of the device
- #sound-dai-cells : must be 0.
Example:
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: tfa9879@6c {
amp: amp@6c {
#sound-dai-cells = <0>;
compatible = "nxp,tfa9879";
reg = <0x6c>;
......
Texas Instruments TAS6424 Quad-Channel Audio amplifier
The TAS6424 serial control bus communicates through I2C protocols.
Required properties:
- compatible: "ti,tas6424" - TAS6424
- reg: I2C slave address
- sound-dai-cells: must be equal to 0
Example:
tas6424: tas6424@6a {
compatible = "ti,tas6424";
reg = <0x6a>;
#sound-dai-cells = <0>;
};
For more product information please see the link below:
http://www.ti.com/product/TAS6424-Q1
......@@ -9803,6 +9803,7 @@ NXP TFA9879 DRIVER
M: Peter Rosin <peda@axentia.se>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/sound/tfa9879.txt
F: sound/soc/codecs/tfa9879*
NXP-NCI NFC DRIVER
......
......@@ -296,9 +296,6 @@ struct snd_soc_dai {
/* DAI runtime info */
unsigned int capture_active:1; /* stream is in use */
unsigned int playback_active:1; /* stream is in use */
unsigned int symmetric_rates:1;
unsigned int symmetric_channels:1;
unsigned int symmetric_samplebits:1;
unsigned int probed:1;
unsigned int active;
......
......@@ -150,6 +150,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_TAS5086 if I2C
select SND_SOC_TAS571X if I2C
select SND_SOC_TAS5720 if I2C
select SND_SOC_TAS6424 if I2C
select SND_SOC_TFA9879 if I2C
select SND_SOC_TLV320AIC23_I2C if I2C
select SND_SOC_TLV320AIC23_SPI if SPI_MASTER
......@@ -901,6 +902,13 @@ config SND_SOC_TAS5720
Enable support for Texas Instruments TAS5720L/M high-efficiency mono
Class-D audio power amplifiers.
config SND_SOC_TAS6424
tristate "Texas Instruments TAS6424 Quad-Channel Audio amplifier"
depends on I2C
help
Enable support for Texas Instruments TAS6424 high-efficiency
digital input quad-channel Class-D audio power amplifiers.
config SND_SOC_TFA9879
tristate "NXP Semiconductors TFA9879 amplifier"
depends on I2C
......
......@@ -159,6 +159,7 @@ snd-soc-sti-sas-objs := sti-sas.o
snd-soc-tas5086-objs := tas5086.o
snd-soc-tas571x-objs := tas571x.o
snd-soc-tas5720-objs := tas5720.o
snd-soc-tas6424-objs := tas6424.o
snd-soc-tfa9879-objs := tfa9879.o
snd-soc-tlv320aic23-objs := tlv320aic23.o
snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o
......@@ -402,6 +403,7 @@ obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o
obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
obj-$(CONFIG_SND_SOC_TAS571X) += snd-soc-tas571x.o
obj-$(CONFIG_SND_SOC_TAS5720) += snd-soc-tas5720.o
obj-$(CONFIG_SND_SOC_TAS6424) += snd-soc-tas6424.o
obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o
obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o
......
......@@ -36,6 +36,11 @@
/* Define how often to check (and clear) the fault status register (in ms) */
#define TAS5720_FAULT_CHECK_INTERVAL 200
enum tas572x_type {
TAS5720,
TAS5722,
};
static const char * const tas5720_supply_names[] = {
"dvdd", /* Digital power supply. Connect to 3.3-V supply. */
"pvdd", /* Class-D amp and analog power supply (connected). */
......@@ -47,6 +52,7 @@ struct tas5720_data {
struct snd_soc_codec *codec;
struct regmap *regmap;
struct i2c_client *tas5720_client;
enum tas572x_type devtype;
struct regulator_bulk_data supplies[TAS5720_NUM_SUPPLIES];
struct delayed_work fault_check_work;
unsigned int last_fault;
......@@ -264,7 +270,7 @@ static void tas5720_fault_check_work(struct work_struct *work)
static int tas5720_codec_probe(struct snd_soc_codec *codec)
{
struct tas5720_data *tas5720 = snd_soc_codec_get_drvdata(codec);
unsigned int device_id;
unsigned int device_id, expected_device_id;
int ret;
tas5720->codec = codec;
......@@ -276,6 +282,11 @@ static int tas5720_codec_probe(struct snd_soc_codec *codec)
return ret;
}
/*
* Take a liberal approach to checking the device ID to allow the
* driver to be used even if the device ID does not match, however
* issue a warning if there is a mismatch.
*/
ret = regmap_read(tas5720->regmap, TAS5720_DEVICE_ID_REG, &device_id);
if (ret < 0) {
dev_err(codec->dev, "failed to read device ID register: %d\n",
......@@ -283,13 +294,22 @@ static int tas5720_codec_probe(struct snd_soc_codec *codec)
goto probe_fail;
}
if (device_id != TAS5720_DEVICE_ID) {
dev_err(codec->dev, "wrong device ID. expected: %u read: %u\n",
TAS5720_DEVICE_ID, device_id);
ret = -ENODEV;
goto probe_fail;
switch (tas5720->devtype) {
case TAS5720:
expected_device_id = TAS5720_DEVICE_ID;
break;
case TAS5722:
expected_device_id = TAS5722_DEVICE_ID;
break;
default:
dev_err(codec->dev, "unexpected private driver data\n");
return -EINVAL;
}
if (device_id != expected_device_id)
dev_warn(codec->dev, "wrong device ID. expected: %u read: %u\n",
expected_device_id, device_id);
/* Set device to mute */
ret = snd_soc_update_bits(codec, TAS5720_DIGITAL_CTRL2_REG,
TAS5720_MUTE, TAS5720_MUTE);
......@@ -446,6 +466,15 @@ static const struct regmap_config tas5720_regmap_config = {
.volatile_reg = tas5720_is_volatile_reg,
};
static const struct regmap_config tas5722_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TAS5722_MAX_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = tas5720_is_volatile_reg,
};
/*
* DAC analog gain. There are four discrete values to select from, ranging
* from 19.2 dB to 26.3dB.
......@@ -544,6 +573,7 @@ static int tas5720_probe(struct i2c_client *client,
{
struct device *dev = &client->dev;
struct tas5720_data *data;
const struct regmap_config *regmap_config;
int ret;
int i;
......@@ -552,7 +582,20 @@ static int tas5720_probe(struct i2c_client *client,
return -ENOMEM;
data->tas5720_client = client;
data->regmap = devm_regmap_init_i2c(client, &tas5720_regmap_config);
data->devtype = id->driver_data;
switch (id->driver_data) {
case TAS5720:
regmap_config = &tas5720_regmap_config;
break;
case TAS5722:
regmap_config = &tas5722_regmap_config;
break;
default:
dev_err(dev, "unexpected private driver data\n");
return -EINVAL;
}
data->regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(data->regmap)) {
ret = PTR_ERR(data->regmap);
dev_err(dev, "failed to allocate register map: %d\n", ret);
......@@ -592,7 +635,8 @@ static int tas5720_remove(struct i2c_client *client)
}
static const struct i2c_device_id tas5720_id[] = {
{ "tas5720", 0 },
{ "tas5720", TAS5720 },
{ "tas5722", TAS5722 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tas5720_id);
......@@ -600,6 +644,7 @@ MODULE_DEVICE_TABLE(i2c, tas5720_id);
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id tas5720_of_match[] = {
{ .compatible = "ti,tas5720", },
{ .compatible = "ti,tas5722", },
{ },
};
MODULE_DEVICE_TABLE(of, tas5720_of_match);
......
......@@ -30,8 +30,14 @@
#define TAS5720_DIGITAL_CLIP1_REG 0x11
#define TAS5720_MAX_REG TAS5720_DIGITAL_CLIP1_REG
/* Additional TAS5722-specific Registers */
#define TAS5722_DIGITAL_CTRL2_REG 0x13
#define TAS5722_ANALOG_CTRL2_REG 0x14
#define TAS5722_MAX_REG TAS5722_ANALOG_CTRL2_REG
/* TAS5720_DEVICE_ID_REG */
#define TAS5720_DEVICE_ID 0x01
#define TAS5722_DEVICE_ID 0x12
/* TAS5720_POWER_CTRL_REG */
#define TAS5720_DIG_CLIP_MASK GENMASK(7, 2)
......@@ -51,6 +57,7 @@
#define TAS5720_SAIF_FORMAT_MASK GENMASK(2, 0)
/* TAS5720_DIGITAL_CTRL2_REG */
#define TAS5722_VOL_RAMP_RATE BIT(6)
#define TAS5720_MUTE BIT(4)
#define TAS5720_TDM_SLOT_SEL_MASK GENMASK(2, 0)
......@@ -87,4 +94,28 @@
#define TAS5720_CLIP1_MASK GENMASK(7, 2)
#define TAS5720_CLIP1_SHIFT (0x2)
/* TAS5722_DIGITAL_CTRL2_REG */
#define TAS5722_HPF_3_7HZ (0x0 << 5)
#define TAS5722_HPF_7_4HZ (0x1 << 5)
#define TAS5722_HPF_14_9HZ (0x2 << 5)
#define TAS5722_HPF_29_7HZ (0x3 << 5)
#define TAS5722_HPF_59_4HZ (0x4 << 5)
#define TAS5722_HPF_118_4HZ (0x5 << 5)
#define TAS5722_HPF_235_0HZ (0x6 << 5)
#define TAS5722_HPF_463_2HZ (0x7 << 5)
#define TAS5722_HPF_MASK GENMASK(7, 5)
#define TAS5722_AUTO_SLEEP_OFF (0x0 << 3)
#define TAS5722_AUTO_SLEEP_1024LR (0x1 << 3)
#define TAS5722_AUTO_SLEEP_65536LR (0x2 << 3)
#define TAS5722_AUTO_SLEEP_262144LR (0x3 << 3)
#define TAS5722_AUTO_SLEEP_MASK GENMASK(4, 3)
#define TAS5722_TDM_SLOT_16B BIT(2)
#define TAS5722_MCLK_PIN_CFG BIT(1)
#define TAS5722_VOL_CONTROL_LSB BIT(0)
/* TAS5722_ANALOG_CTRL2_REG */
#define TAS5722_FAULTZ_PU BIT(3)
#define TAS5722_VREG_LVL BIT(2)
#define TAS5722_PWR_TUNE BIT(0)
#endif /* __TAS5720_H__ */
This diff is collapsed.
// SPDX-License-Identifier: GPL-2.0
/*
* ALSA SoC Texas Instruments TAS6424 Quad-Channel Audio Amplifier
*
* Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
* Author: Andreas Dannenberg <dannenberg@ti.com>
* Andrew F. Davis <afd@ti.com>
*/
#ifndef __TAS6424_H__
#define __TAS6424_H__
#define TAS6424_RATES (SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_96000)
#define TAS6424_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
/* Register Address Map */
#define TAS6424_MODE_CTRL 0x00
#define TAS6424_MISC_CTRL1 0x01
#define TAS6424_MISC_CTRL2 0x02
#define TAS6424_SAP_CTRL 0x03
#define TAS6424_CH_STATE_CTRL 0x04
#define TAS6424_CH1_VOL_CTRL 0x05
#define TAS6424_CH2_VOL_CTRL 0x06
#define TAS6424_CH3_VOL_CTRL 0x07
#define TAS6424_CH4_VOL_CTRL 0x08
#define TAS6424_DC_DIAG_CTRL1 0x09
#define TAS6424_DC_DIAG_CTRL2 0x0a
#define TAS6424_DC_DIAG_CTRL3 0x0b
#define TAS6424_DC_LOAD_DIAG_REP12 0x0c
#define TAS6424_DC_LOAD_DIAG_REP34 0x0d
#define TAS6424_DC_LOAD_DIAG_REPLO 0x0e
#define TAS6424_CHANNEL_STATE 0x0f
#define TAS6424_CHANNEL_FAULT 0x10
#define TAS6424_GLOB_FAULT1 0x11
#define TAS6424_GLOB_FAULT2 0x12
#define TAS6424_WARN 0x13
#define TAS6424_PIN_CTRL 0x14
#define TAS6424_AC_DIAG_CTRL1 0x15
#define TAS6424_AC_DIAG_CTRL2 0x16
#define TAS6424_AC_LOAD_DIAG_REP1 0x17
#define TAS6424_AC_LOAD_DIAG_REP2 0x18
#define TAS6424_AC_LOAD_DIAG_REP3 0x19
#define TAS6424_AC_LOAD_DIAG_REP4 0x1a
#define TAS6424_MISC_CTRL3 0x21
#define TAS6424_CLIP_CTRL 0x22
#define TAS6424_CLIP_WINDOW 0x23
#define TAS6424_CLIP_WARN 0x24
#define TAS6424_CBC_STAT 0x25
#define TAS6424_MISC_CTRL4 0x26
#define TAS6424_MAX TAS6424_MISC_CTRL4
/* TAS6424_MODE_CTRL_REG */
#define TAS6424_RESET BIT(7)
/* TAS6424_SAP_CTRL_REG */
#define TAS6424_SAP_RATE_MASK GENMASK(7, 6)
#define TAS6424_SAP_RATE_44100 (0x00 << 6)
#define TAS6424_SAP_RATE_48000 (0x01 << 6)
#define TAS6424_SAP_RATE_96000 (0x02 << 6)
#define TAS6424_SAP_TDM_SLOT_LAST BIT(5)
#define TAS6424_SAP_TDM_SLOT_SZ_16 BIT(4)
#define TAS6424_SAP_TDM_SLOT_SWAP BIT(3)
#define TAS6424_SAP_FMT_MASK GENMASK(2, 0)
#define TAS6424_SAP_RIGHTJ_24 (0x00 << 0)
#define TAS6424_SAP_RIGHTJ_20 (0x01 << 0)
#define TAS6424_SAP_RIGHTJ_18 (0x02 << 0)
#define TAS6424_SAP_RIGHTJ_16 (0x03 << 0)
#define TAS6424_SAP_I2S (0x04 << 0)
#define TAS6424_SAP_LEFTJ (0x05 << 0)
#define TAS6424_SAP_DSP (0x06 << 0)
/* TAS6424_CH_STATE_CTRL_REG */
#define TAS6424_CH1_STATE_MASK GENMASK(7, 6)
#define TAS6424_CH1_STATE_PLAY (0x00 << 6)
#define TAS6424_CH1_STATE_HIZ (0x01 << 6)
#define TAS6424_CH1_STATE_MUTE (0x02 << 6)
#define TAS6424_CH1_STATE_DIAG (0x03 << 6)
#define TAS6424_CH2_STATE_MASK GENMASK(5, 4)
#define TAS6424_CH2_STATE_PLAY (0x00 << 4)
#define TAS6424_CH2_STATE_HIZ (0x01 << 4)
#define TAS6424_CH2_STATE_MUTE (0x02 << 4)
#define TAS6424_CH2_STATE_DIAG (0x03 << 4)
#define TAS6424_CH3_STATE_MASK GENMASK(3, 2)
#define TAS6424_CH3_STATE_PLAY (0x00 << 2)
#define TAS6424_CH3_STATE_HIZ (0x01 << 2)
#define TAS6424_CH3_STATE_MUTE (0x02 << 2)
#define TAS6424_CH3_STATE_DIAG (0x03 << 2)
#define TAS6424_CH4_STATE_MASK GENMASK(1, 0)
#define TAS6424_CH4_STATE_PLAY (0x00 << 0)
#define TAS6424_CH4_STATE_HIZ (0x01 << 0)
#define TAS6424_CH4_STATE_MUTE (0x02 << 0)
#define TAS6424_CH4_STATE_DIAG (0x03 << 0)
#define TAS6424_ALL_STATE_PLAY (TAS6424_CH1_STATE_PLAY | \
TAS6424_CH2_STATE_PLAY | \
TAS6424_CH3_STATE_PLAY | \
TAS6424_CH4_STATE_PLAY)
#define TAS6424_ALL_STATE_HIZ (TAS6424_CH1_STATE_HIZ | \
TAS6424_CH2_STATE_HIZ | \
TAS6424_CH3_STATE_HIZ | \
TAS6424_CH4_STATE_HIZ)
#define TAS6424_ALL_STATE_MUTE (TAS6424_CH1_STATE_MUTE | \
TAS6424_CH2_STATE_MUTE | \
TAS6424_CH3_STATE_MUTE | \
TAS6424_CH4_STATE_MUTE)
#define TAS6424_ALL_STATE_DIAG (TAS6424_CH1_STATE_DIAG | \
TAS6424_CH2_STATE_DIAG | \
TAS6424_CH3_STATE_DIAG | \
TAS6424_CH4_STATE_DIAG)
/* TAS6424_GLOB_FAULT1_REG */
#define TAS6424_FAULT_CLOCK BIT(4)
#define TAS6424_FAULT_PVDD_OV BIT(3)
#define TAS6424_FAULT_VBAT_OV BIT(2)
#define TAS6424_FAULT_PVDD_UV BIT(1)
#define TAS6424_FAULT_VBAT_UV BIT(0)
/* TAS6424_GLOB_FAULT2_REG */
#define TAS6424_FAULT_OTSD BIT(4)
#define TAS6424_FAULT_OTSD_CH1 BIT(3)
#define TAS6424_FAULT_OTSD_CH2 BIT(2)
#define TAS6424_FAULT_OTSD_CH3 BIT(1)
#define TAS6424_FAULT_OTSD_CH4 BIT(0)
/* TAS6424_WARN_REG */
#define TAS6424_WARN_VDD_UV BIT(6)
#define TAS6424_WARN_VDD_POR BIT(5)
#define TAS6424_WARN_VDD_OTW BIT(4)
#define TAS6424_WARN_VDD_OTW_CH1 BIT(3)
#define TAS6424_WARN_VDD_OTW_CH2 BIT(2)
#define TAS6424_WARN_VDD_OTW_CH3 BIT(1)
#define TAS6424_WARN_VDD_OTW_CH4 BIT(0)
/* TAS6424_MISC_CTRL3_REG */
#define TAS6424_CLEAR_FAULT BIT(7)
#define TAS6424_PBTL_CH_SEL BIT(6)
#define TAS6424_MASK_CBC_WARN BIT(5)
#define TAS6424_MASK_VDD_UV BIT(4)
#define TAS6424_OTSD_AUTO_RECOVERY BIT(3)
#endif /* __TAS6424_H__ */
......@@ -316,6 +316,7 @@ static const struct of_device_id tfa9879_of_match[] = {
{ .compatible = "nxp,tfa9879", },
{ }
};
MODULE_DEVICE_TABLE(of, tfa9879_of_match);
static struct i2c_driver tfa9879_i2c_driver = {
.driver = {
......
......@@ -98,6 +98,8 @@ struct wm2200_priv {
int rev;
int sysclk;
unsigned int symmetric_rates:1;
};
#define WM2200_DSP_RANGE_BASE (WM2200_MAX_REGISTER + 1)
......@@ -1550,7 +1552,7 @@ static const struct snd_soc_dapm_route wm2200_dapm_routes[] = {
static int wm2200_probe(struct snd_soc_codec *codec)
{
struct wm2200_priv *wm2200 = dev_get_drvdata(codec->dev);
struct wm2200_priv *wm2200 = snd_soc_codec_get_drvdata(codec);
int ret;
wm2200->codec = codec;
......@@ -1758,7 +1760,7 @@ static int wm2200_hw_params(struct snd_pcm_substream *substream,
lrclk = bclk_rates[bclk] / params_rate(params);
dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
dai->symmetric_rates)
wm2200->symmetric_rates)
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_7,
WM2200_AIF1RX_BCPF_MASK, lrclk);
else
......@@ -2059,13 +2061,14 @@ static int wm2200_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
static int wm2200_dai_probe(struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct wm2200_priv *wm2200 = snd_soc_codec_get_drvdata(codec);
unsigned int val = 0;
int ret;
ret = snd_soc_read(codec, WM2200_GPIO_CTRL_1);
if (ret >= 0) {
if ((ret & WM2200_GP1_FN_MASK) != 0) {
dai->symmetric_rates = true;
wm2200->symmetric_rates = true;
val = WM2200_AIF1TX_LRCLK_SRC;
}
} else {
......
......@@ -590,12 +590,28 @@ static int sun4i_codec_hw_params(struct snd_pcm_substream *substream,
hwrate);
}
static unsigned int sun4i_codec_src_rates[] = {
8000, 11025, 12000, 16000, 22050, 24000, 32000,
44100, 48000, 96000, 192000
};
static struct snd_pcm_hw_constraint_list sun4i_codec_constraints = {
.count = ARRAY_SIZE(sun4i_codec_src_rates),
.list = sun4i_codec_src_rates,
};
static int sun4i_codec_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &sun4i_codec_constraints);
/*
* Stop issuing DRQ when we have room for less than 16 samples
* in our TX FIFO
......@@ -633,9 +649,7 @@ static struct snd_soc_dai_driver sun4i_codec_dai = {
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
.rates = SNDRV_PCM_RATE_8000_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.sig_bits = 24,
......@@ -645,11 +659,8 @@ static struct snd_soc_dai_driver sun4i_codec_dai = {
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
.rates = SNDRV_PCM_RATE_8000_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000 |
SNDRV_PCM_RATE_KNOT,
.rate_max = 48000,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.sig_bits = 24,
......@@ -1128,7 +1139,7 @@ static const struct snd_soc_component_driver sun4i_codec_component = {
.name = "sun4i-codec",
};
#define SUN4I_CODEC_RATES SNDRV_PCM_RATE_8000_192000
#define SUN4I_CODEC_RATES SNDRV_PCM_RATE_CONTINUOUS
#define SUN4I_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
......
......@@ -921,6 +921,23 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
};
static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.has_slave_select_bit = true,
.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
};
static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
......@@ -1144,6 +1161,10 @@ static const struct of_device_id sun4i_i2s_match[] = {
.compatible = "allwinner,sun6i-a31-i2s",
.data = &sun6i_a31_i2s_quirks,
},
{
.compatible = "allwinner,sun8i-a83t-i2s",
.data = &sun8i_a83t_i2s_quirks,
},
{
.compatible = "allwinner,sun8i-h3-i2s",
.data = &sun8i_h3_i2s_quirks,
......
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