Commit cfb5d7b7 authored by David S. Miller's avatar David S. Miller

Merge branch 'ravb-gigabit'

Biju Das says:

====================
Fillup stubs for Gigabit Ethernet driver support

The DMAC and EMAC blocks of Gigabit Ethernet IP found on RZ/G2L SoC are
similar to the R-Car Ethernet AVB IP.

The Gigabit Ethernet IP consists of Ethernet controller (E-MAC), Internal
TCP/IP Offload Engine (TOE)  and Dedicated Direct memory access controller
(DMAC).

With a few changes in the driver we can support both IPs.

This patch series is for adding Gigabit ethernet driver support to RZ/G2L SoC.

The number of patches after incorporatng RFC review comments is 18.
So split the patches into 2 patchsets (10 + 8).

This series is the second patchset, aims to fillup all the stubs for the
Gigabit Ethernet driver.

This patch series depend upon [1]
[1] https://lore.kernel.org/linux-renesas-soc/20211001150636.7500-1-biju.das.jz@bp.renesas.com/T/#t

RFC->V1:
 * used rx_max_buf_size instead of rx_2k_buffers feature bit.
 * renamed "rgeth" to "gbeth".
 * renamed ravb_rx_ring_free to ravb_rx_ring_free_rcar
 * renamed ravb_rx_ring_format to ravb_rx_ring_format_rcar
 * renamed ravb_alloc_rx_desc to ravb_alloc_rx_desc_rcar
 * renamed ravb_rcar_rx to ravb_rx_rcar
 * Added Sergey's Rb tag for patch #6.
 * Moved CSR0 initialization to patch #8.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 6b7b0c30 16a23519
...@@ -81,6 +81,7 @@ enum ravb_reg { ...@@ -81,6 +81,7 @@ enum ravb_reg {
RQC3 = 0x00A0, RQC3 = 0x00A0,
RQC4 = 0x00A4, RQC4 = 0x00A4,
RPC = 0x00B0, RPC = 0x00B0,
RTC = 0x00B4, /* R-Car Gen3 and RZ/G2L only */
UFCW = 0x00BC, UFCW = 0x00BC,
UFCS = 0x00C0, UFCS = 0x00C0,
UFCV0 = 0x00C4, UFCV0 = 0x00C4,
...@@ -187,13 +188,14 @@ enum ravb_reg { ...@@ -187,13 +188,14 @@ enum ravb_reg {
PIR = 0x0520, PIR = 0x0520,
PSR = 0x0528, PSR = 0x0528,
PIPR = 0x052c, PIPR = 0x052c,
CXR31 = 0x0530, /* RZ/G2L only */
MPR = 0x0558, MPR = 0x0558,
PFTCR = 0x055c, PFTCR = 0x055c,
PFRCR = 0x0560, PFRCR = 0x0560,
GECMR = 0x05b0, GECMR = 0x05b0,
MAHR = 0x05c0, MAHR = 0x05c0,
MALR = 0x05c8, MALR = 0x05c8,
TROCR = 0x0700, /* R-Car Gen3 only */ TROCR = 0x0700, /* R-Car Gen3 and RZ/G2L only */
CEFCR = 0x0740, CEFCR = 0x0740,
FRECR = 0x0748, FRECR = 0x0748,
TSFRCR = 0x0750, TSFRCR = 0x0750,
...@@ -810,10 +812,11 @@ enum ECMR_BIT { ...@@ -810,10 +812,11 @@ enum ECMR_BIT {
ECMR_TXF = 0x00010000, /* Documented for R-Car Gen3 only */ ECMR_TXF = 0x00010000, /* Documented for R-Car Gen3 only */
ECMR_RXF = 0x00020000, ECMR_RXF = 0x00020000,
ECMR_PFR = 0x00040000, ECMR_PFR = 0x00040000,
ECMR_ZPF = 0x00080000, /* Documented for R-Car Gen3 only */ ECMR_ZPF = 0x00080000, /* Documented for R-Car Gen3 and RZ/G2L */
ECMR_RZPF = 0x00100000, ECMR_RZPF = 0x00100000,
ECMR_DPAD = 0x00200000, ECMR_DPAD = 0x00200000,
ECMR_RCSC = 0x00800000, ECMR_RCSC = 0x00800000,
ECMR_RCPT = 0x02000000, /* Documented for RZ/G2L only */
ECMR_TRCCM = 0x04000000, ECMR_TRCCM = 0x04000000,
}; };
...@@ -823,6 +826,7 @@ enum ECSR_BIT { ...@@ -823,6 +826,7 @@ enum ECSR_BIT {
ECSR_MPD = 0x00000002, ECSR_MPD = 0x00000002,
ECSR_LCHNG = 0x00000004, ECSR_LCHNG = 0x00000004,
ECSR_PHYI = 0x00000008, ECSR_PHYI = 0x00000008,
ECSR_PFRI = 0x00000010,
}; };
/* ECSIPR */ /* ECSIPR */
...@@ -860,6 +864,10 @@ enum GECMR_BIT { ...@@ -860,6 +864,10 @@ enum GECMR_BIT {
GECMR_SPEED = 0x00000001, GECMR_SPEED = 0x00000001,
GECMR_SPEED_100 = 0x00000000, GECMR_SPEED_100 = 0x00000000,
GECMR_SPEED_1000 = 0x00000001, GECMR_SPEED_1000 = 0x00000001,
GBETH_GECMR_SPEED = 0x00000030,
GBETH_GECMR_SPEED_10 = 0x00000000,
GBETH_GECMR_SPEED_100 = 0x00000010,
GBETH_GECMR_SPEED_1000 = 0x00000020,
}; };
/* The Ethernet AVB descriptor definitions. */ /* The Ethernet AVB descriptor definitions. */
...@@ -949,6 +957,11 @@ enum RAVB_QUEUE { ...@@ -949,6 +957,11 @@ enum RAVB_QUEUE {
RAVB_NC, /* Network Control Queue */ RAVB_NC, /* Network Control Queue */
}; };
enum CXR31_BIT {
CXR31_SEL_LINK0 = 0x00000001,
CXR31_SEL_LINK1 = 0x00000008,
};
#define DBAT_ENTRY_NUM 22 #define DBAT_ENTRY_NUM 22
#define RX_QUEUE_OFFSET 4 #define RX_QUEUE_OFFSET 4
#define NUM_RX_QUEUE 2 #define NUM_RX_QUEUE 2
...@@ -956,6 +969,8 @@ enum RAVB_QUEUE { ...@@ -956,6 +969,8 @@ enum RAVB_QUEUE {
#define RX_BUF_SZ (2048 - ETH_FCS_LEN + sizeof(__sum16)) #define RX_BUF_SZ (2048 - ETH_FCS_LEN + sizeof(__sum16))
#define GBETH_RX_BUFF_MAX 8192
struct ravb_tstamp_skb { struct ravb_tstamp_skb {
struct list_head list; struct list_head list;
struct sk_buff *skb; struct sk_buff *skb;
...@@ -985,8 +1000,8 @@ struct ravb_hw_info { ...@@ -985,8 +1000,8 @@ struct ravb_hw_info {
void *(*alloc_rx_desc)(struct net_device *ndev, int q); void *(*alloc_rx_desc)(struct net_device *ndev, int q);
bool (*receive)(struct net_device *ndev, int *quota, int q); bool (*receive)(struct net_device *ndev, int *quota, int q);
void (*set_rate)(struct net_device *ndev); void (*set_rate)(struct net_device *ndev);
int (*set_rx_csum_feature)(struct net_device *ndev, netdev_features_t features); int (*set_feature)(struct net_device *ndev, netdev_features_t features);
void (*dmac_init)(struct net_device *ndev); int (*dmac_init)(struct net_device *ndev);
void (*emac_init)(struct net_device *ndev); void (*emac_init)(struct net_device *ndev);
const char (*gstrings_stats)[ETH_GSTRING_LEN]; const char (*gstrings_stats)[ETH_GSTRING_LEN];
size_t gstrings_size; size_t gstrings_size;
...@@ -994,14 +1009,18 @@ struct ravb_hw_info { ...@@ -994,14 +1009,18 @@ struct ravb_hw_info {
netdev_features_t net_features; netdev_features_t net_features;
int stats_len; int stats_len;
size_t max_rx_len; size_t max_rx_len;
u32 tsrq;
unsigned aligned_tx: 1; unsigned aligned_tx: 1;
/* hardware features */ /* hardware features */
unsigned internal_delay:1; /* AVB-DMAC has internal delays */ unsigned internal_delay:1; /* AVB-DMAC has internal delays */
unsigned tx_counters:1; /* E-MAC has TX counters */ unsigned tx_counters:1; /* E-MAC has TX counters */
unsigned multi_irqs:1; /* AVB-DMAC and E-MAC has multiple irqs */ unsigned multi_irqs:1; /* AVB-DMAC and E-MAC has multiple irqs */
unsigned no_ptp_cfg_active:1; /* AVB-DMAC does not support gPTP active in config mode */ unsigned gptp:1; /* AVB-DMAC has gPTP support */
unsigned ptp_cfg_active:1; /* AVB-DMAC has gPTP support active in config mode */ unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */
unsigned nc_queue:1; /* AVB-DMAC has NC queue */
unsigned magic_pkt:1; /* E-MAC supports magic packet detection */
unsigned half_duplex:1; /* E-MAC supports half duplex mode */
}; };
struct ravb_private { struct ravb_private {
...@@ -1056,6 +1075,8 @@ struct ravb_private { ...@@ -1056,6 +1075,8 @@ struct ravb_private {
unsigned rgmii_override:1; /* Deprecated rgmii-*id behavior */ unsigned rgmii_override:1; /* Deprecated rgmii-*id behavior */
unsigned int num_tx_desc; /* TX descriptors per packet */ unsigned int num_tx_desc; /* TX descriptors per packet */
int duplex;
const struct ravb_hw_info *info; const struct ravb_hw_info *info;
struct reset_control *rstc; struct reset_control *rstc;
}; };
......
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