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Commit d08a0d41 authored by Mark Brown's avatar Mark Brown
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TAS2764 fixes/extensions 

Merge series from Martin Povišer <povik+lin@cutebit.org>:

First three patches are fixes analogical to those recently done to
the TAS2770 driver.
Link: https://lore.kernel.org/asahi/20220808141246.5749-1-povik+lin@cutebit.org/T/#t

The latter two add IRQ handler to log faults and expose a new control.
parents e0550fff aca86ec9
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Showing with 152 additions and 52 deletions
sound/soc/codecs/tas2764.c
View file @ d08a0d41
......@@ -31,11 +31,66 @@ struct tas2764_priv {
struct gpio_desc *sdz_gpio;
struct regmap *regmap;
struct device *dev;
int irq;
int v_sense_slot;
int i_sense_slot;
bool dac_powered;
bool unmuted;
};
static const char *tas2764_int_ltch0_msgs[8] = {
"fault: over temperature", /* INT_LTCH0 & BIT(0) */
"fault: over current",
"fault: bad TDM clock",
"limiter active",
"fault: PVDD below limiter inflection point",
"fault: limiter max attenuation",
"fault: BOP infinite hold",
"fault: BOP mute", /* INT_LTCH0 & BIT(7) */
};
static const unsigned int tas2764_int_readout_regs[6] = {
TAS2764_INT_LTCH0,
TAS2764_INT_LTCH1,
TAS2764_INT_LTCH1_0,
TAS2764_INT_LTCH2,
TAS2764_INT_LTCH3,
TAS2764_INT_LTCH4,
};
static irqreturn_t tas2764_irq(int irq, void *data)
{
struct tas2764_priv *tas2764 = data;
u8 latched[6] = {0, 0, 0, 0, 0, 0};
int ret = IRQ_NONE;
int i;
for (i = 0; i < ARRAY_SIZE(latched); i++)
latched[i] = snd_soc_component_read(tas2764->component,
tas2764_int_readout_regs[i]);
for (i = 0; i < 8; i++) {
if (latched[0] & BIT(i)) {
dev_crit_ratelimited(tas2764->dev, "%s\n",
tas2764_int_ltch0_msgs[i]);
ret = IRQ_HANDLED;
}
}
if (latched[0]) {
dev_err_ratelimited(tas2764->dev, "other context to the fault: %02x,%02x,%02x,%02x,%02x",
latched[1], latched[2], latched[3], latched[4], latched[5]);
snd_soc_component_update_bits(tas2764->component,
TAS2764_INT_CLK_CFG,
TAS2764_INT_CLK_CFG_IRQZ_CLR,
TAS2764_INT_CLK_CFG_IRQZ_CLR);
}
return ret;
}
static void tas2764_reset(struct tas2764_priv *tas2764)
{
if (tas2764->reset_gpio) {
......@@ -50,34 +105,22 @@ static void tas2764_reset(struct tas2764_priv *tas2764)
usleep_range(1000, 2000);
}
static int tas2764_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
static int tas2764_update_pwr_ctrl(struct tas2764_priv *tas2764)
{
struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
struct snd_soc_component *component = tas2764->component;
unsigned int val;
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK,
TAS2764_PWR_CTRL_ACTIVE);
break;
case SND_SOC_BIAS_STANDBY:
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK,
TAS2764_PWR_CTRL_MUTE);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK,
TAS2764_PWR_CTRL_SHUTDOWN);
break;
if (tas2764->dac_powered)
val = tas2764->unmuted ?
TAS2764_PWR_CTRL_ACTIVE : TAS2764_PWR_CTRL_MUTE;
else
val = TAS2764_PWR_CTRL_SHUTDOWN;
default:
dev_err(tas2764->dev,
"wrong power level setting %d\n", level);
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK, val);
if (ret < 0)
return ret;
return 0;
}
......@@ -114,9 +157,7 @@ static int tas2764_codec_resume(struct snd_soc_component *component)
usleep_range(1000, 2000);
}
ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK,
TAS2764_PWR_CTRL_ACTIVE);
ret = tas2764_update_pwr_ctrl(tas2764);
if (ret < 0)
return ret;
......@@ -150,14 +191,12 @@ static int tas2764_dac_event(struct snd_soc_dapm_widget *w,
switch (event) {
case SND_SOC_DAPM_POST_PMU:
ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK,
TAS2764_PWR_CTRL_MUTE);
tas2764->dac_powered = true;
ret = tas2764_update_pwr_ctrl(tas2764);
break;
case SND_SOC_DAPM_PRE_PMD:
ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK,
TAS2764_PWR_CTRL_SHUTDOWN);
tas2764->dac_powered = false;
ret = tas2764_update_pwr_ctrl(tas2764);
break;
default:
dev_err(tas2764->dev, "Unsupported event\n");
......@@ -202,17 +241,11 @@ static const struct snd_soc_dapm_route tas2764_audio_map[] = {
static int tas2764_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
int ret;
ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK,
mute ? TAS2764_PWR_CTRL_MUTE : 0);
if (ret < 0)
return ret;
struct tas2764_priv *tas2764 =
snd_soc_component_get_drvdata(dai->component);
return 0;
tas2764->unmuted = !mute;
return tas2764_update_pwr_ctrl(tas2764);
}
static int tas2764_set_bitwidth(struct tas2764_priv *tas2764, int bitwidth)
......@@ -485,7 +518,7 @@ static struct snd_soc_dai_driver tas2764_dai_driver[] = {
.id = 0,
.playback = {
.stream_name = "ASI1 Playback",
.channels_min = 2,
.channels_min = 1,
.channels_max = 2,
.rates = TAS2764_RATES,
.formats = TAS2764_FORMATS,
......@@ -516,6 +549,34 @@ static int tas2764_codec_probe(struct snd_soc_component *component)
tas2764_reset(tas2764);
if (tas2764->irq) {
ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK0, 0xff);
if (ret < 0)
return ret;
ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK1, 0xff);
if (ret < 0)
return ret;
ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK2, 0xff);
if (ret < 0)
return ret;
ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK3, 0xff);
if (ret < 0)
return ret;
ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK4, 0xff);
if (ret < 0)
return ret;
ret = devm_request_threaded_irq(tas2764->dev, tas2764->irq, NULL, tas2764_irq,
IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
"tas2764", tas2764);
if (ret)
dev_warn(tas2764->dev, "failed to request IRQ: %d\n", ret);
}
ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG5,
TAS2764_TDM_CFG5_VSNS_ENABLE, 0);
if (ret < 0)
......@@ -526,30 +587,33 @@ static int tas2764_codec_probe(struct snd_soc_component *component)
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK,
TAS2764_PWR_CTRL_MUTE);
if (ret < 0)
return ret;
return 0;
}
static DECLARE_TLV_DB_SCALE(tas2764_digital_tlv, 1100, 50, 0);
static DECLARE_TLV_DB_SCALE(tas2764_playback_volume, -10050, 50, 1);
static const char * const tas2764_hpf_texts[] = {
"Disabled", "2 Hz", "50 Hz", "100 Hz", "200 Hz",
"400 Hz", "800 Hz"
};
static SOC_ENUM_SINGLE_DECL(
tas2764_hpf_enum, TAS2764_DC_BLK0,
TAS2764_DC_BLK0_HPF_FREQ_PB_SHIFT, tas2764_hpf_texts);
static const struct snd_kcontrol_new tas2764_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", TAS2764_DVC, 0,
TAS2764_DVC_MAX, 1, tas2764_playback_volume),
SOC_SINGLE_TLV("Amp Gain Volume", TAS2764_CHNL_0, 1, 0x14, 0,
tas2764_digital_tlv),
SOC_ENUM("HPF Corner Frequency", tas2764_hpf_enum),
};
static const struct snd_soc_component_driver soc_component_driver_tas2764 = {
.probe = tas2764_codec_probe,
.suspend = tas2764_codec_suspend,
.resume = tas2764_codec_resume,
.set_bias_level = tas2764_set_bias_level,
.controls = tas2764_snd_controls,
.num_controls = ARRAY_SIZE(tas2764_snd_controls),
.dapm_widgets = tas2764_dapm_widgets,
......@@ -585,9 +649,21 @@ static const struct regmap_range_cfg tas2764_regmap_ranges[] = {
},
};
static bool tas2764_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case TAS2764_INT_LTCH0 ... TAS2764_INT_LTCH4:
case TAS2764_INT_CLK_CFG:
return true;
default:
return false;
}
}
static const struct regmap_config tas2764_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = tas2764_volatile_register,
.reg_defaults = tas2764_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas2764_reg_defaults),
.cache_type = REGCACHE_RBTREE,
......@@ -641,6 +717,7 @@ static int tas2764_i2c_probe(struct i2c_client *client)
return -ENOMEM;
tas2764->dev = &client->dev;
tas2764->irq = client->irq;
i2c_set_clientdata(client, tas2764);
dev_set_drvdata(&client->dev, tas2764);
......
sound/soc/codecs/tas2764.h
View file @ d08a0d41
......@@ -33,6 +33,10 @@
#define TAS2764_VSENSE_POWER_EN 3
#define TAS2764_ISENSE_POWER_EN 4
/* DC Blocker Control */
#define TAS2764_DC_BLK0 TAS2764_REG(0x0, 0x04)
#define TAS2764_DC_BLK0_HPF_FREQ_PB_SHIFT 0
/* Digital Volume Control */
#define TAS2764_DVC TAS2764_REG(0X0, 0x1a)
#define TAS2764_DVC_MAX 0xc9
......@@ -87,4 +91,23 @@
#define TAS2764_TDM_CFG6_ISNS_ENABLE BIT(6)
#define TAS2764_TDM_CFG6_50_MASK GENMASK(5, 0)
/* Interrupt Masks */
#define TAS2764_INT_MASK0 TAS2764_REG(0x0, 0x3b)
#define TAS2764_INT_MASK1 TAS2764_REG(0x0, 0x3c)
#define TAS2764_INT_MASK2 TAS2764_REG(0x0, 0x40)
#define TAS2764_INT_MASK3 TAS2764_REG(0x0, 0x41)
#define TAS2764_INT_MASK4 TAS2764_REG(0x0, 0x3d)
/* Latched Fault Registers */
#define TAS2764_INT_LTCH0 TAS2764_REG(0x0, 0x49)
#define TAS2764_INT_LTCH1 TAS2764_REG(0x0, 0x4a)
#define TAS2764_INT_LTCH1_0 TAS2764_REG(0x0, 0x4b)
#define TAS2764_INT_LTCH2 TAS2764_REG(0x0, 0x4f)
#define TAS2764_INT_LTCH3 TAS2764_REG(0x0, 0x50)
#define TAS2764_INT_LTCH4 TAS2764_REG(0x0, 0x51)
/* Clock/IRQ Settings */
#define TAS2764_INT_CLK_CFG TAS2764_REG(0x0, 0x5c)
#define TAS2764_INT_CLK_CFG_IRQZ_CLR BIT(2)
#endif /* __TAS2764__ */
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