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Kirill Smelkov
linux
Commits
d1b610e5
Commit
d1b610e5
authored
Oct 21, 2004
by
Jeff Garzik
Browse files
Options
Browse Files
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Plain Diff
Merge pobox.com:/garz/repo/netdev-2.6/b44
into pobox.com:/garz/repo/net-drivers-2.6
parents
7a150f8b
5950ddc1
Changes
2
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Showing
2 changed files
with
88 additions
and
156 deletions
+88
-156
drivers/net/b44.c
drivers/net/b44.c
+83
-48
drivers/net/b44.h
drivers/net/b44.h
+5
-108
No files found.
drivers/net/b44.c
View file @
d1b610e5
...
...
@@ -8,6 +8,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/ethtool.h>
...
...
@@ -27,8 +28,8 @@
#define DRV_MODULE_NAME "b44"
#define PFX DRV_MODULE_NAME ": "
#define DRV_MODULE_VERSION "0.9
4
"
#define DRV_MODULE_RELDATE "
May 4
, 2004"
#define DRV_MODULE_VERSION "0.9
5
"
#define DRV_MODULE_RELDATE "
Aug 3
, 2004"
#define B44_DEF_MSG_ENABLE \
(NETIF_MSG_DRV | \
...
...
@@ -57,6 +58,7 @@
#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
B44_TX_RING_SIZE)
#define B44_DMA_MASK 0x3fffffff
#define TX_RING_GAP(BP) \
(B44_TX_RING_SIZE - (BP)->tx_pending)
...
...
@@ -67,6 +69,7 @@
#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
#define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
#define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
/* minimum number of free TX descriptors required to wake up TX process */
#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
...
...
@@ -74,13 +77,13 @@
static
char
version
[]
__devinitdata
=
DRV_MODULE_NAME
".c:v"
DRV_MODULE_VERSION
" ("
DRV_MODULE_RELDATE
")
\n
"
;
MODULE_AUTHOR
(
"
David S. Miller (davem@redhat.com)
"
);
MODULE_AUTHOR
(
"
Florian Schirmer, Pekka Pietikainen, David S. Miller
"
);
MODULE_DESCRIPTION
(
"Broadcom 4400 10/100 PCI ethernet driver"
);
MODULE_LICENSE
(
"GPL"
);
MODULE_PARM
(
b44_debug
,
"i"
);
MODULE_PARM_DESC
(
b44_debug
,
"B44 bitmapped debugging message enable value"
);
static
int
b44_debug
=
-
1
;
/* -1 == use B44_DEF_MSG_ENABLE as value */
module_param
(
b44_debug
,
int
,
0
);
MODULE_PARM_DESC
(
b44_debug
,
"B44 bitmapped debugging message enable value"
);
static
struct
pci_device_id
b44_pci_tbl
[]
=
{
{
PCI_VENDOR_ID_BROADCOM
,
PCI_DEVICE_ID_BCM4401
,
...
...
@@ -97,6 +100,10 @@ MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
static
void
b44_halt
(
struct
b44
*
);
static
void
b44_init_rings
(
struct
b44
*
);
static
void
b44_init_hw
(
struct
b44
*
);
static
int
b44_poll
(
struct
net_device
*
dev
,
int
*
budget
);
#ifdef CONFIG_NET_POLL_CONTROLLER
static
void
b44_poll_controller
(
struct
net_device
*
dev
);
#endif
static
inline
unsigned
long
br32
(
const
struct
b44
*
bp
,
unsigned
long
reg
)
{
...
...
@@ -141,41 +148,8 @@ static int b44_wait_bit(struct b44 *bp, unsigned long reg,
* interrupts disabled.
*/
#define SBID_SDRAM 0
#define SBID_PCI_MEM 1
#define SBID_PCI_CFG 2
#define SBID_PCI_DMA 3
#define SBID_SDRAM_SWAPPED 4
#define SBID_ENUM 5
#define SBID_REG_SDRAM 6
#define SBID_REG_ILINE20 7
#define SBID_REG_EMAC 8
#define SBID_REG_CODEC 9
#define SBID_REG_USB 10
#define SBID_REG_PCI 11
#define SBID_REG_MIPS 12
#define SBID_REG_EXTIF 13
#define SBID_EXTIF 14
#define SBID_EJTAG 15
#define SBID_MAX 16
static
u32
ssb_get_addr
(
struct
b44
*
bp
,
u32
id
,
u32
instance
)
{
switch
(
id
)
{
case
SBID_PCI_DMA
:
return
0x40000000
;
case
SBID_ENUM
:
return
0x18000000
;
case
SBID_REG_EMAC
:
return
0x18000000
;
case
SBID_REG_CODEC
:
return
0x18001000
;
case
SBID_REG_PCI
:
return
0x18002000
;
default:
return
0
;
};
}
#define SB_PCI_DMA 0x40000000
/* Client Mode PCI memory access space (1 GB) */
#define BCM4400_PCI_CORE_ADDR 0x18002000
/* Address of PCI core on BCM4400 cards */
static
u32
ssb_get_core_rev
(
struct
b44
*
bp
)
{
...
...
@@ -187,8 +161,7 @@ static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
u32
bar_orig
,
pci_rev
,
val
;
pci_read_config_dword
(
bp
->
pdev
,
SSB_BAR0_WIN
,
&
bar_orig
);
pci_write_config_dword
(
bp
->
pdev
,
SSB_BAR0_WIN
,
ssb_get_addr
(
bp
,
SBID_REG_PCI
,
0
));
pci_write_config_dword
(
bp
->
pdev
,
SSB_BAR0_WIN
,
BCM4400_PCI_CORE_ADDR
);
pci_rev
=
ssb_get_core_rev
(
bp
);
val
=
br32
(
bp
,
B44_SBINTVEC
);
...
...
@@ -649,10 +622,30 @@ static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
if
(
skb
==
NULL
)
return
-
ENOMEM
;
skb
->
dev
=
bp
->
dev
;
mapping
=
pci_map_single
(
bp
->
pdev
,
skb
->
data
,
RX_PKT_BUF_SZ
,
PCI_DMA_FROMDEVICE
);
/* Hardware bug work-around, the chip is unable to do PCI DMA
to/from anything above 1GB :-( */
if
(
mapping
+
RX_PKT_BUF_SZ
>
B44_DMA_MASK
)
{
/* Sigh... */
pci_unmap_single
(
bp
->
pdev
,
mapping
,
RX_PKT_BUF_SZ
,
PCI_DMA_FROMDEVICE
);
dev_kfree_skb_any
(
skb
);
skb
=
__dev_alloc_skb
(
RX_PKT_BUF_SZ
,
GFP_DMA
);
if
(
skb
==
NULL
)
return
-
ENOMEM
;
mapping
=
pci_map_single
(
bp
->
pdev
,
skb
->
data
,
RX_PKT_BUF_SZ
,
PCI_DMA_FROMDEVICE
);
if
(
mapping
+
RX_PKT_BUF_SZ
>
B44_DMA_MASK
)
{
pci_unmap_single
(
bp
->
pdev
,
mapping
,
RX_PKT_BUF_SZ
,
PCI_DMA_FROMDEVICE
);
dev_kfree_skb_any
(
skb
);
return
-
ENOMEM
;
}
}
skb
->
dev
=
bp
->
dev
;
skb_reserve
(
skb
,
bp
->
rx_offset
);
rh
=
(
struct
rx_header
*
)
...
...
@@ -930,6 +923,12 @@ static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
entry
=
bp
->
tx_prod
;
mapping
=
pci_map_single
(
bp
->
pdev
,
skb
->
data
,
len
,
PCI_DMA_TODEVICE
);
if
(
mapping
+
len
>
B44_DMA_MASK
)
{
/* Chip can't handle DMA to/from >1GB, use bounce buffer */
pci_unmap_single
(
bp
->
pdev
,
mapping
,
len
,
PCI_DMA_TODEVICE
);
memcpy
(
bp
->
tx_bufs
+
entry
*
TX_PKT_BUF_SZ
,
skb
->
data
,
skb
->
len
);
mapping
=
pci_map_single
(
bp
->
pdev
,
bp
->
tx_bufs
+
entry
*
TX_PKT_BUF_SZ
,
len
,
PCI_DMA_TODEVICE
);
}
bp
->
tx_buffers
[
entry
].
skb
=
skb
;
pci_unmap_addr_set
(
&
bp
->
tx_buffers
[
entry
],
mapping
,
mapping
);
...
...
@@ -1077,6 +1076,11 @@ static void b44_free_consistent(struct b44 *bp)
bp
->
tx_ring
,
bp
->
tx_ring_dma
);
bp
->
tx_ring
=
NULL
;
}
if
(
bp
->
tx_bufs
)
{
pci_free_consistent
(
bp
->
pdev
,
B44_TX_RING_SIZE
*
TX_PKT_BUF_SZ
,
bp
->
tx_bufs
,
bp
->
tx_bufs_dma
);
bp
->
tx_bufs
=
NULL
;
}
}
/*
...
...
@@ -1099,6 +1103,12 @@ static int b44_alloc_consistent(struct b44 *bp)
goto
out_err
;
memset
(
bp
->
tx_buffers
,
0
,
size
);
size
=
B44_TX_RING_SIZE
*
TX_PKT_BUF_SZ
;
bp
->
tx_bufs
=
pci_alloc_consistent
(
bp
->
pdev
,
size
,
&
bp
->
tx_bufs_dma
);
if
(
!
bp
->
tx_bufs
)
goto
out_err
;
memset
(
bp
->
tx_bufs
,
0
,
size
);
size
=
DMA_TABLE_BYTES
;
bp
->
rx_ring
=
pci_alloc_consistent
(
bp
->
pdev
,
size
,
&
bp
->
rx_ring_dma
);
if
(
!
bp
->
rx_ring
)
...
...
@@ -1297,6 +1307,19 @@ static int b44_open(struct net_device *dev)
}
#endif
#ifdef CONFIG_NET_POLL_CONTROLLER
/*
* Polling receive - used by netconsole and other diagnostic tools
* to allow network i/o with interrupts disabled.
*/
static
void
b44_poll_controller
(
struct
net_device
*
dev
)
{
disable_irq
(
dev
->
irq
);
b44_interrupt
(
dev
->
irq
,
dev
,
NULL
);
enable_irq
(
dev
->
irq
);
}
#endif
static
int
b44_close
(
struct
net_device
*
dev
)
{
struct
b44
*
bp
=
netdev_priv
(
dev
);
...
...
@@ -1358,7 +1381,10 @@ static struct net_device_stats *b44_get_stats(struct net_device *dev)
hwstat
->
rx_symbol_errs
);
nstat
->
tx_aborted_errors
=
hwstat
->
tx_underruns
;
#if 0
/* Carrier lost counter seems to be broken for some devices */
nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
#endif
return
nstat
;
}
...
...
@@ -1684,7 +1710,6 @@ static int __devinit b44_get_invariants(struct b44 *bp)
bp
->
dev
->
dev_addr
[
5
]
=
eeprom
[
82
];
bp
->
phy_addr
=
eeprom
[
90
]
&
0x1f
;
bp
->
mdc_port
=
(
eeprom
[
90
]
>>
14
)
&
0x1
;
/* With this, plus the rx_header prepended to the data by the
* hardware, we'll land the ethernet header on a 2-byte boundary.
...
...
@@ -1694,7 +1719,7 @@ static int __devinit b44_get_invariants(struct b44 *bp)
bp
->
imask
=
IMASK_DEF
;
bp
->
core_unit
=
ssb_core_unit
(
bp
);
bp
->
dma_offset
=
ssb_get_addr
(
bp
,
SBID_PCI_DMA
,
0
)
;
bp
->
dma_offset
=
SB_PCI_DMA
;
/* XXX - really required?
bp->flags |= B44_FLAG_BUGGY_TXPTR;
...
...
@@ -1738,7 +1763,14 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
pci_set_master
(
pdev
);
err
=
pci_set_dma_mask
(
pdev
,
(
u64
)
0xffffffff
);
err
=
pci_set_dma_mask
(
pdev
,
(
u64
)
B44_DMA_MASK
);
if
(
err
)
{
printk
(
KERN_ERR
PFX
"No usable DMA configuration, "
"aborting.
\n
"
);
goto
err_out_free_res
;
}
err
=
pci_set_consistent_dma_mask
(
pdev
,
(
u64
)
B44_DMA_MASK
);
if
(
err
)
{
printk
(
KERN_ERR
PFX
"No usable DMA configuration, "
"aborting.
\n
"
);
...
...
@@ -1793,6 +1825,9 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
dev
->
poll
=
b44_poll
;
dev
->
weight
=
64
;
dev
->
watchdog_timeo
=
B44_TX_TIMEOUT
;
#ifdef CONFIG_NET_POLL_CONTROLLER
dev
->
poll_controller
=
b44_poll_controller
;
#endif
dev
->
change_mtu
=
b44_change_mtu
;
dev
->
irq
=
pdev
->
irq
;
SET_ETHTOOL_OPS
(
dev
,
&
b44_ethtool_ops
);
...
...
@@ -1870,7 +1905,7 @@ static void __devexit b44_remove_one(struct pci_dev *pdev)
static
int
b44_suspend
(
struct
pci_dev
*
pdev
,
u32
state
)
{
struct
net_device
*
dev
=
pci_get_drvdata
(
pdev
);
struct
b44
*
bp
=
dev
->
priv
;
struct
b44
*
bp
=
netdev_priv
(
dev
)
;
if
(
!
netif_running
(
dev
))
return
0
;
...
...
@@ -1891,7 +1926,7 @@ static int b44_suspend(struct pci_dev *pdev, u32 state)
static
int
b44_resume
(
struct
pci_dev
*
pdev
)
{
struct
net_device
*
dev
=
pci_get_drvdata
(
pdev
);
struct
b44
*
bp
=
dev
->
priv
;
struct
b44
*
bp
=
netdev_priv
(
dev
)
;
pci_restore_state
(
pdev
);
...
...
drivers/net/b44.h
View file @
d1b610e5
...
...
@@ -223,21 +223,8 @@
#define B44_RX_SYM 0x05D0UL
/* MIB RX Symbol Errors */
#define B44_RX_PAUSE 0x05D4UL
/* MIB RX Pause Packets */
#define B44_RX_NPAUSE 0x05D8UL
/* MIB RX Non-Pause Packets */
#define B44_SBIPSFLAG 0x0F08UL
/* SB Initiator Port OCP Slave Flag */
#define SBIPSFLAG_IMASK1 0x0000003f
/* Which sbflags --> mips interrupt 1 */
#define SBIPSFLAG_ISHIFT1 0
#define SBIPSFLAG_IMASK2 0x00003f00
/* Which sbflags --> mips interrupt 2 */
#define SBIPSFLAG_ISHIFT2 8
#define SBIPSFLAG_IMASK3 0x003f0000
/* Which sbflags --> mips interrupt 3 */
#define SBIPSFLAG_ISHIFT3 16
#define SBIPSFLAG_IMASK4 0x3f000000
/* Which sbflags --> mips interrupt 4 */
#define SBIPSFLAG_ISHIFT4 24
#define B44_SBTPSFLAG 0x0F18UL
/* SB Target Port OCP Slave Flag */
#define SBTPS_NUM0_MASK 0x0000003f
#define SBTPS_F0EN0 0x00000040
#define B44_SBADMATCH3 0x0F60UL
/* SB Address Match 3 */
#define B44_SBADMATCH2 0x0F68UL
/* SB Address Match 2 */
#define B44_SBADMATCH1 0x0F70UL
/* SB Address Match 1 */
/* Silicon backplane register definitions */
#define B44_SBIMSTATE 0x0F90UL
/* SB Initiator Agent State */
#define SBIMSTATE_PC 0x0000000f
/* Pipe Count */
#define SBIMSTATE_AP_MASK 0x00000030
/* Arbitration Priority */
...
...
@@ -269,86 +256,6 @@
#define SBTMSHIGH_GCR 0x20000000
/* Gated Clock Request */
#define SBTMSHIGH_BISTF 0x40000000
/* BIST Failed */
#define SBTMSHIGH_BISTD 0x80000000
/* BIST Done */
#define B44_SBBWA0 0x0FA0UL
/* SB Bandwidth Allocation Table 0 */
#define SBBWA0_TAB0_MASK 0x0000ffff
/* Lookup Table 0 */
#define SBBWA0_TAB0_SHIFT 0
#define SBBWA0_TAB1_MASK 0xffff0000
/* Lookup Table 0 */
#define SBBWA0_TAB1_SHIFT 16
#define B44_SBIMCFGLOW 0x0FA8UL
/* SB Initiator Configuration Low */
#define SBIMCFGLOW_STO_MASK 0x00000003
/* Service Timeout */
#define SBIMCFGLOW_RTO_MASK 0x00000030
/* Request Timeout */
#define SBIMCFGLOW_RTO_SHIFT 4
#define SBIMCFGLOW_CID_MASK 0x00ff0000
/* Connection ID */
#define SBIMCFGLOW_CID_SHIFT 16
#define B44_SBIMCFGHIGH 0x0FACUL
/* SB Initiator Configuration High */
#define SBIMCFGHIGH_IEM_MASK 0x0000000c
/* Inband Error Mode */
#define SBIMCFGHIGH_TEM_MASK 0x00000030
/* Timeout Error Mode */
#define SBIMCFGHIGH_TEM_SHIFT 4
#define SBIMCFGHIGH_BEM_MASK 0x000000c0
/* Bus Error Mode */
#define SBIMCFGHIGH_BEM_SHIFT 6
#define B44_SBADMATCH0 0x0FB0UL
/* SB Address Match 0 */
#define SBADMATCH0_TYPE_MASK 0x00000003
/* Address Type */
#define SBADMATCH0_AD64 0x00000004
/* Reserved */
#define SBADMATCH0_AI0_MASK 0x000000f8
/* Type0 Size */
#define SBADMATCH0_AI0_SHIFT 3
#define SBADMATCH0_AI1_MASK 0x000001f8
/* Type1 Size */
#define SBADMATCH0_AI1_SHIFT 3
#define SBADMATCH0_AI2_MASK 0x000001f8
/* Type2 Size */
#define SBADMATCH0_AI2_SHIFT 3
#define SBADMATCH0_ADEN 0x00000400
/* Enable */
#define SBADMATCH0_ADNEG 0x00000800
/* Negative Decode */
#define SBADMATCH0_BS0_MASK 0xffffff00
/* Type0 Base Address */
#define SBADMATCH0_BS0_SHIFT 8
#define SBADMATCH0_BS1_MASK 0xfffff000
/* Type1 Base Address */
#define SBADMATCH0_BS1_SHIFT 12
#define SBADMATCH0_BS2_MASK 0xffff0000
/* Type2 Base Address */
#define SBADMATCH0_BS2_SHIFT 16
#define B44_SBTMCFGLOW 0x0FB8UL
/* SB Target Configuration Low */
#define SBTMCFGLOW_CD_MASK 0x000000ff
/* Clock Divide Mask */
#define SBTMCFGLOW_CO_MASK 0x0000f800
/* Clock Offset Mask */
#define SBTMCFGLOW_CO_SHIFT 11
#define SBTMCFGLOW_IF_MASK 0x00fc0000
/* Interrupt Flags Mask */
#define SBTMCFGLOW_IF_SHIFT 18
#define SBTMCFGLOW_IM_MASK 0x03000000
/* Interrupt Mode Mask */
#define SBTMCFGLOW_IM_SHIFT 24
#define B44_SBTMCFGHIGH 0x0FBCUL
/* SB Target Configuration High */
#define SBTMCFGHIGH_BM_MASK 0x00000003
/* Busy Mode */
#define SBTMCFGHIGH_RM_MASK 0x0000000C
/* Retry Mode */
#define SBTMCFGHIGH_RM_SHIFT 2
#define SBTMCFGHIGH_SM_MASK 0x00000030
/* Stop Mode */
#define SBTMCFGHIGH_SM_SHIFT 4
#define SBTMCFGHIGH_EM_MASK 0x00000300
/* Error Mode */
#define SBTMCFGHIGH_EM_SHIFT 8
#define SBTMCFGHIGH_IM_MASK 0x00000c00
/* Interrupt Mode */
#define SBTMCFGHIGH_IM_SHIFT 10
#define B44_SBBCFG 0x0FC0UL
/* SB Broadcast Configuration */
#define SBBCFG_LAT_MASK 0x00000003
/* SB Latency */
#define SBBCFG_MAX0_MASK 0x000f0000
/* MAX Counter 0 */
#define SBBCFG_MAX0_SHIFT 16
#define SBBCFG_MAX1_MASK 0x00f00000
/* MAX Counter 1 */
#define SBBCFG_MAX1_SHIFT 20
#define B44_SBBSTATE 0x0FC8UL
/* SB Broadcast State */
#define SBBSTATE_SRD 0x00000001
/* ST Reg Disable */
#define SBBSTATE_HRD 0x00000002
/* Hold Reg Disable */
#define B44_SBACTCNFG 0x0FD8UL
/* SB Activate Configuration */
#define B44_SBFLAGST 0x0FE8UL
/* SB Current SBFLAGS */
#define B44_SBIDLOW 0x0FF8UL
/* SB Identification Low */
#define SBIDLOW_CS_MASK 0x00000003
/* Config Space Mask */
#define SBIDLOW_AR_MASK 0x00000038
/* Num Address Ranges Supported */
#define SBIDLOW_AR_SHIFT 3
#define SBIDLOW_SYNCH 0x00000040
/* Sync */
#define SBIDLOW_INIT 0x00000080
/* Initiator */
#define SBIDLOW_MINLAT_MASK 0x00000f00
/* Minimum Backplane Latency */
#define SBIDLOW_MINLAT_SHIFT 8
#define SBIDLOW_MAXLAT_MASK 0x0000f000
/* Maximum Backplane Latency */
#define SBIDLOW_MAXLAT_SHIFT 12
#define SBIDLOW_FIRST 0x00010000
/* This Initiator is First */
#define SBIDLOW_CW_MASK 0x000c0000
/* Cycle Counter Width */
#define SBIDLOW_CW_SHIFT 18
#define SBIDLOW_TP_MASK 0x00f00000
/* Target Ports */
#define SBIDLOW_TP_SHIFT 20
#define SBIDLOW_IP_MASK 0x0f000000
/* Initiator Ports */
#define SBIDLOW_IP_SHIFT 24
#define B44_SBIDHIGH 0x0FFCUL
/* SB Identification High */
#define SBIDHIGH_RC_MASK 0x0000000f
/* Revision Code */
#define SBIDHIGH_CC_MASK 0x0000fff0
/* Core Code */
...
...
@@ -356,23 +263,13 @@
#define SBIDHIGH_VC_MASK 0xffff0000
/* Vendor Code */
#define SBIDHIGH_VC_SHIFT 16
#define CORE_CODE_ILINE20 0x801
#define CORE_CODE_SDRAM 0x803
#define CORE_CODE_PCI 0x804
#define CORE_CODE_MIPS 0x805
#define CORE_CODE_ENET 0x806
#define CORE_CODE_CODEC 0x807
#define CORE_CODE_USB 0x808
#define CORE_CODE_ILINE100 0x80a
#define CORE_CODE_EXTIF 0x811
/* SSB PCI config space registers. */
#define SSB_BAR0_WIN 0x80
#define SSB_BAR1_WIN 0x84
#define SSB_SPROM_CONTROL 0x88
#define SSB_BAR1_CONTROL 0x8c
/* SSB core and h
so
t control registers. */
/* SSB core and h
os
t control registers. */
#define SSB_CONTROL 0x0000UL
#define SSB_ARBCONTROL 0x0010UL
#define SSB_ISTAT 0x0020UL
...
...
@@ -500,6 +397,7 @@ struct b44 {
struct
ring_info
*
rx_buffers
;
struct
ring_info
*
tx_buffers
;
unsigned
char
*
tx_bufs
;
u32
dma_offset
;
u32
flags
;
...
...
@@ -531,12 +429,11 @@ struct b44 {
struct
pci_dev
*
pdev
;
struct
net_device
*
dev
;
dma_addr_t
rx_ring_dma
,
tx_ring_dma
;
dma_addr_t
rx_ring_dma
,
tx_ring_dma
,
tx_bufs_dma
;
u32
rx_pending
;
u32
tx_pending
;
u8
phy_addr
;
u8
mdc_port
;
u8
core_unit
;
struct
mii_if_info
mii_if
;
...
...
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