V4L/DVB (9110): cx18: Add default behavior of checking and retrying PCI MMIO accesses

cx18: Add default behavior of checking and retrying PCI MMIO accesses.
The concept of checking and retrying PCI MMIO accesses for better reliability
in older motherboards was suggested by Steve Toth <stoth@linuxtv.org>.  This
change implements MMIO retries and the retry_mmio module parameter that is
enabled by default.  Limited experiments have shown this is more reliable than
the mmio_ndelay parameter.  mmio_ndelay has insignificant effect with retries
enabled.
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

drivers/media/video/cx18/cx18-av-core.c

@@ -42,6 +42,12 @@ int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
 	return 0;
 }
 
+int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
+{
+	cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
+	return 0;
+}
+
 u8 cx18_av_read(struct cx18 *cx, u16 addr)
 {
 	u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
@@ -55,6 +61,11 @@ u32 cx18_av_read4(struct cx18 *cx, u16 addr)
 	return cx18_read_reg(cx, 0xc40000 + addr);
 }
 
+u32 cx18_av_read4_noretry(struct cx18 *cx, u16 addr)
+{
+	return cx18_read_reg_noretry(cx, 0xc40000 + addr);
+}
+
 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
 		   u8 or_value)
 {

drivers/media/video/cx18/cx18-av-core.h

@@ -301,8 +301,10 @@ struct cx18_av_state {
 /* cx18_av-core.c 							   */
 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
+int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value);
 u8 cx18_av_read(struct cx18 *cx, u16 addr);
 u32 cx18_av_read4(struct cx18 *cx, u16 addr);
+u32 cx18_av_read4_noretry(struct cx18 *cx, u16 addr);
 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value);
 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value);
 int cx18_av_cmd(struct cx18 *cx, unsigned int cmd, void *arg);

drivers/media/video/cx18/cx18-av-firmware.c

@@ -50,7 +50,7 @@ int cx18_av_loadfw(struct cx18 *cx)
 		cx18_av_write4(cx, 0x8100, 0x00010000);
 
 		/* Put the 8051 in reset and enable firmware upload */
-		cx18_av_write4(cx, CXADEC_DL_CTL, 0x0F000000);
+		cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
 
 		ptr = fw->data;
 		size = fw->size;
@@ -59,22 +59,28 @@ int cx18_av_loadfw(struct cx18 *cx)
 			u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
 			u32 value = 0;
 			int retries2;
+			int unrec_err = 0;
 
-			for (retries2 = 0; retries2 < 5; retries2++) {
-				cx18_av_write4(cx, CXADEC_DL_CTL, dl_control);
+			for (retries2 = 0; retries2 < CX18_MAX_MMIO_RETRIES;
+			     retries2++) {
+				cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
+						       dl_control);
 				udelay(10);
-				value = cx18_av_read4(cx, CXADEC_DL_CTL);
+				value = cx18_av_read4_noretry(cx,
+							      CXADEC_DL_CTL);
 				if (value == dl_control)
 					break;
 				/* Check if we can correct the byte by changing
 				   the address.  We can only write the lower
 				   address byte of the address. */
 				if ((value & 0x3F00) != (dl_control & 0x3F00)) {
-					retries2 = 5;
+					unrec_err = 1;
 					break;
 				}
 			}
-			if (retries2 >= 5)
+			cx18_log_write_retries(cx, retries2,
+					cx->reg_mem + 0xc40000 + CXADEC_DL_CTL);
+			if (unrec_err || retries2 >= CX18_MAX_MMIO_RETRIES)
 				break;
 		}
 		if (i == size)

drivers/media/video/cx18/cx18-driver.c

@@ -96,6 +96,7 @@ static int enc_pcm_buffers = CX18_DEFAULT_ENC_PCM_BUFFERS;
 
 static int cx18_pci_latency = 1;
 
+int cx18_retry_mmio = 1;
 int cx18_debug;
 
 module_param_array(tuner, int, &tuner_c, 0644);
@@ -106,6 +107,7 @@ module_param_string(pal, pal, sizeof(pal), 0644);
 module_param_string(secam, secam, sizeof(secam), 0644);
 module_param_string(ntsc, ntsc, sizeof(ntsc), 0644);
 module_param_named(debug, cx18_debug, int, 0644);
+module_param_named(retry_mmio, cx18_retry_mmio, int, 0644);
 module_param(cx18_pci_latency, int, 0644);
 module_param(cx18_first_minor, int, 0644);
 
@@ -147,6 +149,9 @@ MODULE_PARM_DESC(debug,
 MODULE_PARM_DESC(cx18_pci_latency,
 		 "Change the PCI latency to 64 if lower: 0 = No, 1 = Yes,\n"
 		 "\t\t\tDefault: Yes");
+MODULE_PARM_DESC(retry_mmio,
+		 "Check and retry memory mapped IO accesses\n"
+		 "\t\t\tDefault: 1 [Yes]");
 MODULE_PARM_DESC(mmio_ndelay,
 		 "Delay (ns) for each CX23418 memory mapped IO access.\n"
 		 "\t\t\tTry larger values that are close to a multiple of the\n"
@@ -827,6 +832,7 @@ static int __devinit cx18_probe(struct pci_dev *dev,
 	if (retval == 0)
 		retval = -ENODEV;
 	CX18_ERR("Error %d on initialization\n", retval);
+	cx18_log_statistics(cx);
 
 	kfree(cx18_cards[cx18_cards_active]);
 	cx18_cards[cx18_cards_active] = NULL;
@@ -931,6 +937,7 @@ static void cx18_remove(struct pci_dev *pci_dev)
 
 	pci_disable_device(cx->dev);
 
+	cx18_log_statistics(cx);
 	CX18_INFO("Removed %s, card #%d\n", cx->card_name, cx->num);
 }
 

drivers/media/video/cx18/cx18-driver.h

@@ -171,6 +171,7 @@
 
 #define CX18_MAX_PGM_INDEX (400)
 
+extern int cx18_retry_mmio;	/* enable check & retry of mmio accesses */
 extern int cx18_debug;
 
 
@@ -344,6 +345,13 @@ struct cx18_i2c_algo_callback_data {
 	int bus_index;   /* 0 or 1 for the cx23418's 1st or 2nd I2C bus */
 };
 
+#define CX18_MAX_MMIO_RETRIES 10
+
+struct cx18_mmio_stats {
+	atomic_t retried_write[CX18_MAX_MMIO_RETRIES+1];
+	atomic_t retried_read[CX18_MAX_MMIO_RETRIES+1];
+};
+
 /* Struct to hold info about cx18 cards */
 struct cx18 {
 	int num;		/* board number, -1 during init! */
@@ -433,6 +441,9 @@ struct cx18 {
 	u32 gpio_val;
 	struct mutex gpio_lock;
 
+	/* Statistics */
+	struct cx18_mmio_stats mmio_stats;
+
 	/* v4l2 and User settings */
 
 	/* codec settings */

drivers/media/video/cx18/cx18-io.c

@@ -24,6 +24,131 @@
 #include "cx18-io.h"
 #include "cx18-irq.h"
 
+void cx18_log_statistics(struct cx18 *cx)
+{
+	int i;
+
+	if (!(cx18_debug & CX18_DBGFLG_INFO))
+		return;
+
+	for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
+		CX18_DEBUG_INFO("retried_write[%d] = %d\n", i,
+				atomic_read(&cx->mmio_stats.retried_write[i]));
+	for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
+		CX18_DEBUG_INFO("retried_read[%d] = %d\n", i,
+				atomic_read(&cx->mmio_stats.retried_read[i]));
+	return;
+}
+
+void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
+{
+	int i;
+	for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+		cx18_raw_writel_noretry(cx, val, addr);
+		if (val == cx18_raw_readl_noretry(cx, addr))
+			break;
+	}
+	cx18_log_write_retries(cx, i, addr);
+}
+
+u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr)
+{
+	int i;
+	u32 val;
+	for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+		val = cx18_raw_readl_noretry(cx, addr);
+		if (val != 0xffffffff) /* PCI bus read error */
+			break;
+	}
+	cx18_log_read_retries(cx, i, addr);
+	return val;
+}
+
+u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
+{
+	int i;
+	u16 val;
+	for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+		val = cx18_raw_readw_noretry(cx, addr);
+		if (val != 0xffff) /* PCI bus read error */
+			break;
+	}
+	cx18_log_read_retries(cx, i, addr);
+	return val;
+}
+
+void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
+{
+	int i;
+	for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+		cx18_writel_noretry(cx, val, addr);
+		if (val == cx18_readl_noretry(cx, addr))
+			break;
+	}
+	cx18_log_write_retries(cx, i, addr);
+}
+
+void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
+{
+	int i;
+	for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+		cx18_writew_noretry(cx, val, addr);
+		if (val == cx18_readw_noretry(cx, addr))
+			break;
+	}
+	cx18_log_write_retries(cx, i, addr);
+}
+
+void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr)
+{
+	int i;
+	for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+		cx18_writeb_noretry(cx, val, addr);
+		if (val == cx18_readb_noretry(cx, addr))
+			break;
+	}
+	cx18_log_write_retries(cx, i, addr);
+}
+
+u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr)
+{
+	int i;
+	u32 val;
+	for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+		val = cx18_readl_noretry(cx, addr);
+		if (val != 0xffffffff) /* PCI bus read error */
+			break;
+	}
+	cx18_log_read_retries(cx, i, addr);
+	return val;
+}
+
+u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr)
+{
+	int i;
+	u16 val;
+	for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+		val = cx18_readw_noretry(cx, addr);
+		if (val != 0xffff) /* PCI bus read error */
+			break;
+	}
+	cx18_log_read_retries(cx, i, addr);
+	return val;
+}
+
+u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr)
+{
+	int i;
+	u8 val;
+	for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+		val = cx18_readb_noretry(cx, addr);
+		if (val != 0xff) /* PCI bus read error */
+			break;
+	}
+	cx18_log_read_retries(cx, i, addr);
+	return val;
+}
+
 void cx18_memcpy_fromio(struct cx18 *cx, void *to,
 			const void __iomem *from, unsigned int len)
 {
@@ -127,13 +252,3 @@ void cx18_setup_page(struct cx18 *cx, u32 addr)
 	val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
 	cx18_write_reg(cx, val, 0xD000F8);
 }
-
-/* Tries to recover from the CX23418 responding improperly on the PCI bus */
-int cx18_pci_try_recover(struct cx18 *cx)
-{
-	u16 status;
-
-	pci_read_config_word(cx->dev, PCI_STATUS, &status);
-	pci_write_config_word(cx->dev, PCI_STATUS, status);
-	return 0;
-}

drivers/media/video/cx18/cx18-io.h

@@ -31,102 +31,343 @@ static inline void cx18_io_delay(struct cx18 *cx)
 		ndelay(cx->options.mmio_ndelay);
 }
 
+/*
+ * Readback and retry of MMIO access for reliability:
+ * The concept was suggested by Steve Toth <stoth@linuxtv.org>.
+ * The implmentation is the fault of Andy Walls <awalls@radix.net>.
+ */
+
+/* Statistics gathering */
+static inline
+void cx18_log_write_retries(struct cx18 *cx, int i, const void *addr)
+{
+	if (i > CX18_MAX_MMIO_RETRIES)
+		i = CX18_MAX_MMIO_RETRIES;
+	atomic_inc(&cx->mmio_stats.retried_write[i]);
+	return;
+}
+
+static inline
+void cx18_log_read_retries(struct cx18 *cx, int i, const void *addr)
+{
+	if (i > CX18_MAX_MMIO_RETRIES)
+		i = CX18_MAX_MMIO_RETRIES;
+	atomic_inc(&cx->mmio_stats.retried_read[i]);
+	return;
+}
+
+void cx18_log_statistics(struct cx18 *cx);
+
 /* Non byteswapping memory mapped IO */
-static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
+static inline
+void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
 {
 	__raw_writel(val, addr);
 	cx18_io_delay(cx);
 }
 
-static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
+void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr);
+
+static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
+{
+	if (cx18_retry_mmio)
+		cx18_raw_writel_retry(cx, val, addr);
+	else
+		cx18_raw_writel_noretry(cx, val, addr);
+}
+
+
+static inline
+u32 cx18_raw_readl_noretry(struct cx18 *cx, const void __iomem *addr)
 {
 	u32 ret = __raw_readl(addr);
 	cx18_io_delay(cx);
 	return ret;
 }
 
-static inline u16 cx18_raw_readw(struct cx18 *cx, const void __iomem *addr)
+u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr);
+
+static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
+{
+	if (cx18_retry_mmio)
+		return cx18_raw_readl_retry(cx, addr);
+
+	return cx18_raw_readl_noretry(cx, addr);
+}
+
+
+static inline
+u16 cx18_raw_readw_noretry(struct cx18 *cx, const void __iomem *addr)
 {
 	u16 ret = __raw_readw(addr);
 	cx18_io_delay(cx);
 	return ret;
 }
 
+u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr);
+
+static inline u16 cx18_raw_readw(struct cx18 *cx, const void __iomem *addr)
+{
+	if (cx18_retry_mmio)
+		return cx18_raw_readw_retry(cx, addr);
+
+	return cx18_raw_readw_noretry(cx, addr);
+}
+
+
 /* Normal memory mapped IO */
-static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
+static inline
+void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
 {
 	writel(val, addr);
 	cx18_io_delay(cx);
 }
 
-static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr)
+void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr);
+
+static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
+{
+	if (cx18_retry_mmio)
+		cx18_writel_retry(cx, val, addr);
+	else
+		cx18_writel_noretry(cx, val, addr);
+}
+
+
+static inline
+void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr)
 {
 	writew(val, addr);
 	cx18_io_delay(cx);
 }
 
-static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr)
+void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr);
+
+static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr)
+{
+	if (cx18_retry_mmio)
+		cx18_writew_retry(cx, val, addr);
+	else
+		cx18_writew_noretry(cx, val, addr);
+}
+
+
+static inline
+void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr)
 {
 	writeb(val, addr);
 	cx18_io_delay(cx);
 }
 
-static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
+void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr);
+
+static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr)
+{
+	if (cx18_retry_mmio)
+		cx18_writeb_retry(cx, val, addr);
+	else
+		cx18_writeb_noretry(cx, val, addr);
+}
+
+
+static inline u32 cx18_readl_noretry(struct cx18 *cx, const void __iomem *addr)
 {
 	u32 ret = readl(addr);
 	cx18_io_delay(cx);
 	return ret;
 }
 
-static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
+u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr);
+
+static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
+{
+	if (cx18_retry_mmio)
+		return cx18_readl_retry(cx, addr);
+
+	return cx18_readl_noretry(cx, addr);
+}
+
+
+static inline u16 cx18_readw_noretry(struct cx18 *cx, const void __iomem *addr)
+{
+	u16 ret = readw(addr);
+	cx18_io_delay(cx);
+	return ret;
+}
+
+u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr);
+
+static inline u16 cx18_readw(struct cx18 *cx, const void __iomem *addr)
+{
+	if (cx18_retry_mmio)
+		return cx18_readw_retry(cx, addr);
+
+	return cx18_readw_noretry(cx, addr);
+}
+
+
+static inline u8 cx18_readb_noretry(struct cx18 *cx, const void __iomem *addr)
 {
 	u8 ret = readb(addr);
 	cx18_io_delay(cx);
 	return ret;
 }
 
+u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr);
+
+static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
+{
+	if (cx18_retry_mmio)
+		return cx18_readb_retry(cx, addr);
+
+	return cx18_readb_noretry(cx, addr);
+}
+
+
+static inline
+u32 cx18_write_sync_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
+{
+	cx18_writel_noretry(cx, val, addr);
+	return cx18_readl_noretry(cx, addr);
+}
+
+static inline
+u32 cx18_write_sync_retry(struct cx18 *cx, u32 val, void __iomem *addr)
+{
+	cx18_writel_retry(cx, val, addr);
+	return cx18_readl_retry(cx, addr);
+}
+
 static inline u32 cx18_write_sync(struct cx18 *cx, u32 val, void __iomem *addr)
 {
-	cx18_writel(cx, val, addr);
-	return cx18_readl(cx, addr);
+	if (cx18_retry_mmio)
+		return cx18_write_sync_retry(cx, val, addr);
+
+	return cx18_write_sync_noretry(cx, val, addr);
 }
 
+
 void cx18_memcpy_fromio(struct cx18 *cx, void *to,
 			const void __iomem *from, unsigned int len);
 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count);
 
+
 /* Access "register" region of CX23418 memory mapped I/O */
+static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg)
+{
+	cx18_writel_noretry(cx, val, cx->reg_mem + reg);
+}
+
+static inline void cx18_write_reg_retry(struct cx18 *cx, u32 val, u32 reg)
+{
+	cx18_writel_retry(cx, val, cx->reg_mem + reg);
+}
+
 static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
 {
-	cx18_writel(cx, val, cx->reg_mem + reg);
+	if (cx18_retry_mmio)
+		cx18_write_reg_retry(cx, val, reg);
+	else
+		cx18_write_reg_noretry(cx, val, reg);
+}
+
+
+static inline u32 cx18_read_reg_noretry(struct cx18 *cx, u32 reg)
+{
+	return cx18_readl_noretry(cx, cx->reg_mem + reg);
+}
+
+static inline u32 cx18_read_reg_retry(struct cx18 *cx, u32 reg)
+{
+	return cx18_readl_retry(cx, cx->reg_mem + reg);
 }
 
 static inline u32 cx18_read_reg(struct cx18 *cx, u32 reg)
 {
-	return cx18_readl(cx, cx->reg_mem + reg);
+	if (cx18_retry_mmio)
+		return cx18_read_reg_retry(cx, reg);
+
+	return cx18_read_reg_noretry(cx, reg);
+}
+
+
+static inline u32 cx18_write_reg_sync_noretry(struct cx18 *cx, u32 val, u32 reg)
+{
+	return cx18_write_sync_noretry(cx, val, cx->reg_mem + reg);
+}
+
+static inline u32 cx18_write_reg_sync_retry(struct cx18 *cx, u32 val, u32 reg)
+{
+	return cx18_write_sync_retry(cx, val, cx->reg_mem + reg);
 }
 
 static inline u32 cx18_write_reg_sync(struct cx18 *cx, u32 val, u32 reg)
 {
-	return cx18_write_sync(cx, val, cx->reg_mem + reg);
+	if (cx18_retry_mmio)
+		return cx18_write_reg_sync_retry(cx, val, reg);
+
+	return cx18_write_reg_sync_noretry(cx, val, reg);
 }
 
+
 /* Access "encoder memory" region of CX23418 memory mapped I/O */
+static inline void cx18_write_enc_noretry(struct cx18 *cx, u32 val, u32 addr)
+{
+	cx18_writel_noretry(cx, val, cx->enc_mem + addr);
+}
+
+static inline void cx18_write_enc_retry(struct cx18 *cx, u32 val, u32 addr)
+{
+	cx18_writel_retry(cx, val, cx->enc_mem + addr);
+}
+
 static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr)
 {
-	cx18_writel(cx, val, cx->enc_mem + addr);
+	if (cx18_retry_mmio)
+		cx18_write_enc_retry(cx, val, addr);
+	else
+		cx18_write_enc_noretry(cx, val, addr);
+}
+
+
+static inline u32 cx18_read_enc_noretry(struct cx18 *cx, u32 addr)
+{
+	return cx18_readl_noretry(cx, cx->enc_mem + addr);
+}
+
+static inline u32 cx18_read_enc_retry(struct cx18 *cx, u32 addr)
+{
+	return cx18_readl_retry(cx, cx->enc_mem + addr);
 }
 
 static inline u32 cx18_read_enc(struct cx18 *cx, u32 addr)
 {
-	return cx18_readl(cx, cx->enc_mem + addr);
+	if (cx18_retry_mmio)
+		return cx18_read_enc_retry(cx, addr);
+
+	return cx18_read_enc_noretry(cx, addr);
+}
+
+static inline
+u32 cx18_write_enc_sync_noretry(struct cx18 *cx, u32 val, u32 addr)
+{
+	return cx18_write_sync_noretry(cx, val, cx->enc_mem + addr);
 }
 
-static inline u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr)
+static inline
+u32 cx18_write_enc_sync_retry(struct cx18 *cx, u32 val, u32 addr)
 {
-	return cx18_write_sync(cx, val, cx->enc_mem + addr);
+	return cx18_write_sync_retry(cx, val, cx->enc_mem + addr);
 }
 
+static inline
+u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr)
+{
+	if (cx18_retry_mmio)
+		return cx18_write_enc_sync_retry(cx, val, addr);
+
+	return cx18_write_enc_sync_noretry(cx, val, addr);
+}
 
 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val);
 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val);
@@ -134,7 +375,4 @@ void cx18_sw2_irq_enable(struct cx18 *cx, u32 val);
 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val);
 void cx18_setup_page(struct cx18 *cx, u32 addr);
 
-/* Tries to recover from the CX23418 responding improperly on the PCI bus */
-int cx18_pci_try_recover(struct cx18 *cx);
-
 #endif /* CX18_IO_H */

drivers/media/video/cx18/cx18-ioctl.c

@@ -752,6 +752,7 @@ static int cx18_log_status(struct file *file, void *fh)
 	CX18_INFO("Read MPEG/VBI: %lld/%lld bytes\n",
 			(long long)cx->mpg_data_received,
 			(long long)cx->vbi_data_inserted);
+	cx18_log_statistics(cx);
 	CX18_INFO("==================  END STATUS CARD #%d  ==================\n", cx->num);
 	return 0;
 }