Commit d352f41e authored by Arnaud Ebalard's avatar Arnaud Ebalard Committed by Jason Cooper

arm: mvebu: define and use common Armada XP UART2/3 pinctrl settings

This patch defines common Armada XP pinctrl settings for uart2 and
uart3 interfaces (uart0 and uart1 rx/tx do not rely on MPP):

 uart2: MPP42-43 as default
 uart3: MPP44-45 as default
Suggested-by: default avatarAndrew Lunn <andrew@lunn.ch>
Acked-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarArnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/fd51c080c7139a67ec01df8d797f1e88ce557796.1416613429.git.arno@natisbad.orgSigned-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent f8afeaea
...@@ -55,6 +55,8 @@ i2c1: i2c@11100 { ...@@ -55,6 +55,8 @@ i2c1: i2c@11100 {
uart2: serial@12200 { uart2: serial@12200 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
reg = <0x12200 0x100>; reg = <0x12200 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <43>; interrupts = <43>;
...@@ -65,6 +67,8 @@ uart2: serial@12200 { ...@@ -65,6 +67,8 @@ uart2: serial@12200 {
uart3: serial@12300 { uart3: serial@12300 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
pinctrl-0 = <&uart3_pins>;
pinctrl-names = "default";
reg = <0x12300 0x100>; reg = <0x12300 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <44>; interrupts = <44>;
...@@ -235,4 +239,14 @@ sdio_pins: sdio-pins { ...@@ -235,4 +239,14 @@ sdio_pins: sdio-pins {
"mpp33", "mpp34", "mpp35"; "mpp33", "mpp34", "mpp35";
marvell,function = "sd0"; marvell,function = "sd0";
}; };
uart2_pins: uart2-pins {
marvell,pins = "mpp42", "mpp43";
marvell,function = "uart2";
};
uart3_pins: uart3-pins {
marvell,pins = "mpp44", "mpp45";
marvell,function = "uart3";
};
}; };
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