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Commit d35cbff8 authored by Paul Mackerras's avatar Paul Mackerras
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PPC32: Add support for the IBM405LP-based "Beech" board

parent f55d5107
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arch/ppc/configs/beech_defconfig 0 → 100644
View file @ d35cbff8
#
# Automatically generated make config: don't edit
#
# CONFIG_UID16 is not set
# CONFIG_RWSEM_GENERIC_SPINLOCK is not set
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_HAVE_DEC_LOCK=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
# CONFIG_ADVANCED_OPTIONS is not set
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODVERSIONS=y
CONFIG_KMOD=y
#
# Platform support
#
CONFIG_PPC=y
CONFIG_PPC32=y
# CONFIG_6xx is not set
CONFIG_40x=y
# CONFIG_440 is not set
# CONFIG_POWER3 is not set
# CONFIG_8xx is not set
# CONFIG_PPC_ISERIES is not set
CONFIG_4xx=y
# CONFIG_PPC_STD_MMU is not set
# CONFIG_ASH is not set
# CONFIG_CEDER is not set
CONFIG_BEECH=y
# CONFIG_CPCI405 is not set
# CONFIG_EP405 is not set
# CONFIG_OAK is not set
# CONFIG_RAINIER is not set
# CONFIG_REDWOOD_4 is not set
# CONFIG_REDWOOD_5 is not set
# CONFIG_TIVO is not set
# CONFIG_WALNUT is not set
# CONFIG_ALL_PPC is not set
# CONFIG_SMP is not set
# CONFIG_MATH_EMULATION is not set
CONFIG_405LP=y
CONFIG_IBM_OPENBIOS=y
CONFIG_IBM405_ERR77=y
CONFIG_IBM_OCP=y
# CONFIG_PM is not set
CONFIG_UART0_TTYS0=y
# CONFIG_UART0_TTYS1 is not set
CONFIG_IBM405_ERR51=y
CONFIG_NOT_COHERENT_CACHE=y
# CONFIG_PPC4xx_DMA is not set
CONFIG_OCP_PROC=y
#
# General setup
#
# CONFIG_HIGHMEM is not set
# CONFIG_ISA is not set
# CONFIG_EISA is not set
# CONFIG_SBUS is not set
# CONFIG_MCA is not set
# CONFIG_PCI is not set
# CONFIG_PC_KEYBOARD is not set
CONFIG_NET=y
CONFIG_SYSCTL=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
CONFIG_KERNEL_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
# CONFIG_PPC_RTC is not set
# CONFIG_CMDLINE_BOOL is not set
#
# Memory Technology Devices (MTD)
#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_CONCAT is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# CONFIG_MTD_OBSOLETE_CHIPS is not set
# CONFIG_MTD_AMDSTD is not set
# CONFIG_MTD_SHARP is not set
# CONFIG_MTD_JEDEC is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_DBOX2 is not set
# CONFIG_MTD_CFI_FLAGADM is not set
# CONFIG_MTD_PCI is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC1000 is not set
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOCPROBE is not set
#
# NAND Flash Device Drivers
#
# CONFIG_MTD_NAND is not set
#
# Plug and Play configuration
#
# CONFIG_PNP is not set
# CONFIG_ISAPNP is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_CISS_SCSI_TAPE is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_INITRD=y
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_MD_MULTIPATH is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Networking options
#
# CONFIG_PACKET is not set
# CONFIG_NETLINK_DEV is not set
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
CONFIG_SYN_COOKIES=y
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
#
#
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
#
# Appletalk devices
#
# CONFIG_DEV_APPLETALK is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
#
# ATA/IDE/MFM/RLL support
#
# CONFIG_IDE is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI support
#
# CONFIG_SCSI is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
# CONFIG_FUSION_BOOT is not set
# CONFIG_FUSION_ISENSE is not set
# CONFIG_FUSION_CTL is not set
# CONFIG_FUSION_LAN is not set
#
# I2O device support
#
# CONFIG_I2O is not set
# CONFIG_I2O_BLOCK is not set
# CONFIG_I2O_LAN is not set
# CONFIG_I2O_SCSI is not set
# CONFIG_I2O_PROC is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_MACE is not set
# CONFIG_BMAC is not set
# CONFIG_GMAC is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
#
# Backplane Networking
#
# CONFIG_NPNET is not set
#
# On-chip net devices
#
# CONFIG_IBM_OCP_ENET is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Token Ring devices
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set
#
# IrDA (infrared) support
#
# CONFIG_IRDA is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
#
# CONFIG_CD_NO_IDESCSI is not set
#
# Console drivers
#
#
# Frame-buffer support
#
CONFIG_FB=y
CONFIG_DUMMY_CONSOLE=y
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_CT65550 is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_S3TRIO is not set
# CONFIG_FB_VESA is not set
# CONFIG_FB_VGA16 is not set
# CONFIG_FB_LYNX is not set
# CONFIG_FB_VIRTUAL is not set
CONFIG_FBCON_ADVANCED=y
CONFIG_FBCON_MFB=y
CONFIG_FBCON_CFB2=y
CONFIG_FBCON_CFB4=y
CONFIG_FBCON_CFB8=y
CONFIG_FBCON_CFB16=y
CONFIG_FBCON_CFB24=y
CONFIG_FBCON_CFB32=y
# CONFIG_FBCON_AFB is not set
# CONFIG_FBCON_ILBM is not set
# CONFIG_FBCON_IPLAN2P2 is not set
# CONFIG_FBCON_IPLAN2P4 is not set
# CONFIG_FBCON_IPLAN2P8 is not set
# CONFIG_FBCON_MAC is not set
# CONFIG_FBCON_VGA_PLANES is not set
# CONFIG_FBCON_VGA is not set
# CONFIG_FBCON_HGA is not set
# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
CONFIG_FBCON_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_PEARL_8x8 is not set
# CONFIG_FONT_ACORN_8x8 is not set
#
# Input core support
#
# CONFIG_INPUT is not set
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
#
# Macintosh device drivers
#
#
# Character devices
#
CONFIG_VT=y
# CONFIG_VT_CONSOLE is not set
CONFIG_SERIAL=y
CONFIG_SERIAL_CONSOLE=y
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
#
CONFIG_I2C=y
# CONFIG_I2C_ALGOBIT is not set
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_IBM_OCP_ALGO is not set
# CONFIG_I2C_CHARDEV is not set
# CONFIG_I2C_PROC is not set
#
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_MOUSE is not set
#
# Joysticks
#
# CONFIG_INPUT_GAMEPORT is not set
#
# Input core support is needed for gameports
#
#
# Input core support is needed for joysticks
#
# CONFIG_QIC02_TAPE is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
CONFIG_IBM_OCP_GPIO=y
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# File systems
#
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_JBD_DEBUG is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
CONFIG_TMPFS=y
CONFIG_RAMFS=y
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
# CONFIG_ZISOFS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
CONFIG_DEVFS_FS=y
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
#
# Network File Systems
#
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
# CONFIG_NFSD_V3 is not set
CONFIG_SUNRPC=y
CONFIG_LOCKD=y
# CONFIG_SMB_FS is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_STRONG is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
# CONFIG_ZISOFS_FS is not set
# CONFIG_ZLIB_FS_INFLATE is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
#
# Sound
#
CONFIG_SOUND=y
# CONFIG_SOUND_BT878 is not set
# CONFIG_SOUND_CMPCI is not set
# CONFIG_SOUND_EMU10K1 is not set
# CONFIG_MIDI_EMU10K1 is not set
# CONFIG_SOUND_FUSION is not set
# CONFIG_SOUND_CS4281 is not set
# CONFIG_SOUND_ES1370 is not set
# CONFIG_SOUND_ES1371 is not set
# CONFIG_SOUND_ESSSOLO1 is not set
# CONFIG_SOUND_MAESTRO is not set
# CONFIG_SOUND_MAESTRO3 is not set
# CONFIG_SOUND_ICH is not set
# CONFIG_SOUND_RME96XX is not set
# CONFIG_SOUND_SONICVIBES is not set
# CONFIG_SOUND_TRIDENT is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_VIA82CXXX is not set
# CONFIG_MIDI_VIA82CXXX is not set
# CONFIG_SOUND_OSS is not set
# CONFIG_SOUND_TVMIXER is not set
#
# IBM 4xx options
#
#
# USB support
#
# CONFIG_USB is not set
#
# Bluetooth support
#
# CONFIG_BLUEZ is not set
#
# Kernel hacking
#
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_KGDB is not set
# CONFIG_XMON is not set
# CONFIG_BDI_SWITCH is not set
# CONFIG_SERIAL_TEXT_DEBUG is not set
arch/ppc/platforms/4xx/Kconfig
View file @ d35cbff8
...@@ -13,6 +13,9 @@ choice ...@@ -13,6 +13,9 @@ choice
config ASH config ASH
bool "Ash" bool "Ash"
config BEECH
bool "Beech"
config CEDAR config CEDAR
bool "Cedar" bool "Cedar"
...@@ -75,7 +78,7 @@ config IBM405_ERR51 ...@@ -75,7 +78,7 @@ config IBM405_ERR51
config IBM_OCP config IBM_OCP
bool bool
depends on ASH || CEDAR || CPCI405 || EP405 || REDWOOD_4 || REDWOOD_5 || WALNUT depends on ASH || BEECH || CEDAR || CPCI405 || EP405 || REDWOOD_4 || REDWOOD_5 || WALNUT
default y default y
config NP405L config NP405L
...@@ -110,7 +113,7 @@ config EMBEDDEDBOOT ...@@ -110,7 +113,7 @@ config EMBEDDEDBOOT
config IBM_OPENBIOS config IBM_OPENBIOS
bool bool
depends on ASH || CEDAR || REDWOOD_4 || REDWOOD_5 || WALNUT depends on ASH || BEECH || CEDAR || REDWOOD_4 || REDWOOD_5 || WALNUT
default y default y
config 405_DMA config 405_DMA
......
arch/ppc/platforms/4xx/Makefile
View file @ d35cbff8
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
# Makefile for the PowerPC 4xx linux kernel. # Makefile for the PowerPC 4xx linux kernel.
obj-$(CONFIG_ASH) += ash.o obj-$(CONFIG_ASH) += ash.o
obj-$(CONFIG_BEECH) += beech.o
obj-$(CONFIG_CEDAR) += cedar.o obj-$(CONFIG_CEDAR) += cedar.o
obj-$(CONFIG_CPCI405) += cpci405.o obj-$(CONFIG_CPCI405) += cpci405.o
obj-$(CONFIG_EP405) += ep405.o obj-$(CONFIG_EP405) += ep405.o
......
arch/ppc/platforms/4xx/beech.c 0 → 100644
View file @ d35cbff8
/*
* arch/ppc/platforms/beech.c Platform setup for the IBM Beech board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2002, International Business Machines Corporation
* All Rights Reserved
*
* Bishop Brock
* IBM Research, Austin Center for Low-Power Computing
* bcbrock@us.ibm.com
* March, 2002
*
*/
#include <linux/blk.h>
#include <linux/config.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/param.h>
#include <linux/rtc.h>
#include <linux/string.h>
#include <asm/delay.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/page.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/todc.h>
static void beech_ebc_setup(void);
static void beech_fpga_setup(void);
/*
Beech board physical memory map:
Main Memory (Initialized by the BIOS)
=======================================================================
SDRAM (64 MB) 0x00000000 - 0x04000000
OPB Space: (Mapped virtual = physical in ppc4xx_setup.c)
=======================================================================
UART0 0xEF600300
UART1 0xEF600400
IIC 0xEF600500
OPB Arbiter 0xEF600600
GPIO Controller 0xEF600700
CODEC Interface 0xEF600900
Touch Panel Controller 0xEF600A00
DES Controller 0xEF600B00
EBC Space: (Mapped virtual = physical in ppc4xx_map_io(); EBC setup
for PCMCIA left to 4xx_pccf)
Space EBC Bank Physical Addresses EBC Base Address
=========================================================================
PCMCIA (32 MB) x F0000000 - F1FFFFFF F0000000
Expansion 2 F8000000 - F8FFFFFF F8000000
Linux Flash (16 MB) F9000000 - F9FFFFFF
NVRAM (32 KB) 1 FFE00000 - FFE07FFF FFE00000
Ethernet(I/O) 1 FFE20300 - FFE2030F FFE00000
(MEM) FFE40000 - FFE40FFF
FPGA_REG_4 1 FFE60000 - FFE60000 FFE00000
FPGA_REG_0 1 FFE80000 - FFE80000 FFE00000
FPGA_REG_1 1 FFEA0000 - FFEA0000 FFE00000
FPGA_REG_2 1 FFEC0000 - FFEC0000 FFE00000
FPGA_REG_3 1 FFEE0000 - FFEE0000 FFE00000
SRAM (512 KB) 0 FFF00000 - FFF7FFFF FFF00000
Boot Flash (512 KB) 0 FFF80000 - FFFFFFFF FFF00000
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
NB: On Beech 1, address ranges for Bank 2 were reversed
*/
void __init
beech_setup_arch(void)
{
ppc4xx_setup_arch();
TODC_INIT(TODC_TYPE_DCR146818, NULL, NULL, NULL, 8);
/* Set up Beech FPGA. */
beech_fpga_setup();
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
ppc4xx_init(r3, r4, r5, r6, r7);
ppc_md.setup_arch = beech_setup_arch;
#ifdef CONFIG_PPC_RTC
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.nvram_read_val = todc_dcr146818_read_val;
ppc_md.nvram_write_val = todc_dcr146818_write_val;
#endif
/* Disable the LCD controller, which may have been left on by the
BIOS. Then do initialization of the EBC. */
mtdcri(DCRN_LCD0, DER, 0);
beech_ebc_setup();
}
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ Non-standard board support follows
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
/****************************************************************************
* EBC Setup
****************************************************************************/
/* The EBC is set up for Beech. This may simply replicate the setup already
done by the IBM BIOS for Beech (possibly with some address map changes), or
may be the first initialization if the board is booting from another BIOS.
Virtually all that is required to boot Linux on Beech is that the BIOS
enable the memory controller, load a Linux image from flash, and run it.
For optimal dynamic frequency scaling the EBC settings will also vary as the
frequency varies.
*/
static void __init
beech_ebc_setup(void)
{
ebc0_bnap_t ap;
ebc0_bncr_t cr;
/* Set EBC bank 0 for the SRAM and boot flash.
Access parameters assume 120ns AMD flash @ 66.66 MHz maximum bus
speed = 8 cycle access with 2 turnaround cycles (30 ns).
These parameters will work for the SRAM as well, which is a 70 ns
part.
NB: IBM BIOS sets this bank to burst, however bursting will never
happen in Linux because this region is mapped non-cacheable and
guarded, so it is set non-burst here. */
cr.reg = (BEECH_BANK0_PADDR & 0xfff00000) |
(mfdcri(DCRN_EBC0, BnCR(0)) & EBC0_BnCR_MASK);
cr.fields.bs = BEECH_BANK0_EBC_SIZE;
cr.fields.bu = EBC0_BnCR_BU_RW;
cr.fields.bw = EBC0_BnCR_BW_16;
mtdcri(DCRN_EBC0, BnCR(0), cr.reg);
ap.reg = mfdcri(DCRN_EBC0, BnAP(0)) & EBC0_BnAP_MASK;
ap.fields.twt = 8;
ap.fields.th = 2;
mtdcri(DCRN_EBC0, BnAP(0), ap.reg);
/* EBC bank 1 is used for many purposes: NVRAM, Ethernet, and FPGA
registers. This is a 1 MB, 16-bit bank. The access parameters must
handle the worst case of all of the devices.
The Ethernet chip needs 20 ns setup of the addresses to the I/O
write signal (generated from the chip select), a minimum 150 ns
cycle, and 30 ns of turnaround. These settings will work for the
other devices as well.
*/
cr.reg = (BEECH_BANK1_PADDR & 0xfff00000) |
(mfdcri(DCRN_EBC0, BnCR(1)) & EBC0_BnCR_MASK);
cr.fields.bs = BEECH_BANK1_EBC_SIZE;
cr.fields.bu = EBC0_BnCR_BU_RW;
cr.fields.bw = EBC0_BnCR_BW_16;
mtdcri(DCRN_EBC0, BnCR(1), cr.reg);
ap.reg = mfdcri(DCRN_EBC0, BnAP(1)) & EBC0_BnAP_MASK;
ap.fields.twt = 10;
ap.fields.csn = 2;
ap.fields.th = 2;
mtdcri(DCRN_EBC0, BnAP(1), ap.reg);
/* Set EBC bank 2 for the big (Linux) flash. There is 16 MB of flash,
but the CPLD decodes a 32 MB region.
Access parameters assume 90ns AMD flash @ 66.66 MHz maximum bus
speed = 6 cycle access with 2 turnaround cycles (30 ns).
NB: IBM BIOS sets this bank to burst, however bursting will never
happen in Linux because this region is mapped non-cacheable and
guarded, so it is set non-burst here. */
cr.reg = (BEECH_BANK2_PADDR & 0xfff00000) |
(mfdcri(DCRN_EBC0, BnCR(2)) & EBC0_BnCR_MASK);
cr.fields.bs = BEECH_BANK2_EBC_SIZE;
cr.fields.bu = EBC0_BnCR_BU_RW;
cr.fields.bw = EBC0_BnCR_BW_8;
mtdcri(DCRN_EBC0, BnCR(2), cr.reg);
ap.reg = mfdcri(DCRN_EBC0, BnAP(2)) & EBC0_BnAP_MASK;
ap.fields.twt = 6;
ap.fields.th = 2;
mtdcri(DCRN_EBC0, BnAP(2), ap.reg);
}
/****************************************************************************
* FPGA Setup
****************************************************************************/
/* The Beech FPGA is set up for Linux. */
static void __init
beech_fpga_setup(void)
{
volatile u8 *fpga_reg_2;
fpga_reg_2 = (volatile u8 *)
ioremap(BEECH_FPGA_REG_2_PADDR, BEECH_FPGA_REG_2_SIZE);
/* Set RTS/CTS mode for UART 1 */
*fpga_reg_2 |= FPGA_REG_2_DEFAULT_UART1_N;
}
/*
* Local variables:
* c-basic-offset: 8
* End:
*/
arch/ppc/platforms/4xx/beech.h 0 → 100755
View file @ d35cbff8
/*
* include/asm-ppc/platforms/beech.h Platform definitions for the IBM Beech
* board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2002, International Business Machines Corporation
* All Rights Reserved.
*
* Bishop Brock
* IBM Research, Austin Center for Low-Power Computing
* bcbrock@us.ibm.com
* March, 2002
*
*/
#ifdef __KERNEL__
#ifndef __ASM_BEECH_H__
#define __ASM_BEECH_H__
#include <platforms/4xx/ibm405lp.h>
#ifndef __ASSEMBLY__
/*
* Data structure defining board information maintained by the standard boot
* ROM on the IBM Beech board. An effort has been made to
* keep the field names consistent with the 8xx 'bd_t' board info
* structures.
*/
typedef struct board_info {
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned long bi_tbfreq; /* Frequency of SysTmrClk */
unsigned char bi_r_version[30]; /* Version of the IBM ROM */
unsigned int bi_memsize; /* DRAM installed, in bytes */
unsigned long sysclock_period; /* SysClk period in ns */
unsigned long sys_speed; /* SysCLk frequency in Hz */
unsigned long bi_intfreq; /* Processor speed, in Hz */
unsigned long vco_speed; /* PLL VCO speed, in Hz */
unsigned long bi_busfreq; /* PLB Bus speed, in Hz */
unsigned long opb_speed; /* OPB Bus speed, in Hz */
unsigned long ebc_speed; /* EBC Bus speed, in Hz */
} bd_t;
/* See beech.c for a concise diagram of the Beech physical memory map. */
#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
/* EBC Bank 0 controls the boot flash and SRAM */
#define BEECH_BANK0_PADDR ((uint)0xfff00000)
#define BEECH_BANK0_EBC_SIZE EBC0_BnCR_BS_1MB
#define BEECH_SRAM_PADDR BEECH_BANK0_PADDR
#define BEECH_SRAM_SIZE ((uint)(512 * 1024))
#define BEECH_BOOTFLASH_PADDR (BEECH_BANK0_PADDR + (512 * 1024))
#define BEECH_BOOTFLASH_SIZE ((uint)(512 * 1024))
/* EBC bank 1 controls the NVRAM, Ethernet and CPLD registers. The different
areas are mapped in as small an area as possible to help catch any kernel
addressing errors.
NVRAM is improperly connected on Beech Pass 1. Only every other location is
accessible. This is a 32 KB NVRAM.
The Ethernet chip maps 13 address lines. We only map the "I/O" space used by
the current driver.
The FPGA "registers" are decoded on 128 KB boundarys. Each is mapped in a
separate page. */
#define BEECH_BANK1_PADDR ((uint)0xffe00000)
#define BEECH_BANK1_EBC_SIZE EBC0_BnCR_BS_1MB
#define BEECH_NVRAM_PADDR BEECH_BANK1_PADDR
#define BEECH_NVRAM_SIZE ((uint) (32 * 1024))
#define BEECH_ETHERNET_PADDR (BEECH_BANK1_PADDR + 0x00020000)
#define BEECH_ETHERNET_SIZE ((uint) (8 * 1024))
#define BEECH_FPGA_REG_0_PADDR (BEECH_BANK1_PADDR + 0x00080000)
#define BEECH_FPGA_REG_0_SIZE PAGE_SIZE
#define BEECH_FPGA_REG_1_PADDR (BEECH_BANK1_PADDR + 0x000A0000)
#define BEECH_FPGA_REG_1_SIZE PAGE_SIZE
#define BEECH_FPGA_REG_2_PADDR (BEECH_BANK1_PADDR + 0x000C0000)
#define BEECH_FPGA_REG_2_SIZE PAGE_SIZE
#define BEECH_FPGA_REG_3_PADDR (BEECH_BANK1_PADDR + 0x000E0000)
#define BEECH_FPGA_REG_3_SIZE PAGE_SIZE
#define BEECH_FPGA_REG_4_PADDR (BEECH_BANK1_PADDR + 0x00060000)
#define BEECH_FPGA_REG_4_SIZE PAGE_SIZE
/* FPGA Register Bits (From IBM BIOS) [ May not be valid for Beech Pass 1 ]*/
#define FPGA_REG_0_FLASH_N 0x01
#define FPGA_REG_0_FLASH_ONBD_N 0x02
#define FPGA_REG_0_HITA_TOSH_N 0x04 /* New in Pass 2 */
#define FPGA_REG_0_STAT_OC 0x20
#define FPGA_REG_0_AC_SOURCE_SEL_N 0x40
#define FPGA_REG_0_AC_ACTIVE_N 0x80
#define FPGA_REG_1_USB_ACTIVE 0x01 /* New in Pass 2 */
#define FPGA_REG_1_CLK_VARIABLE 0x02
#define FPGA_REG_1_CLK_TEST 0x04
#define FPGA_REG_1_CLK_SS 0x08
#define FPGA_REG_1_EXT_IRQ_N 0x10
#define FPGA_REG_1_SMI_MODE_N 0x20
#define FPGA_REG_1_BATT_LOW_N 0x40
#define FPGA_REG_1_PCMCIA_PWR_FAULT_N 0x80
#define FPGA_REG_2_DEFAULT_UART1_N 0x01
#define FPGA_REG_2_EN_1_8V_PLL_N 0x02
#define FPGA_REG_2_PC_BUF_EN_N 0x08
#define FPGA_REG_2_CODEC_RESET_N 0x10 /* New in Pass 2 */
#define FPGA_REG_2_TP_JSTICK_N 0x20 /* New in Pass 2 */
#define FPGA_REG_3_GAS_GAUGE_IO 0x01
#define FPGA_REG_4_SDRAM_CLK3_ENAB 0x01
#define FPGA_REG_4_SDRAM_CLK2_ENAB 0x02
#define FPGA_REG_4_SDRAM_CLK1_ENAB 0x04
#define FPGA_REG_4_SDRAM_CLK0_ENAB 0x08
#define FPGA_REG_4_PCMCIA_5V 0x10 /* New in Pass 2 */
#define FPGA_REG_4_IRQ3 0x20 /* New in Pass 2 */
/* EBC Bank 2 contains the 16 MB "Linux" flash. The FPGA decodes a 32 MB
bank. The lower 16 MB are available for expansion devices. The upper 16 MB
are used for the "Linux" flash.
Partitioning information is for the benefit of the MTD driver. See
drivers/mtd/maps/ibm4xx.c. We currently allocate the lower 1 MB for a
kernel, and the other 15 MB for a filesystem.
*/
/* Bank 2 mappings changed between Beech Pass 1 and Pass 2 */
#ifdef CONFIG_BEECH_PASS1
#define BEECH_BIGFLASH_OFFSET 0
#else
#define BEECH_BIGFLASH_OFFSET (16 * 1024 * 1024)
#endif
#define BEECH_BANK2_PADDR ((uint)0xf8000000)
#define BEECH_BANK2_EBC_SIZE EBC0_BnCR_BS_32MB
#define BEECH_BIGFLASH_PADDR (BEECH_BANK2_PADDR + BEECH_BIGFLASH_OFFSET)
#define BEECH_BIGFLASH_SIZE (16 * 1024 * 1024)
#define BEECH_KERNEL_OFFSET 0
#define BEECH_KERNEL_SIZE (1 * 1024 * 1024)
#define BEECH_FREE_AREA_OFFSET BEECH_KERNEL_SIZE
#define BEECH_FREE_AREA_SIZE (BEECH_BIGFLASH_SIZE - BEECH_KERNEL_SIZE)
/* The PCMCIA controller driver 4xx_pccf.c is responsible for the EBC setup of
PCMCIA. Externally, EBC bank selects 3..7 take on PCMCIA functions when
PCMCIA is enabled. */
#define BEECH_PCMCIA_PADDR ((uint)0xf0000000)
#define BEECH_PCMCIA_SIZE ((uint)(32 * 1024 * 1024))
/* We do not currently support the internal clock mode for the UART. This
limits the minimum OPB frequency to just over 2X the UART oscillator
frequency. At OPB frequencies less than this the serial port will not
function due to the way that SerClk is sampled. */
#define PPC4xx_SERCLK_FREQ 11059200
#define BASE_BAUD (PPC4xx_SERCLK_FREQ / 16)
#define PPC4xx_MACHINE_NAME "IBM 405LP Beech"
/****************************************************************************
* Non-standard board support follows
****************************************************************************/
extern int beech_sram_free(void *p);
extern int ibm405lp_set_pixclk(unsigned pixclk_low, unsigned pixclk_high);
extern void *beech_sram_alloc(size_t size);
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_BEECH_H__ */
#endif /* __KERNEL__ */
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