Commit d3b94285 authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle

MIPS: Netlogic: Some cleanups for assembly code

No change in logic, the changes are:
* cleanup some whitespace and comments
* remove confusing argument of SYS_CPU_COHERENT_BASE macro
* make the numerical labels in macros consistent
Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6273/
parent ce59d0f7
...@@ -50,8 +50,8 @@ ...@@ -50,8 +50,8 @@
#include <asm/netlogic/xlp-hal/cpucontrol.h> #include <asm/netlogic/xlp-hal/cpucontrol.h>
#define CP0_EBASE $15 #define CP0_EBASE $15
#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ #define SYS_CPU_COHERENT_BASE CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \
SYS_CPU_NONCOHERENT_MODE * 4 SYS_CPU_NONCOHERENT_MODE * 4
/* Enable XLP features and workarounds in the LSU */ /* Enable XLP features and workarounds in the LSU */
...@@ -82,26 +82,26 @@ ...@@ -82,26 +82,26 @@
li t1, LSU_DEBUG_ADDR li t1, LSU_DEBUG_ADDR
li t2, 0 /* index */ li t2, 0 /* index */
li t3, 0x1000 /* loop count */ li t3, 0x1000 /* loop count */
1: 11:
sll v0, t2, 5 sll v0, t2, 5
mtcr zero, t0 mtcr zero, t0
ori v1, v0, 0x3 /* way0 | write_enable | write_active */ ori v1, v0, 0x3 /* way0 | write_enable | write_active */
mtcr v1, t1 mtcr v1, t1
2: 12:
mfcr v1, t1 mfcr v1, t1
andi v1, 0x1 /* wait for write_active == 0 */ andi v1, 0x1 /* wait for write_active == 0 */
bnez v1, 2b bnez v1, 12b
nop nop
mtcr zero, t0 mtcr zero, t0
ori v1, v0, 0x7 /* way1 | write_enable | write_active */ ori v1, v0, 0x7 /* way1 | write_enable | write_active */
mtcr v1, t1 mtcr v1, t1
3: 13:
mfcr v1, t1 mfcr v1, t1
andi v1, 0x1 /* wait for write_active == 0 */ andi v1, 0x1 /* wait for write_active == 0 */
bnez v1, 3b bnez v1, 13b
nop nop
addi t2, 1 addi t2, 1
bne t3, t2, 1b bne t3, t2, 11b
nop nop
.endm .endm
...@@ -149,7 +149,7 @@ FEXPORT(nlm_reset_entry) ...@@ -149,7 +149,7 @@ FEXPORT(nlm_reset_entry)
li t1, 0x1 li t1, 0x1
sll t0, t1, t0 sll t0, t1, t0
nor t0, t0, zero /* t0 <- ~(1 << core) */ nor t0, t0, zero /* t0 <- ~(1 << core) */
li t2, SYS_CPU_COHERENT_BASE(0) li t2, SYS_CPU_COHERENT_BASE
add t2, t2, t3 /* t2 <- SYS offset for node */ add t2, t2, t3 /* t2 <- SYS offset for node */
lw t1, 0(t2) lw t1, 0(t2)
and t1, t1, t0 and t1, t1, t0
...@@ -164,8 +164,7 @@ FEXPORT(nlm_reset_entry) ...@@ -164,8 +164,7 @@ FEXPORT(nlm_reset_entry)
/* FALL THROUGH */ /* FALL THROUGH */
/* /*
* Wake up sibling threads from the initial thread in * Wake up sibling threads from the initial thread in a core.
* a core.
*/ */
EXPORT(nlm_boot_siblings) EXPORT(nlm_boot_siblings)
/* core L1D flush before enable threads */ /* core L1D flush before enable threads */
...@@ -182,6 +181,8 @@ EXPORT(nlm_boot_siblings) ...@@ -182,6 +181,8 @@ EXPORT(nlm_boot_siblings)
* The new hardware thread starts at the next instruction * The new hardware thread starts at the next instruction
* For all the cases other than core 0 thread 0, we will * For all the cases other than core 0 thread 0, we will
* jump to the secondary wait function. * jump to the secondary wait function.
* NOTE: All GPR contents are lost after the mtcr above!
*/ */
mfc0 v0, CP0_EBASE, 1 mfc0 v0, CP0_EBASE, 1
andi v0, 0x3ff /* v0 <- node/core */ andi v0, 0x3ff /* v0 <- node/core */
...@@ -196,7 +197,7 @@ EXPORT(nlm_boot_siblings) ...@@ -196,7 +197,7 @@ EXPORT(nlm_boot_siblings)
#endif #endif
mtc0 t1, CP0_STATUS mtc0 t1, CP0_STATUS
/* mark CPU ready, careful here, previous mtcr trashed registers */ /* mark CPU ready */
li t3, CKSEG1ADDR(RESET_DATA_PHYS) li t3, CKSEG1ADDR(RESET_DATA_PHYS)
ADDIU t1, t3, BOOT_CPU_READY ADDIU t1, t3, BOOT_CPU_READY
sll v1, v0, 2 sll v1, v0, 2
......
...@@ -133,6 +133,7 @@ NESTED(nlm_rmiboot_preboot, 16, sp) ...@@ -133,6 +133,7 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
or t1, t2, v1 /* put in new value */ or t1, t2, v1 /* put in new value */
mtcr t1, t0 /* update core control */ mtcr t1, t0 /* update core control */
/* wait for NMI to hit */
1: wait 1: wait
b 1b b 1b
nop nop
......
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