Commit d52ea3dc authored by Tim Huang's avatar Tim Huang Committed by Alex Deucher

drm/amdgpu/pm: correct the firmware flag address for SMU IP v13.0.4

For SMU IP v13.0.4, the smnMP1_FIRMWARE_FLAGS address is different,
we need this to correct the reading address.
Signed-off-by: default avatarTim Huang <tim.huang@amd.com>
Reviewed-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5089c4a8
...@@ -43,6 +43,7 @@ ...@@ -43,6 +43,7 @@
/* address block */ /* address block */
#define smnMP1_FIRMWARE_FLAGS 0x3010024 #define smnMP1_FIRMWARE_FLAGS 0x3010024
#define smnMP1_V13_0_4_FIRMWARE_FLAGS 0x3010028
#define smnMP0_FW_INTF 0x30101c0 #define smnMP0_FW_INTF 0x30101c0
#define smnMP1_PUB_CTRL 0x3010b14 #define smnMP1_PUB_CTRL 0x3010b14
......
...@@ -273,8 +273,16 @@ int smu_v13_0_check_fw_status(struct smu_context *smu) ...@@ -273,8 +273,16 @@ int smu_v13_0_check_fw_status(struct smu_context *smu)
struct amdgpu_device *adev = smu->adev; struct amdgpu_device *adev = smu->adev;
uint32_t mp1_fw_flags; uint32_t mp1_fw_flags;
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 4):
mp1_fw_flags = RREG32_PCIE(MP1_Public |
(smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
break;
default:
mp1_fw_flags = RREG32_PCIE(MP1_Public | mp1_fw_flags = RREG32_PCIE(MP1_Public |
(smnMP1_FIRMWARE_FLAGS & 0xffffffff)); (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
break;
}
if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
......
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