Commit d6e6d562 authored by Michael Shych's avatar Michael Shych Committed by Wim Van Sebroeck

docs: watchdog: mlx-wdt: Add description of new watchdog type 3

Add documentation with details of new type of Mellanox watchdog driver.
Signed-off-by: default avatarMichael Shych <michaelsh@mellanox.com>
Reviewed-by: default avatarVadim Pasternak <vadimp@mellanox.com>
Acked-by: default avatarGuenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20200504141427.17685-5-michaelsh@mellanox.comSigned-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarWim Van Sebroeck <wim@linux-watchdog.org>
parent eee85114
...@@ -24,10 +24,19 @@ Type 2: ...@@ -24,10 +24,19 @@ Type 2:
Maximum timeout is 255 sec. Maximum timeout is 255 sec.
Get time-left is supported. Get time-left is supported.
Type 3:
Same as Type 2 with extended maximum timeout period.
Maximum timeout is 65535 sec.
Type 1 HW watchdog implementation exist in old systems and Type 1 HW watchdog implementation exist in old systems and
all new systems have type 2 HW watchdog. all new systems have type 2 HW watchdog.
Two types of HW implementation have also different register map. Two types of HW implementation have also different register map.
Type 3 HW watchdog implementation can exist on all Mellanox systems
with new programmer logic device.
It's differentiated by WD capability bit.
Old systems still have only one main watchdog.
Mellanox system can have 2 watchdogs: main and auxiliary. Mellanox system can have 2 watchdogs: main and auxiliary.
Main and auxiliary watchdog devices can be enabled together Main and auxiliary watchdog devices can be enabled together
on the same system. on the same system.
...@@ -54,3 +63,4 @@ The driver checks during initialization if the previous system reset ...@@ -54,3 +63,4 @@ The driver checks during initialization if the previous system reset
was done by the watchdog. If yes, it makes a notification about this event. was done by the watchdog. If yes, it makes a notification about this event.
Access to HW registers is performed through a generic regmap interface. Access to HW registers is performed through a generic regmap interface.
Programmable logic device registers have little-endian order.
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