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Commit d8b02dbb authored by Ben Skeggs's avatar Ben Skeggs
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drm/nvc0/gr: update initial register/context values 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 37c3afd0
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Inline Side-by-side
Showing with 1042 additions and 544 deletions
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
View file @ d8b02dbb
...@@ -1325,6 +1325,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv) ...@@ -1325,6 +1325,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv)
nv_mthd(priv, 0x9097, 0x0214, 0x00000000); nv_mthd(priv, 0x9097, 0x0214, 0x00000000);
switch (nv_device(priv)->chipset) { switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xd9: case 0xd9:
case 0xd7: case 0xd7:
break; break;
...@@ -1471,6 +1472,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) ...@@ -1471,6 +1472,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x40402c, 0x00000000); nv_wr32(priv, 0x40402c, 0x00000000);
break; break;
case 0xc0:
default: default:
break; break;
} }
...@@ -1490,6 +1492,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) ...@@ -1490,6 +1492,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x4040c4, 0x00000000); nv_wr32(priv, 0x4040c4, 0x00000000);
nv_wr32(priv, 0x4040c8, 0xf0000087); nv_wr32(priv, 0x4040c8, 0xf0000087);
switch (nv_device(priv)->chipset) { switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xd9: case 0xd9:
case 0xd7: case 0xd7:
nv_wr32(priv, 0x4040d0, 0x00000000); nv_wr32(priv, 0x4040d0, 0x00000000);
...@@ -1516,6 +1519,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) ...@@ -1516,6 +1519,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
case 0xd9: case 0xd9:
case 0xd7: case 0xd7:
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x404174, 0x00000000); nv_wr32(priv, 0x404174, 0x00000000);
break; break;
...@@ -1645,20 +1649,24 @@ nvc0_grctx_generate_unk47xx(struct nvc0_graph_priv *priv) ...@@ -1645,20 +1649,24 @@ nvc0_grctx_generate_unk47xx(struct nvc0_graph_priv *priv)
static void static void
nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv) nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv)
{ {
switch (nv_device(priv)->chipset) {
if (nv_device(priv)->chipset >= 0xd0) { case 0xc1:
nv_wr32(priv, 0x405800, 0x0f8000bf); nv_wr32(priv, 0x405800, 0x0f8000bf);
nv_wr32(priv, 0x405830, 0x02180218); nv_wr32(priv, 0x405830, 0x02180218);
nv_wr32(priv, 0x405834, 0x08000000); nv_wr32(priv, 0x405834, 0x00000000);
} else break;
if (nv_device(priv)->chipset == 0xc1) { case 0xd9:
case 0xd7:
nv_wr32(priv, 0x405800, 0x0f8000bf); nv_wr32(priv, 0x405800, 0x0f8000bf);
nv_wr32(priv, 0x405830, 0x02180218); nv_wr32(priv, 0x405830, 0x02180218);
nv_wr32(priv, 0x405834, 0x00000000); nv_wr32(priv, 0x405834, 0x08000000);
} else { break;
case 0xc0:
default:
nv_wr32(priv, 0x405800, 0x078000bf); nv_wr32(priv, 0x405800, 0x078000bf);
nv_wr32(priv, 0x405830, 0x02180000); nv_wr32(priv, 0x405830, 0x02180000);
nv_wr32(priv, 0x405834, 0x00000000); nv_wr32(priv, 0x405834, 0x00000000);
break;
} }
nv_wr32(priv, 0x405838, 0x00000000); nv_wr32(priv, 0x405838, 0x00000000);
nv_wr32(priv, 0x405854, 0x00000000); nv_wr32(priv, 0x405854, 0x00000000);
...@@ -1694,6 +1702,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv) ...@@ -1694,6 +1702,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x4064bc, 0x00000000); nv_wr32(priv, 0x4064bc, 0x00000000);
break; break;
case 0xc0:
default: default:
break; break;
} }
...@@ -1704,6 +1713,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv) ...@@ -1704,6 +1713,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x4064c0, 0x80140078); nv_wr32(priv, 0x4064c0, 0x80140078);
nv_wr32(priv, 0x4064c4, 0x0086ffff); nv_wr32(priv, 0x4064c4, 0x0086ffff);
break; break;
case 0xc0:
default: default:
break; break;
} }
...@@ -1742,6 +1752,12 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv) ...@@ -1742,6 +1752,12 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x408800, 0x02802a3c); nv_wr32(priv, 0x408800, 0x02802a3c);
nv_wr32(priv, 0x408804, 0x00000040); nv_wr32(priv, 0x408804, 0x00000040);
switch (nv_device(priv)->chipset) { switch (nv_device(priv)->chipset) {
case 0xc0:
nv_wr32(priv, 0x408808, 0x0003e00d);
nv_wr32(priv, 0x408900, 0x3080b801);
nv_wr32(priv, 0x408904, 0x02000001);
nv_wr32(priv, 0x408908, 0x00c80929);
break;
case 0xc1: case 0xc1:
nv_wr32(priv, 0x408808, 0x1003e005); nv_wr32(priv, 0x408808, 0x1003e005);
nv_wr32(priv, 0x408900, 0x3080b801); nv_wr32(priv, 0x408900, 0x3080b801);
...@@ -1780,6 +1796,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) ...@@ -1780,6 +1796,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xd9: case 0xd9:
case 0xd7: case 0xd7:
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x418408, 0x00000000); nv_wr32(priv, 0x418408, 0x00000000);
break; break;
...@@ -1791,6 +1808,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) ...@@ -1791,6 +1808,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x418414, 0x02200fff); nv_wr32(priv, 0x418414, 0x02200fff);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x418414, 0x00200fff); nv_wr32(priv, 0x418414, 0x00200fff);
break; break;
...@@ -1814,6 +1832,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) ...@@ -1814,6 +1832,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x41870c, 0x00000000); nv_wr32(priv, 0x41870c, 0x00000000);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x41870c, 0x07c80000); nv_wr32(priv, 0x41870c, 0x07c80000);
break; break;
...@@ -1824,6 +1843,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) ...@@ -1824,6 +1843,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x418800, 0x7006860a); nv_wr32(priv, 0x418800, 0x7006860a);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x418800, 0x0006860a); nv_wr32(priv, 0x418800, 0x0006860a);
break; break;
...@@ -1838,6 +1858,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) ...@@ -1838,6 +1858,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x418830, 0x10000001); nv_wr32(priv, 0x418830, 0x10000001);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x418830, 0x00000001); nv_wr32(priv, 0x418830, 0x00000001);
break; break;
...@@ -1857,6 +1878,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) ...@@ -1857,6 +1878,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x4188fc, 0x20100008); nv_wr32(priv, 0x4188fc, 0x20100008);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x4188fc, 0x00100000); nv_wr32(priv, 0x4188fc, 0x00100000);
break; break;
...@@ -1879,6 +1901,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) ...@@ -1879,6 +1901,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x418b00, 0x00000006); nv_wr32(priv, 0x418b00, 0x00000006);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x418b00, 0x00000000); nv_wr32(priv, 0x418b00, 0x00000000);
break; break;
...@@ -1905,6 +1928,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) ...@@ -1905,6 +1928,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x418c6c, 0x00000001); nv_wr32(priv, 0x418c6c, 0x00000001);
break; break;
case 0xc0:
default: default:
break; break;
} }
...@@ -1929,6 +1953,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) ...@@ -1929,6 +1953,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x419864, 0x00000129); nv_wr32(priv, 0x419864, 0x00000129);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x419864, 0x0000012a); nv_wr32(priv, 0x419864, 0x0000012a);
break; break;
...@@ -1940,8 +1965,14 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) ...@@ -1940,8 +1965,14 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419a0c, 0x00020000); nv_wr32(priv, 0x419a0c, 0x00020000);
nv_wr32(priv, 0x419a10, 0x00000000); nv_wr32(priv, 0x419a10, 0x00000000);
nv_wr32(priv, 0x419a14, 0x00000200); nv_wr32(priv, 0x419a14, 0x00000200);
switch (nv_device(priv)->chipset) {
case 0xc0:
break;
default:
nv_wr32(priv, 0x419a1c, 0x00000000); nv_wr32(priv, 0x419a1c, 0x00000000);
nv_wr32(priv, 0x419a20, 0x00000800); nv_wr32(priv, 0x419a20, 0x00000800);
break;
}
switch (nv_device(priv)->chipset) { switch (nv_device(priv)->chipset) {
case 0xc0: case 0xc0:
case 0xc8: case 0xc8:
...@@ -1967,6 +1998,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) ...@@ -1967,6 +1998,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x419be0, 0x00400001); nv_wr32(priv, 0x419be0, 0x00400001);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x419be0, 0x00000001); nv_wr32(priv, 0x419be0, 0x00000001);
break; break;
...@@ -1977,6 +2009,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) ...@@ -1977,6 +2009,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x419c00, 0x0000000a); nv_wr32(priv, 0x419c00, 0x0000000a);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x419c00, 0x00000002); nv_wr32(priv, 0x419c00, 0x00000002);
break; break;
...@@ -1995,6 +2028,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) ...@@ -1995,6 +2028,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419c28, 0x3cf3cf3c); nv_wr32(priv, 0x419c28, 0x3cf3cf3c);
nv_wr32(priv, 0x419cb0, 0x00020048); nv_wr32(priv, 0x419cb0, 0x00020048);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x419cb0, 0x00060048); nv_wr32(priv, 0x419cb0, 0x00060048);
break; break;
...@@ -2007,6 +2041,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) ...@@ -2007,6 +2041,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x419d20, 0x12180000); nv_wr32(priv, 0x419d20, 0x12180000);
break; break;
case 0xc0:
default: default:
nv_wr32(priv, 0x419d20, 0x02180000); nv_wr32(priv, 0x419d20, 0x02180000);
break; break;
...@@ -2018,6 +2053,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) ...@@ -2018,6 +2053,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_wr32(priv, 0x419d44, 0x02180218); nv_wr32(priv, 0x419d44, 0x02180218);
break; break;
case 0xc0:
default: default:
break; break;
} }
...@@ -2399,6 +2435,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) ...@@ -2399,6 +2435,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
for (i = 0x400; i <= 0x417; i++) for (i = 0x400; i <= 0x417; i++)
nv_icmd(priv, i, 0x00000040); nv_icmd(priv, i, 0x00000040);
break; break;
case 0xc0:
default: default:
break; break;
} }
...@@ -2416,6 +2453,8 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) ...@@ -2416,6 +2453,8 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
for (i = 0x440; i <= 0x457; i++) for (i = 0x440; i <= 0x457; i++)
nv_icmd(priv, i, 0x0000c080); nv_icmd(priv, i, 0x0000c080);
break; break;
case 0xc0:
break;
default: default:
break; break;
} }
...@@ -2986,6 +3025,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) ...@@ -2986,6 +3025,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_icmd(priv, 0x0000057b, 0x00000059); nv_icmd(priv, 0x0000057b, 0x00000059);
break; break;
case 0xc0:
default: default:
break; break;
} }
...@@ -3094,6 +3134,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) ...@@ -3094,6 +3134,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
case 0xd7: case 0xd7:
nv_icmd(priv, 0x0000097d, 0x00000020); nv_icmd(priv, 0x0000097d, 0x00000020);
break; break;
case 0xc0:
default: default:
break; break;
} }
...@@ -3240,6 +3281,9 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) ...@@ -3240,6 +3281,9 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
nvc0_grctx_generate_90c0(priv); nvc0_grctx_generate_90c0(priv);
switch (nv_device(priv)->chipset) { switch (nv_device(priv)->chipset) {
case 0xc0:
nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
break;
case 0xd9: case 0xd9:
case 0xd7: case 0xd7:
nv_mthd(priv, 0x902d, 0x3410, 0x80002006); nv_mthd(priv, 0x902d, 0x3410, 0x80002006);
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
View file @ d8b02dbb
...@@ -48,10 +48,10 @@ cmd_queue: queue_init ...@@ -48,10 +48,10 @@ cmd_queue: queue_init
// chipset descriptions // chipset descriptions
chipsets: chipsets:
.b8 0xc0 0 0 0 .b8 0xc0 0 0 0
.b16 #nvc0_gpc_mmio_head .b16 #nnvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail .b16 #nnvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head .b16 #nnvc0_tpc_mmio_head
.b16 #nvc0_tpc_mmio_tail .b16 #nnvc0_tpc_mmio_tail
.b8 0xc1 0 0 0 .b8 0xc1 0 0 0
.b16 #nvc0_gpc_mmio_head .b16 #nvc0_gpc_mmio_head
.b16 #nvc1_gpc_mmio_tail .b16 #nvc1_gpc_mmio_tail
...@@ -124,6 +124,33 @@ nvc0_gpc_mmio_tail: ...@@ -124,6 +124,33 @@ nvc0_gpc_mmio_tail:
mmctx_data(0x000c6c, 1); mmctx_data(0x000c6c, 1);
nvc1_gpc_mmio_tail: nvc1_gpc_mmio_tail:
nnvc0_gpc_mmio_head:
mmctx_data(0x000380, 1)
mmctx_data(0x000400, 6)
mmctx_data(0x000450, 9)
mmctx_data(0x000600, 1)
mmctx_data(0x000684, 1)
mmctx_data(0x000700, 5)
mmctx_data(0x000800, 1)
mmctx_data(0x000808, 3)
mmctx_data(0x000828, 1)
mmctx_data(0x000830, 1)
mmctx_data(0x0008d8, 1)
mmctx_data(0x0008e0, 1)
mmctx_data(0x0008e8, 6)
mmctx_data(0x00091c, 1)
mmctx_data(0x000924, 3)
mmctx_data(0x000b00, 1)
mmctx_data(0x000b08, 6)
mmctx_data(0x000bb8, 1)
mmctx_data(0x000c08, 1)
mmctx_data(0x000c10, 8)
mmctx_data(0x000c80, 1)
mmctx_data(0x000c8c, 1)
mmctx_data(0x001000, 3)
mmctx_data(0x001014, 1)
nnvc0_gpc_mmio_tail:
nvd9_gpc_mmio_head: nvd9_gpc_mmio_head:
mmctx_data(0x000380, 1) mmctx_data(0x000380, 1)
mmctx_data(0x000400, 2) mmctx_data(0x000400, 2)
...@@ -185,6 +212,28 @@ nvc3_tpc_mmio_tail: ...@@ -185,6 +212,28 @@ nvc3_tpc_mmio_tail:
mmctx_data(0x000544, 1) mmctx_data(0x000544, 1)
nvc1_tpc_mmio_tail: nvc1_tpc_mmio_tail:
nnvc0_tpc_mmio_head:
mmctx_data(0x000018, 1)
mmctx_data(0x00003c, 1)
mmctx_data(0x000048, 1)
mmctx_data(0x000064, 1)
mmctx_data(0x000088, 1)
mmctx_data(0x000200, 6)
mmctx_data(0x000300, 6)
mmctx_data(0x0003d0, 1)
mmctx_data(0x0003e0, 2)
mmctx_data(0x000400, 3)
mmctx_data(0x000420, 1)
mmctx_data(0x0004b0, 1)
mmctx_data(0x0004e8, 1)
mmctx_data(0x0004f4, 1)
mmctx_data(0x000520, 2)
mmctx_data(0x000604, 4)
mmctx_data(0x000644, 20)
mmctx_data(0x000698, 1)
mmctx_data(0x000750, 2)
nnvc0_tpc_mmio_tail:
nvd9_tpc_mmio_head: nvd9_tpc_mmio_head:
mmctx_data(0x000018, 1) mmctx_data(0x000018, 1)
mmctx_data(0x00003c, 1) mmctx_data(0x00003c, 1)
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
View file @ d8b02dbb
...@@ -34,32 +34,32 @@ uint32_t nvc0_grgpc_data[] = { ...@@ -34,32 +34,32 @@ uint32_t nvc0_grgpc_data[] = {
0x00000000, 0x00000000,
/* 0x0064: chipsets */ /* 0x0064: chipsets */
0x000000c0, 0x000000c0,
0x013400d4, 0x01980138,
0x01f001a0, 0x02b00264,
0x000000c1, 0x000000c1,
0x013800d4, 0x013800d4,
0x020401a0, 0x02640200,
0x000000c3, 0x000000c3,
0x013400d4, 0x013400d4,
0x020001a0, 0x02600200,
0x000000c4, 0x000000c4,
0x013400d4, 0x013400d4,
0x020001a0, 0x02600200,
0x000000c8, 0x000000c8,
0x013400d4, 0x013400d4,
0x01f001a0, 0x02500200,
0x000000ce, 0x000000ce,
0x013400d4, 0x013400d4,
0x020001a0, 0x02600200,
0x000000cf, 0x000000cf,
0x013400d4, 0x013400d4,
0x01fc01a0, 0x025c0200,
0x000000d9, 0x000000d9,
0x01a00138, 0x02000198,
0x02600204, 0x030c02b0,
0x000000d7, 0x000000d7,
0x01a00138, 0x02000198,
0x02600204, 0x030c02b0,
0x00000000, 0x00000000,
/* 0x00d4: nvc0_gpc_mmio_head */ /* 0x00d4: nvc0_gpc_mmio_head */
0x00000380, 0x00000380,
...@@ -89,7 +89,33 @@ uint32_t nvc0_grgpc_data[] = { ...@@ -89,7 +89,33 @@ uint32_t nvc0_grgpc_data[] = {
/* 0x0134: nvc0_gpc_mmio_tail */ /* 0x0134: nvc0_gpc_mmio_tail */
0x00000c6c, 0x00000c6c,
/* 0x0138: nvc1_gpc_mmio_tail */ /* 0x0138: nvc1_gpc_mmio_tail */
/* 0x0138: nvd9_gpc_mmio_head */ /* 0x0138: nnvc0_gpc_mmio_head */
0x00000380,
0x14000400,
0x20000450,
0x00000600,
0x00000684,
0x10000700,
0x00000800,
0x08000808,
0x00000828,
0x00000830,
0x000008d8,
0x000008e0,
0x140008e8,
0x0000091c,
0x08000924,
0x00000b00,
0x14000b08,
0x00000bb8,
0x00000c08,
0x1c000c10,
0x00000c80,
0x00000c8c,
0x08001000,
0x00001014,
/* 0x0198: nnvc0_gpc_mmio_tail */
/* 0x0198: nvd9_gpc_mmio_head */
0x00000380, 0x00000380,
0x04000400, 0x04000400,
0x0800040c, 0x0800040c,
...@@ -116,8 +142,8 @@ uint32_t nvc0_grgpc_data[] = { ...@@ -116,8 +142,8 @@ uint32_t nvc0_grgpc_data[] = {
0x00000c8c, 0x00000c8c,
0x08001000, 0x08001000,
0x00001014, 0x00001014,
/* 0x01a0: nvd9_gpc_mmio_tail */ /* 0x0200: nvd9_gpc_mmio_tail */
/* 0x01a0: nvc0_tpc_mmio_head */ /* 0x0200: nvc0_tpc_mmio_head */
0x00000018, 0x00000018,
0x0000003c, 0x0000003c,
0x00000048, 0x00000048,
...@@ -138,16 +164,37 @@ uint32_t nvc0_grgpc_data[] = { ...@@ -138,16 +164,37 @@ uint32_t nvc0_grgpc_data[] = {
0x4c000644, 0x4c000644,
0x00000698, 0x00000698,
0x04000750, 0x04000750,
/* 0x01f0: nvc0_tpc_mmio_tail */ /* 0x0250: nvc0_tpc_mmio_tail */
0x00000758, 0x00000758,
0x000002c4, 0x000002c4,
0x000006e0, 0x000006e0,
/* 0x01fc: nvcf_tpc_mmio_tail */ /* 0x025c: nvcf_tpc_mmio_tail */
0x000004bc, 0x000004bc,
/* 0x0200: nvc3_tpc_mmio_tail */ /* 0x0260: nvc3_tpc_mmio_tail */
0x00000544, 0x00000544,
/* 0x0204: nvc1_tpc_mmio_tail */ /* 0x0264: nvc1_tpc_mmio_tail */
/* 0x0204: nvd9_tpc_mmio_head */ /* 0x0264: nnvc0_tpc_mmio_head */
0x00000018,
0x0000003c,
0x00000048,
0x00000064,
0x00000088,
0x14000200,
0x14000300,
0x000003d0,
0x040003e0,
0x08000400,
0x00000420,
0x000004b0,
0x000004e8,
0x000004f4,
0x04000520,
0x0c000604,
0x4c000644,
0x00000698,
0x04000750,
/* 0x02b0: nnvc0_tpc_mmio_tail */
/* 0x02b0: nvd9_tpc_mmio_head */
0x00000018, 0x00000018,
0x0000003c, 0x0000003c,
0x00000048, 0x00000048,
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
View file @ d8b02dbb
...@@ -37,10 +37,19 @@ hub_mmio_list_tail: .b32 0 ...@@ -37,10 +37,19 @@ hub_mmio_list_tail: .b32 0
ctx_current: .b32 0 ctx_current: .b32 0
.align 256
chan_data:
chan_mmio_count: .b32 0
chan_mmio_address: .b32 0
.align 256
xfer_data: .b32 0
.align 256
chipsets: chipsets:
.b8 0xc0 0 0 0 .b8 0xc0 0 0 0
.b16 #nvc0_hub_mmio_head .b16 #nnvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail .b16 #nnvc0_hub_mmio_tail
.b8 0xc1 0 0 0 .b8 0xc1 0 0 0
.b16 #nvc0_hub_mmio_head .b16 #nvc0_hub_mmio_head
.b16 #nvc1_hub_mmio_tail .b16 #nvc1_hub_mmio_tail
...@@ -111,6 +120,48 @@ nvc0_hub_mmio_tail: ...@@ -111,6 +120,48 @@ nvc0_hub_mmio_tail:
mmctx_data(0x4064c0, 2) mmctx_data(0x4064c0, 2)
nvc1_hub_mmio_tail: nvc1_hub_mmio_tail:
nnvc0_hub_mmio_head:
mmctx_data(0x17e91c, 2)
mmctx_data(0x400204, 2)
mmctx_data(0x404004, 11)
mmctx_data(0x404044, 1)
mmctx_data(0x404094, 14)
mmctx_data(0x4040d0, 7)
mmctx_data(0x4040f8, 1)
mmctx_data(0x404130, 3)
mmctx_data(0x404150, 3)
mmctx_data(0x404164, 2)
mmctx_data(0x404174, 3)
mmctx_data(0x404200, 8)
mmctx_data(0x404404, 14)
mmctx_data(0x404460, 4)
mmctx_data(0x404480, 1)
mmctx_data(0x404498, 1)
mmctx_data(0x404604, 4)
mmctx_data(0x404618, 32)
mmctx_data(0x404698, 21)
mmctx_data(0x4046f0, 2)
mmctx_data(0x404700, 22)
mmctx_data(0x405800, 1)
mmctx_data(0x405830, 3)
mmctx_data(0x405854, 1)
mmctx_data(0x405870, 4)
mmctx_data(0x405a00, 2)
mmctx_data(0x405a18, 1)
mmctx_data(0x406020, 1)
mmctx_data(0x406028, 4)
mmctx_data(0x4064a8, 2)
mmctx_data(0x4064b4, 2)
mmctx_data(0x407804, 1)
mmctx_data(0x40780c, 6)
mmctx_data(0x4078bc, 1)
mmctx_data(0x408000, 7)
mmctx_data(0x408064, 1)
mmctx_data(0x408800, 3)
mmctx_data(0x408900, 3)
mmctx_data(0x408980, 1)
nnvc0_hub_mmio_tail:
nvd9_hub_mmio_head: nvd9_hub_mmio_head:
mmctx_data(0x17e91c, 2) mmctx_data(0x17e91c, 2)
mmctx_data(0x400204, 2) mmctx_data(0x400204, 2)
...@@ -153,14 +204,6 @@ mmctx_data(0x408900, 3) ...@@ -153,14 +204,6 @@ mmctx_data(0x408900, 3)
mmctx_data(0x408980, 1) mmctx_data(0x408980, 1)
nvd9_hub_mmio_tail: nvd9_hub_mmio_tail:
.align 256
chan_data:
chan_mmio_count: .b32 0
chan_mmio_address: .b32 0
.align 256
xfer_data: .b32 0
.section #nvc0_grhub_code .section #nvc0_grhub_code
bra #init bra #init
define(`include_code') define(`include_code')
......
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View file @ d8b02dbb
...@@ -745,9 +745,17 @@ nvc0_graph_init_unk60xx(struct nvc0_graph_priv *priv) ...@@ -745,9 +745,17 @@ nvc0_graph_init_unk60xx(struct nvc0_graph_priv *priv)
static void static void
nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv) nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
{ {
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x4064f0, 0x00000000); nv_wr32(priv, 0x4064f0, 0x00000000);
nv_wr32(priv, 0x4064f4, 0x00000000); nv_wr32(priv, 0x4064f4, 0x00000000);
nv_wr32(priv, 0x4064f8, 0x00000000); nv_wr32(priv, 0x4064f8, 0x00000000);
break;
case 0xc0:
default:
break;
}
} }
static void static void
...@@ -755,10 +763,26 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv) ...@@ -755,10 +763,26 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
{ {
nv_wr32(priv, 0x405844, 0x00ffffff); nv_wr32(priv, 0x405844, 0x00ffffff);
nv_wr32(priv, 0x405850, 0x00000000); nv_wr32(priv, 0x405850, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x405900, 0x00002834); nv_wr32(priv, 0x405900, 0x00002834);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x405908, 0x00000000); nv_wr32(priv, 0x405908, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x405928, 0x00000000); nv_wr32(priv, 0x405928, 0x00000000);
nv_wr32(priv, 0x40592c, 0x00000000); nv_wr32(priv, 0x40592c, 0x00000000);
break;
case 0xc0:
default:
break;
}
} }
static void static void
...@@ -770,19 +794,53 @@ nvc0_graph_init_unk80xx(struct nvc0_graph_priv *priv) ...@@ -770,19 +794,53 @@ nvc0_graph_init_unk80xx(struct nvc0_graph_priv *priv)
static void static void
nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
{ {
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x418408, 0x00000000); nv_wr32(priv, 0x418408, 0x00000000);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x4184a0, 0x00000000); nv_wr32(priv, 0x4184a0, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x4184a4, 0x00000000); nv_wr32(priv, 0x4184a4, 0x00000000);
nv_wr32(priv, 0x4184a8, 0x00000000); nv_wr32(priv, 0x4184a8, 0x00000000);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x418604, 0x00000000); nv_wr32(priv, 0x418604, 0x00000000);
nv_wr32(priv, 0x418680, 0x00000000); nv_wr32(priv, 0x418680, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x418714, 0x00000000); nv_wr32(priv, 0x418714, 0x00000000);
break;
case 0xc0:
default:
nv_wr32(priv, 0x418714, 0x80000000);
break;
}
nv_wr32(priv, 0x418384, 0x00000000); nv_wr32(priv, 0x418384, 0x00000000);
nv_wr32(priv, 0x418814, 0x00000000); nv_wr32(priv, 0x418814, 0x00000000);
nv_wr32(priv, 0x418818, 0x00000000); nv_wr32(priv, 0x418818, 0x00000000);
nv_wr32(priv, 0x41881c, 0x00000000); nv_wr32(priv, 0x41881c, 0x00000000);
nv_wr32(priv, 0x418b04, 0x00000000); nv_wr32(priv, 0x418b04, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x4188c8, 0x00000000); nv_wr32(priv, 0x4188c8, 0x00000000);
break;
case 0xc0:
default:
nv_wr32(priv, 0x4188c8, 0x80000000);
break;
}
nv_wr32(priv, 0x4188cc, 0x00000000); nv_wr32(priv, 0x4188cc, 0x00000000);
nv_wr32(priv, 0x4188d0, 0x00010000); nv_wr32(priv, 0x4188d0, 0x00010000);
nv_wr32(priv, 0x4188d4, 0x00000001); nv_wr32(priv, 0x4188d4, 0x00000001);
...@@ -794,22 +852,63 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) ...@@ -794,22 +852,63 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x418988, 0x77777777); nv_wr32(priv, 0x418988, 0x77777777);
nv_wr32(priv, 0x41898c, 0x77777777); nv_wr32(priv, 0x41898c, 0x77777777);
nv_wr32(priv, 0x418c04, 0x00000000); nv_wr32(priv, 0x418c04, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x418c64, 0x00000000); nv_wr32(priv, 0x418c64, 0x00000000);
nv_wr32(priv, 0x418c68, 0x00000000); nv_wr32(priv, 0x418c68, 0x00000000);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x418c88, 0x00000000); nv_wr32(priv, 0x418c88, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x418cb4, 0x00000000); nv_wr32(priv, 0x418cb4, 0x00000000);
nv_wr32(priv, 0x418cb8, 0x00000000); nv_wr32(priv, 0x418cb8, 0x00000000);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x418d00, 0x00000000); nv_wr32(priv, 0x418d00, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x418d28, 0x00000000); nv_wr32(priv, 0x418d28, 0x00000000);
nv_wr32(priv, 0x418d2c, 0x00000000); nv_wr32(priv, 0x418d2c, 0x00000000);
nv_wr32(priv, 0x418f00, 0x00000000); nv_wr32(priv, 0x418f00, 0x00000000);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x418f08, 0x00000000); nv_wr32(priv, 0x418f08, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x418f20, 0x00000000); nv_wr32(priv, 0x418f20, 0x00000000);
nv_wr32(priv, 0x418f24, 0x00000000); nv_wr32(priv, 0x418f24, 0x00000000);
nv_wr32(priv, 0x418e00, 0x00000003); nv_wr32(priv, 0x418e00, 0x00000003);
break;
case 0xc0:
default:
nv_wr32(priv, 0x418e00, 0x00000050);
break;
}
nv_wr32(priv, 0x418e08, 0x00000000); nv_wr32(priv, 0x418e08, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x418e1c, 0x00000000); nv_wr32(priv, 0x418e1c, 0x00000000);
nv_wr32(priv, 0x418e20, 0x00000000); nv_wr32(priv, 0x418e20, 0x00000000);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x41900c, 0x00000000); nv_wr32(priv, 0x41900c, 0x00000000);
nv_wr32(priv, 0x419018, 0x00000000); nv_wr32(priv, 0x419018, 0x00000000);
} }
...@@ -821,21 +920,64 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) ...@@ -821,21 +920,64 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419d0c, 0x00000000); nv_wr32(priv, 0x419d0c, 0x00000000);
nv_wr32(priv, 0x419d10, 0x00000014); nv_wr32(priv, 0x419d10, 0x00000014);
nv_wr32(priv, 0x419ab0, 0x00000000); nv_wr32(priv, 0x419ab0, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419ac8, 0x00000000); nv_wr32(priv, 0x419ac8, 0x00000000);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x419ab8, 0x000000e7); nv_wr32(priv, 0x419ab8, 0x000000e7);
nv_wr32(priv, 0x419abc, 0x00000000); nv_wr32(priv, 0x419abc, 0x00000000);
nv_wr32(priv, 0x419ac0, 0x00000000); nv_wr32(priv, 0x419ac0, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419ab4, 0x00000000); nv_wr32(priv, 0x419ab4, 0x00000000);
nv_wr32(priv, 0x41980c, 0x00000010); nv_wr32(priv, 0x41980c, 0x00000010);
break;
case 0xc0:
default:
nv_wr32(priv, 0x41980c, 0x00000000);
break;
}
nv_wr32(priv, 0x419810, 0x00000000); nv_wr32(priv, 0x419810, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419814, 0x00000004); nv_wr32(priv, 0x419814, 0x00000004);
break;
case 0xc0:
default:
nv_wr32(priv, 0x419814, 0x00000000);
break;
}
nv_wr32(priv, 0x419844, 0x00000000); nv_wr32(priv, 0x419844, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x41984c, 0x0000a918); nv_wr32(priv, 0x41984c, 0x0000a918);
break;
case 0xc0:
default:
nv_wr32(priv, 0x41984c, 0x00005bc5);
break;
}
nv_wr32(priv, 0x419850, 0x00000000); nv_wr32(priv, 0x419850, 0x00000000);
nv_wr32(priv, 0x419854, 0x00000000); nv_wr32(priv, 0x419854, 0x00000000);
nv_wr32(priv, 0x419858, 0x00000000); nv_wr32(priv, 0x419858, 0x00000000);
nv_wr32(priv, 0x41985c, 0x00000000); nv_wr32(priv, 0x41985c, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419880, 0x00000002); nv_wr32(priv, 0x419880, 0x00000002);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x419c98, 0x00000000); nv_wr32(priv, 0x419c98, 0x00000000);
nv_wr32(priv, 0x419ca8, 0x80000000); nv_wr32(priv, 0x419ca8, 0x80000000);
nv_wr32(priv, 0x419cb4, 0x00000000); nv_wr32(priv, 0x419cb4, 0x00000000);
...@@ -845,25 +987,60 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) ...@@ -845,25 +987,60 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419cc4, 0x00000000); nv_wr32(priv, 0x419cc4, 0x00000000);
nv_wr32(priv, 0x419bd4, 0x00800000); nv_wr32(priv, 0x419bd4, 0x00800000);
nv_wr32(priv, 0x419bdc, 0x00000000); nv_wr32(priv, 0x419bdc, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419bf8, 0x00000000); nv_wr32(priv, 0x419bf8, 0x00000000);
nv_wr32(priv, 0x419bfc, 0x00000000); nv_wr32(priv, 0x419bfc, 0x00000000);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x419d2c, 0x00000000); nv_wr32(priv, 0x419d2c, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419d48, 0x00000000); nv_wr32(priv, 0x419d48, 0x00000000);
nv_wr32(priv, 0x419d4c, 0x00000000); nv_wr32(priv, 0x419d4c, 0x00000000);
break;
case 0xc0:
default:
break;
}
nv_wr32(priv, 0x419c0c, 0x00000000); nv_wr32(priv, 0x419c0c, 0x00000000);
nv_wr32(priv, 0x419e00, 0x00000000); nv_wr32(priv, 0x419e00, 0x00000000);
nv_wr32(priv, 0x419ea0, 0x00000000); nv_wr32(priv, 0x419ea0, 0x00000000);
nv_wr32(priv, 0x419ea4, 0x00000100); nv_wr32(priv, 0x419ea4, 0x00000100);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419ea8, 0x02001100); nv_wr32(priv, 0x419ea8, 0x02001100);
break;
case 0xc0:
default:
nv_wr32(priv, 0x419ea8, 0x00001100);
break;
}
nv_wr32(priv, 0x419eac, 0x11100702); nv_wr32(priv, 0x419eac, 0x11100702);
nv_wr32(priv, 0x419eb0, 0x00000003); nv_wr32(priv, 0x419eb0, 0x00000003);
nv_wr32(priv, 0x419eb4, 0x00000000); nv_wr32(priv, 0x419eb4, 0x00000000);
nv_wr32(priv, 0x419eb8, 0x00000000); nv_wr32(priv, 0x419eb8, 0x00000000);
nv_wr32(priv, 0x419ebc, 0x00000000); nv_wr32(priv, 0x419ebc, 0x00000000);
nv_wr32(priv, 0x419ec0, 0x00000000); nv_wr32(priv, 0x419ec0, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419ec8, 0x0e063818); nv_wr32(priv, 0x419ec8, 0x0e063818);
nv_wr32(priv, 0x419ecc, 0x0e060e06); nv_wr32(priv, 0x419ecc, 0x0e060e06);
nv_wr32(priv, 0x419ed0, 0x00003818); nv_wr32(priv, 0x419ed0, 0x00003818);
break;
case 0xc0:
default:
nv_wr32(priv, 0x419ec8, 0x06060618);
nv_wr32(priv, 0x419ed0, 0x0eff0e38);
break;
}
nv_wr32(priv, 0x419ed4, 0x011104f1); nv_wr32(priv, 0x419ed4, 0x011104f1);
nv_wr32(priv, 0x419edc, 0x00000000); nv_wr32(priv, 0x419edc, 0x00000000);
nv_wr32(priv, 0x419f00, 0x00000000); nv_wr32(priv, 0x419f00, 0x00000000);
...@@ -1133,6 +1310,7 @@ nvc0_graph_init(struct nouveau_object *object) ...@@ -1133,6 +1310,7 @@ nvc0_graph_init(struct nouveau_object *object)
nvc0_graph_init_regs(priv); nvc0_graph_init_regs(priv);
switch (nv_device(priv)->chipset) { switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xd9: case 0xd9:
case 0xd7: case 0xd7:
nvc0_graph_init_unk40xx(priv); nvc0_graph_init_unk40xx(priv);
......
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