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Commit d9750a2f authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
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Merge tag 'iio-for-4.6b' of... 

Merge tag 'iio-for-4.6b' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-next

Jonathan writes:

2nd round of new IIO device support, features and cleanups for the 4.6 cycle.

New Device Support
* Apex stx104 DAC
  - new driver for this PC104 board. Right now DAC support only.
* ADI ad5064
  - Add support for ad5625, ad5627, ad5645, ad5665, ad5667 DACs.
  - Add support for Linear Technology ltc2606, ltc2607, ltc2609, ltc2616,
    ltc2617, ltc2619, ltc2626, ltc2627 and ltc2629.
* ADI ad7192
  - add support for the ad7193
* Invensense mpu6050
  - substantial rework of driver to use regmap allowing SPI support extending
    the now split driver to cover the MPU6000.
* TI adc0832
  - new driver supporting ADC0831, ADC0832, ADC0834 and ADC0838 ADCs.
* TI ads1015
  - new driver, note that there is an existing hwmon driver. The long term
    intention is to probably remove the hwmon driver but for now we just have
    guards in place to ensure this driver is not built if that one is enabled.
* TI afe4403
  - new driver for this heart rate monitor / pulse oximeter front end chip.
* TI afe4404
  - new driver for this heart rate monitor / pulse oximeter front end chip.

Staging Graduations
* mxs-lradc
  - A combined general purpose and touch screen (input) device driver.
    Originally held in staging to allow reworking into and MFD but as
    that wasn't happening and isn't an absolute requirement we are moving
    it out of staging.

Driver new features
* ms5611
  - triggered buffer support
  - IIO_CHAN_INFO_SCALE to aid the triggered buffer support.

Driver cleanups / reworks / fixes
* ad5064
  - Use an enum for the register map layout to allow support of additional
    chips (precursor to the new support listed above).
  - Structural driver changes to allow support of the slightly different
    handling for the ltc parts above.
* ad5933
  - drop an exceptional & unnecessary for a function pointer.
* ad7606
  - Cleanup the repeated copies of pm ops.
  - consolidate the various channels specs via a sport of rearranging so only
    one version is needed.
* atlas ph sensor
  - add select IRQ_WORK
* hmc8543 (soon to move out of staging)
  - Comment style fixes
  - functionality of suspend and resume was swapped.
* spear-adc
  - use devm_clk_dev instead of managing the clk lifetime by hand.

Core
* Use new dmaengine_terminate_sync call to avoid a theoretical race.
* Fix docs for mlock in struct iio_dev as it is correctly taken in some
  drivers (docs used to say for core only).
* Add a helper function for calculating the scan index storage size within
  the core cutting out some cut and paste versions of the same code.
parents 2cdb82c7 ecc24e72
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Documentation/ABI/testing/sysfs-bus-iio
View file @ d9750a2f
......@@ -496,6 +496,7 @@ Description:
1kohm_to_gnd: connected to ground via an 1kOhm resistor,
6kohm_to_gnd: connected to ground via a 6kOhm resistor,
20kohm_to_gnd: connected to ground via a 20kOhm resistor,
90kohm_to_gnd: connected to ground via a 90kOhm resistor,
100kohm_to_gnd: connected to ground via an 100kOhm resistor,
125kohm_to_gnd: connected to ground via an 125kOhm resistor,
500kohm_to_gnd: connected to ground via a 500kOhm resistor,
......
Documentation/ABI/testing/sysfs-bus-iio-health-afe440x 0 → 100644
View file @ d9750a2f
What: /sys/bus/iio/devices/iio:deviceX/tia_resistanceY
/sys/bus/iio/devices/iio:deviceX/tia_capacitanceY
Date: December 2015
KernelVersion:
Contact: Andrew F. Davis <afd@ti.com>
Description:
Get and set the resistance and the capacitance settings for the
Transimpedance Amplifier. Y is 1 for Rf1 and Cf1, Y is 2 for
Rf2 and Cf2 values.
What: /sys/bus/iio/devices/iio:deviceX/tia_separate_en
Date: December 2015
KernelVersion:
Contact: Andrew F. Davis <afd@ti.com>
Description:
Enable or disable separate settings for the TransImpedance
Amplifier above, when disabled both values are set by the
first channel.
What: /sys/bus/iio/devices/iio:deviceX/in_intensity_ledY_raw
/sys/bus/iio/devices/iio:deviceX/in_intensity_ledY_ambient_raw
Date: December 2015
KernelVersion:
Contact: Andrew F. Davis <afd@ti.com>
Description:
Get measured values from the ADC for these stages. Y is the
specific LED number. The values are expressed in 24-bit twos
complement.
What: /sys/bus/iio/devices/iio:deviceX/in_intensity_ledY-ledY_ambient_raw
Date: December 2015
KernelVersion:
Contact: Andrew F. Davis <afd@ti.com>
Description:
Get differential values from the ADC for these stages. Y is the
specific LED number. The values are expressed in 24-bit twos
complement for the specified LEDs.
What: /sys/bus/iio/devices/iio:deviceX/out_current_ledY_offset
/sys/bus/iio/devices/iio:deviceX/out_current_ledY_ambient_offset
Date: December 2015
KernelVersion:
Contact: Andrew F. Davis <afd@ti.com>
Description:
Get and set the offset cancellation DAC setting for these
stages. The values are expressed in 5-bit sign-magnitude.
What: /sys/bus/iio/devices/iio:deviceX/out_current_ledY_raw
Date: December 2015
KernelVersion:
Contact: Andrew F. Davis <afd@ti.com>
Description:
Get and set the LED current for the specified LED. Y is the
specific LED number.
Documentation/devicetree/bindings/iio/adc/ti-adc0832.txt 0 → 100644
View file @ d9750a2f
* Texas Instruments' ADC0831/ADC0832/ADC0832/ADC0838
Required properties:
- compatible: Should be one of
* "ti,adc0831"
* "ti,adc0832"
* "ti,adc0834"
* "ti,adc0838"
- reg: spi chip select number for the device
- vref-supply: The regulator supply for ADC reference voltage
- spi-max-frequency: Max SPI frequency to use (< 400000)
Example:
adc@0 {
compatible = "ti,adc0832";
reg = <0>;
vref-supply = <&vdd_supply>;
spi-max-frequency = <200000>;
};
Documentation/devicetree/bindings/iio/health/afe4403.txt 0 → 100644
View file @ d9750a2f
Texas Instruments AFE4403 Heart rate and Pulse Oximeter
Required properties:
- compatible : Should be "ti,afe4403".
- reg : SPI chip select address of device.
- tx-supply : Regulator supply to transmitting LEDs.
- interrupt-parent : Phandle to he parent interrupt controller.
- interrupts : The interrupt line the device ADC_RDY pin is
connected to. For details refer to,
../../interrupt-controller/interrupts.txt.
Optional properties:
- reset-gpios : GPIO used to reset the device.
For details refer to, ../../gpio/gpio.txt.
For other required and optional properties of SPI slave nodes
please refer to ../../spi/spi-bus.txt.
Example:
&spi0 {
heart_mon@0 {
compatible = "ti,afe4403";
reg = <0>;
spi-max-frequency = <10000000>;
tx-supply = <&vbat>;
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
};
Documentation/devicetree/bindings/iio/health/afe4404.txt 0 → 100644
View file @ d9750a2f
Texas Instruments AFE4404 Heart rate and Pulse Oximeter
Required properties:
- compatible : Should be "ti,afe4404".
- reg : I2C address of the device.
- tx-supply : Regulator supply to transmitting LEDs.
- interrupt-parent : Phandle to he parent interrupt controller.
- interrupts : The interrupt line the device ADC_RDY pin is
connected to. For details refer to,
../interrupt-controller/interrupts.txt.
Optional properties:
- reset-gpios : GPIO used to reset the device.
For details refer to, ../gpio/gpio.txt.
Example:
&i2c2 {
heart_mon@58 {
compatible = "ti,afe4404";
reg = <0x58>;
tx-supply = <&vbat>;
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
};
MAINTAINERS
View file @ d9750a2f
......@@ -769,6 +769,12 @@ L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Maintained
F: sound/aoa/
APEX EMBEDDED SYSTEMS STX104 DAC DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
L: linux-iio@vger.kernel.org
S: Maintained
F: drivers/iio/dac/stx104.c
APM DRIVER
M: Jiri Kosina <jikos@kernel.org>
S: Odd fixes
......
drivers/iio/adc/Kconfig
View file @ d9750a2f
......@@ -297,6 +297,20 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
depends on INPUT
select STMP_DEVICE
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Say yes here to build support for i.MX23/i.MX28 LRADC convertor
built into these chips.
To compile this driver as a module, choose M here: the
module will be called mxs-lradc.
config NAU7802
tristate "Nuvoton NAU7802 ADC driver"
depends on I2C
......@@ -362,6 +376,16 @@ config TI_ADC081C
This driver can also be built as a module. If so, the module will be
called ti-adc081c.
config TI_ADC0832
tristate "Texas Instruments ADC0831/ADC0832/ADC0834/ADC0838"
depends on SPI
help
If you say yes here you get support for Texas Instruments ADC0831,
ADC0832, ADC0834, ADC0838 ADC chips.
This driver can also be built as a module. If so, the module will be
called ti-adc0832.
config TI_ADC128S052
tristate "Texas Instruments ADC128S052/ADC122S021/ADC124S021"
depends on SPI
......@@ -372,6 +396,19 @@ config TI_ADC128S052
This driver can also be built as a module. If so, the module will be
called ti-adc128s052.
config TI_ADS1015
tristate "Texas Instruments ADS1015 ADC"
depends on I2C && !SENSORS_ADS1015
select REGMAP_I2C
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
If you say yes here you get support for Texas Instruments ADS1015
ADC chip.
This driver can also be built as a module. If so, the module will be
called ti-ads1015.
config TI_ADS8688
tristate "Texas Instruments ADS8688"
depends on SPI && OF
......
drivers/iio/adc/Makefile
View file @ d9750a2f
......@@ -29,13 +29,16 @@ obj-$(CONFIG_MAX1363) += max1363.o
obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o
obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o
obj-$(CONFIG_TI_ADS1015) += ti-ads1015.o
obj-$(CONFIG_TI_ADS8688) += ti-ads8688.o
obj-$(CONFIG_TI_AM335X_ADC) += ti_am335x_adc.o
obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o
......
drivers/staging/iio/adc/mxs-lradc.c → drivers/iio/adc/mxs-lradc.c
View file @ d9750a2f
......@@ -443,7 +443,8 @@ static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
LRADC_CH(ch));
/* from the datasheet:
/*
* from the datasheet:
* "Software must clear this register in preparation for a
* multi-cycle accumulation.
*/
......@@ -504,7 +505,8 @@ static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
/* from the datasheet:
/*
* from the datasheet:
* "Software must clear this register in preparation for a
* multi-cycle accumulation.
*/
......@@ -914,7 +916,8 @@ static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
case IIO_CHAN_INFO_SCALE:
if (chan->type == IIO_TEMP) {
/* From the datasheet, we have to multiply by 1.012 and
/*
* From the datasheet, we have to multiply by 1.012 and
* divide by 4
*/
*val = 0;
......@@ -929,7 +932,8 @@ static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
case IIO_CHAN_INFO_OFFSET:
if (chan->type == IIO_TEMP) {
/* The calculated value from the ADC is in Kelvin, we
/*
* The calculated value from the ADC is in Kelvin, we
* want Celsius for hwmon so the offset is -273.15
* The offset is applied before scaling so it is
* actually -213.15 * 4 / 1.012 = -1079.644268
......@@ -1750,6 +1754,7 @@ static int mxs_lradc_remove(struct platform_device *pdev)
iio_triggered_buffer_cleanup(iio);
clk_disable_unprepare(lradc->clk);
return 0;
}
......
drivers/iio/adc/ti-adc0832.c 0 → 100644
View file @ d9750a2f
/*
* ADC0831/ADC0832/ADC0834/ADC0838 8-bit ADC driver
*
* Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
*
* This file is subject to the terms and conditions of version 2 of
* the GNU General Public License. See the file COPYING in the main
* directory of this archive for more details.
*
* Datasheet: http://www.ti.com/lit/ds/symlink/adc0832-n.pdf
*/
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#include <linux/regulator/consumer.h>
enum {
adc0831,
adc0832,
adc0834,
adc0838,
};
struct adc0832 {
struct spi_device *spi;
struct regulator *reg;
struct mutex lock;
u8 mux_bits;
u8 tx_buf[2] ____cacheline_aligned;
u8 rx_buf[2];
};
#define ADC0832_VOLTAGE_CHANNEL(chan) \
{ \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
}
#define ADC0832_VOLTAGE_CHANNEL_DIFF(chan1, chan2) \
{ \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (chan1), \
.channel2 = (chan2), \
.differential = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
}
static const struct iio_chan_spec adc0831_channels[] = {
ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1),
};
static const struct iio_chan_spec adc0832_channels[] = {
ADC0832_VOLTAGE_CHANNEL(0),
ADC0832_VOLTAGE_CHANNEL(1),
ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1),
ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0),
};
static const struct iio_chan_spec adc0834_channels[] = {
ADC0832_VOLTAGE_CHANNEL(0),
ADC0832_VOLTAGE_CHANNEL(1),
ADC0832_VOLTAGE_CHANNEL(2),
ADC0832_VOLTAGE_CHANNEL(3),
ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1),
ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0),
ADC0832_VOLTAGE_CHANNEL_DIFF(2, 3),
ADC0832_VOLTAGE_CHANNEL_DIFF(3, 2),
};
static const struct iio_chan_spec adc0838_channels[] = {
ADC0832_VOLTAGE_CHANNEL(0),
ADC0832_VOLTAGE_CHANNEL(1),
ADC0832_VOLTAGE_CHANNEL(2),
ADC0832_VOLTAGE_CHANNEL(3),
ADC0832_VOLTAGE_CHANNEL(4),
ADC0832_VOLTAGE_CHANNEL(5),
ADC0832_VOLTAGE_CHANNEL(6),
ADC0832_VOLTAGE_CHANNEL(7),
ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1),
ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0),
ADC0832_VOLTAGE_CHANNEL_DIFF(2, 3),
ADC0832_VOLTAGE_CHANNEL_DIFF(3, 2),
ADC0832_VOLTAGE_CHANNEL_DIFF(4, 5),
ADC0832_VOLTAGE_CHANNEL_DIFF(5, 4),
ADC0832_VOLTAGE_CHANNEL_DIFF(6, 7),
ADC0832_VOLTAGE_CHANNEL_DIFF(7, 6),
};
static int adc0831_adc_conversion(struct adc0832 *adc)
{
struct spi_device *spi = adc->spi;
int ret;
ret = spi_read(spi, &adc->rx_buf, 2);
if (ret)
return ret;
/*
* Skip TRI-STATE and a leading zero
*/
return (adc->rx_buf[0] << 2 & 0xff) | (adc->rx_buf[1] >> 6);
}
static int adc0832_adc_conversion(struct adc0832 *adc, int channel,
bool differential)
{
struct spi_device *spi = adc->spi;
struct spi_transfer xfer = {
.tx_buf = adc->tx_buf,
.rx_buf = adc->rx_buf,
.len = 2,
};
int ret;
if (!adc->mux_bits)
return adc0831_adc_conversion(adc);
/* start bit */
adc->tx_buf[0] = 1 << (adc->mux_bits + 1);
/* single-ended or differential */
adc->tx_buf[0] |= differential ? 0 : (1 << adc->mux_bits);
/* odd / sign */
adc->tx_buf[0] |= (channel % 2) << (adc->mux_bits - 1);
/* select */
if (adc->mux_bits > 1)
adc->tx_buf[0] |= channel / 2;
/* align Data output BIT7 (MSB) to 8-bit boundary */
adc->tx_buf[0] <<= 1;
ret = spi_sync_transfer(spi, &xfer, 1);
if (ret)
return ret;
return adc->rx_buf[1];
}
static int adc0832_read_raw(struct iio_dev *iio,
struct iio_chan_spec const *channel, int *value,
int *shift, long mask)
{
struct adc0832 *adc = iio_priv(iio);
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&adc->lock);
*value = adc0832_adc_conversion(adc, channel->channel,
channel->differential);
mutex_unlock(&adc->lock);
if (*value < 0)
return *value;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*value = regulator_get_voltage(adc->reg);
if (*value < 0)
return *value;
/* convert regulator output voltage to mV */
*value /= 1000;
*shift = 8;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
static const struct iio_info adc0832_info = {
.read_raw = adc0832_read_raw,
.driver_module = THIS_MODULE,
};
static int adc0832_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct adc0832 *adc;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
if (!indio_dev)
return -ENOMEM;
adc = iio_priv(indio_dev);
adc->spi = spi;
mutex_init(&adc->lock);
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->dev.parent = &spi->dev;
indio_dev->info = &adc0832_info;
indio_dev->modes = INDIO_DIRECT_MODE;
switch (spi_get_device_id(spi)->driver_data) {
case adc0831:
adc->mux_bits = 0;
indio_dev->channels = adc0831_channels;
indio_dev->num_channels = ARRAY_SIZE(adc0831_channels);
break;
case adc0832:
adc->mux_bits = 1;
indio_dev->channels = adc0832_channels;
indio_dev->num_channels = ARRAY_SIZE(adc0832_channels);
break;
case adc0834:
adc->mux_bits = 2;
indio_dev->channels = adc0834_channels;
indio_dev->num_channels = ARRAY_SIZE(adc0834_channels);
break;
case adc0838:
adc->mux_bits = 3;
indio_dev->channels = adc0838_channels;
indio_dev->num_channels = ARRAY_SIZE(adc0838_channels);
break;
default:
return -EINVAL;
}
adc->reg = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(adc->reg))
return PTR_ERR(adc->reg);
ret = regulator_enable(adc->reg);
if (ret)
return ret;
spi_set_drvdata(spi, indio_dev);
ret = iio_device_register(indio_dev);
if (ret)
regulator_disable(adc->reg);
return ret;
}
static int adc0832_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct adc0832 *adc = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
regulator_disable(adc->reg);
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id adc0832_dt_ids[] = {
{ .compatible = "ti,adc0831", },
{ .compatible = "ti,adc0832", },
{ .compatible = "ti,adc0834", },
{ .compatible = "ti,adc0838", },
{}
};
MODULE_DEVICE_TABLE(of, adc0832_dt_ids);
#endif
static const struct spi_device_id adc0832_id[] = {
{ "adc0831", adc0831 },
{ "adc0832", adc0832 },
{ "adc0834", adc0834 },
{ "adc0838", adc0838 },
{}
};
MODULE_DEVICE_TABLE(spi, adc0832_id);
static struct spi_driver adc0832_driver = {
.driver = {
.name = "adc0832",
.of_match_table = of_match_ptr(adc0832_dt_ids),
},
.probe = adc0832_probe,
.remove = adc0832_remove,
.id_table = adc0832_id,
};
module_spi_driver(adc0832_driver);
MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
MODULE_DESCRIPTION("ADC0831/ADC0832/ADC0834/ADC0838 driver");
MODULE_LICENSE("GPL v2");
drivers/iio/adc/ti-ads1015.c 0 → 100644
View file @ d9750a2f
/*
* ADS1015 - Texas Instruments Analog-to-Digital Converter
*
* Copyright (c) 2016, Intel Corporation.
*
* This file is subject to the terms and conditions of version 2 of
* the GNU General Public License. See the file COPYING in the main
* directory of this archive for more details.
*
* IIO driver for ADS1015 ADC 7-bit I2C slave address:
* * 0x48 - ADDR connected to Ground
* * 0x49 - ADDR connected to Vdd
* * 0x4A - ADDR connected to SDA
* * 0x4B - ADDR connected to SCL
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/pm_runtime.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/i2c/ads1015.h>
#include <linux/iio/iio.h>
#include <linux/iio/types.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#define ADS1015_DRV_NAME "ads1015"
#define ADS1015_CONV_REG 0x00
#define ADS1015_CFG_REG 0x01
#define ADS1015_CFG_DR_SHIFT 5
#define ADS1015_CFG_MOD_SHIFT 8
#define ADS1015_CFG_PGA_SHIFT 9
#define ADS1015_CFG_MUX_SHIFT 12
#define ADS1015_CFG_DR_MASK GENMASK(7, 5)
#define ADS1015_CFG_MOD_MASK BIT(8)
#define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
#define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
/* device operating modes */
#define ADS1015_CONTINUOUS 0
#define ADS1015_SINGLESHOT 1
#define ADS1015_SLEEP_DELAY_MS 2000
#define ADS1015_DEFAULT_PGA 2
#define ADS1015_DEFAULT_DATA_RATE 4
#define ADS1015_DEFAULT_CHAN 0
enum ads1015_channels {
ADS1015_AIN0_AIN1 = 0,
ADS1015_AIN0_AIN3,
ADS1015_AIN1_AIN3,
ADS1015_AIN2_AIN3,
ADS1015_AIN0,
ADS1015_AIN1,
ADS1015_AIN2,
ADS1015_AIN3,
ADS1015_TIMESTAMP,
};
static const unsigned int ads1015_data_rate[] = {
128, 250, 490, 920, 1600, 2400, 3300, 3300
};
static const struct {
int scale;
int uscale;
} ads1015_scale[] = {
{3, 0},
{2, 0},
{1, 0},
{0, 500000},
{0, 250000},
{0, 125000},
{0, 125000},
{0, 125000},
};
#define ADS1015_V_CHAN(_chan, _addr) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.address = _addr, \
.channel = _chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.scan_index = _addr, \
.scan_type = { \
.sign = 's', \
.realbits = 12, \
.storagebits = 16, \
.shift = 4, \
.endianness = IIO_CPU, \
}, \
}
#define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
.type = IIO_VOLTAGE, \
.differential = 1, \
.indexed = 1, \
.address = _addr, \
.channel = _chan, \
.channel2 = _chan2, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.scan_index = _addr, \
.scan_type = { \
.sign = 's', \
.realbits = 12, \
.storagebits = 16, \
.shift = 4, \
.endianness = IIO_CPU, \
}, \
}
struct ads1015_data {
struct regmap *regmap;
/*
* Protects ADC ops, e.g: concurrent sysfs/buffered
* data reads, configuration updates
*/
struct mutex lock;
struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
};
static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
{
return (reg == ADS1015_CFG_REG);
}
static const struct regmap_config ads1015_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.max_register = ADS1015_CFG_REG,
.writeable_reg = ads1015_is_writeable_reg,
};
static const struct iio_chan_spec ads1015_channels[] = {
ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
ADS1015_V_CHAN(0, ADS1015_AIN0),
ADS1015_V_CHAN(1, ADS1015_AIN1),
ADS1015_V_CHAN(2, ADS1015_AIN2),
ADS1015_V_CHAN(3, ADS1015_AIN3),
IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
};
static int ads1015_set_power_state(struct ads1015_data *data, bool on)
{
int ret;
struct device *dev = regmap_get_device(data->regmap);
if (on) {
ret = pm_runtime_get_sync(dev);
if (ret < 0)
pm_runtime_put_noidle(dev);
} else {
pm_runtime_mark_last_busy(dev);
ret = pm_runtime_put_autosuspend(dev);
}
return ret;
}
static
int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
{
int ret, pga, dr, conv_time;
bool change;
if (chan < 0 || chan >= ADS1015_CHANNELS)
return -EINVAL;
pga = data->channel_data[chan].pga;
dr = data->channel_data[chan].data_rate;
ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG,
ADS1015_CFG_MUX_MASK |
ADS1015_CFG_PGA_MASK,
chan << ADS1015_CFG_MUX_SHIFT |
pga << ADS1015_CFG_PGA_SHIFT,
&change);
if (ret < 0)
return ret;
if (change) {
conv_time = DIV_ROUND_UP(USEC_PER_SEC, ads1015_data_rate[dr]);
usleep_range(conv_time, conv_time + 1);
}
return regmap_read(data->regmap, ADS1015_CONV_REG, val);
}
static irqreturn_t ads1015_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct ads1015_data *data = iio_priv(indio_dev);
s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */
int chan, ret, res;
memset(buf, 0, sizeof(buf));
mutex_lock(&data->lock);
chan = find_first_bit(indio_dev->active_scan_mask,
indio_dev->masklength);
ret = ads1015_get_adc_result(data, chan, &res);
if (ret < 0) {
mutex_unlock(&data->lock);
goto err;
}
buf[0] = res;
mutex_unlock(&data->lock);
iio_push_to_buffers_with_timestamp(indio_dev, buf, iio_get_time_ns());
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int ads1015_set_scale(struct ads1015_data *data, int chan,
int scale, int uscale)
{
int i, ret, rindex = -1;
for (i = 0; i < ARRAY_SIZE(ads1015_scale); i++)
if (ads1015_scale[i].scale == scale &&
ads1015_scale[i].uscale == uscale) {
rindex = i;
break;
}
if (rindex < 0)
return -EINVAL;
ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
ADS1015_CFG_PGA_MASK,
rindex << ADS1015_CFG_PGA_SHIFT);
if (ret < 0)
return ret;
data->channel_data[chan].pga = rindex;
return 0;
}
static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
{
int i, ret, rindex = -1;
for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++)
if (ads1015_data_rate[i] == rate) {
rindex = i;
break;
}
if (rindex < 0)
return -EINVAL;
ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
ADS1015_CFG_DR_MASK,
rindex << ADS1015_CFG_DR_SHIFT);
if (ret < 0)
return ret;
data->channel_data[chan].data_rate = rindex;
return 0;
}
static int ads1015_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
int ret, idx;
struct ads1015_data *data = iio_priv(indio_dev);
mutex_lock(&indio_dev->mlock);
mutex_lock(&data->lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (iio_buffer_enabled(indio_dev)) {
ret = -EBUSY;
break;
}
ret = ads1015_set_power_state(data, true);
if (ret < 0)
break;
ret = ads1015_get_adc_result(data, chan->address, val);
if (ret < 0) {
ads1015_set_power_state(data, false);
break;
}
/* 12 bit res, D0 is bit 4 in conversion register */
*val = sign_extend32(*val >> 4, 11);
ret = ads1015_set_power_state(data, false);
if (ret < 0)
break;
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SCALE:
idx = data->channel_data[chan->address].pga;
*val = ads1015_scale[idx].scale;
*val2 = ads1015_scale[idx].uscale;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
case IIO_CHAN_INFO_SAMP_FREQ:
idx = data->channel_data[chan->address].data_rate;
*val = ads1015_data_rate[idx];
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&data->lock);
mutex_unlock(&indio_dev->mlock);
return ret;
}
static int ads1015_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct ads1015_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->lock);
switch (mask) {
case IIO_CHAN_INFO_SCALE:
ret = ads1015_set_scale(data, chan->address, val, val2);
break;
case IIO_CHAN_INFO_SAMP_FREQ:
ret = ads1015_set_data_rate(data, chan->address, val);
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&data->lock);
return ret;
}
static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
{
return ads1015_set_power_state(iio_priv(indio_dev), true);
}
static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
{
return ads1015_set_power_state(iio_priv(indio_dev), false);
}
static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
.preenable = ads1015_buffer_preenable,
.postenable = iio_triggered_buffer_postenable,
.predisable = iio_triggered_buffer_predisable,
.postdisable = ads1015_buffer_postdisable,
.validate_scan_mask = &iio_validate_scan_mask_onehot,
};
static IIO_CONST_ATTR(scale_available, "3 2 1 0.5 0.25 0.125");
static IIO_CONST_ATTR(sampling_frequency_available,
"128 250 490 920 1600 2400 3300");
static struct attribute *ads1015_attributes[] = {
&iio_const_attr_scale_available.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL,
};
static const struct attribute_group ads1015_attribute_group = {
.attrs = ads1015_attributes,
};
static const struct iio_info ads1015_info = {
.driver_module = THIS_MODULE,
.read_raw = ads1015_read_raw,
.write_raw = ads1015_write_raw,
.attrs = &ads1015_attribute_group,
};
#ifdef CONFIG_OF
static int ads1015_get_channels_config_of(struct i2c_client *client)
{
struct ads1015_data *data = i2c_get_clientdata(client);
struct device_node *node;
if (!client->dev.of_node ||
!of_get_next_child(client->dev.of_node, NULL))
return -EINVAL;
for_each_child_of_node(client->dev.of_node, node) {
u32 pval;
unsigned int channel;
unsigned int pga = ADS1015_DEFAULT_PGA;
unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
if (of_property_read_u32(node, "reg", &pval)) {
dev_err(&client->dev, "invalid reg on %s\n",
node->full_name);
continue;
}
channel = pval;
if (channel >= ADS1015_CHANNELS) {
dev_err(&client->dev,
"invalid channel index %d on %s\n",
channel, node->full_name);
continue;
}
if (!of_property_read_u32(node, "ti,gain", &pval)) {
pga = pval;
if (pga > 6) {
dev_err(&client->dev, "invalid gain on %s\n",
node->full_name);
return -EINVAL;
}
}
if (!of_property_read_u32(node, "ti,datarate", &pval)) {
data_rate = pval;
if (data_rate > 7) {
dev_err(&client->dev,
"invalid data_rate on %s\n",
node->full_name);
return -EINVAL;
}
}
data->channel_data[channel].pga = pga;
data->channel_data[channel].data_rate = data_rate;
}
return 0;
}
#endif
static void ads1015_get_channels_config(struct i2c_client *client)
{
unsigned int k;
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct ads1015_data *data = iio_priv(indio_dev);
struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
/* prefer platform data */
if (pdata) {
memcpy(data->channel_data, pdata->channel_data,
sizeof(data->channel_data));
return;
}
#ifdef CONFIG_OF
if (!ads1015_get_channels_config_of(client))
return;
#endif
/* fallback on default configuration */
for (k = 0; k < ADS1015_CHANNELS; ++k) {
data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
}
}
static int ads1015_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct iio_dev *indio_dev;
struct ads1015_data *data;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
mutex_init(&data->lock);
indio_dev->dev.parent = &client->dev;
indio_dev->info = &ads1015_info;
indio_dev->name = ADS1015_DRV_NAME;
indio_dev->channels = ads1015_channels;
indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
/* we need to keep this ABI the same as used by hwmon ADS1015 driver */
ads1015_get_channels_config(client);
data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(&client->dev, "Failed to allocate register map\n");
return PTR_ERR(data->regmap);
}
ret = iio_triggered_buffer_setup(indio_dev, NULL,
ads1015_trigger_handler,
&ads1015_buffer_setup_ops);
if (ret < 0) {
dev_err(&client->dev, "iio triggered buffer setup failed\n");
return ret;
}
ret = pm_runtime_set_active(&client->dev);
if (ret)
goto err_buffer_cleanup;
pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
pm_runtime_use_autosuspend(&client->dev);
pm_runtime_enable(&client->dev);
ret = iio_device_register(indio_dev);
if (ret < 0) {
dev_err(&client->dev, "Failed to register IIO device\n");
goto err_buffer_cleanup;
}
return 0;
err_buffer_cleanup:
iio_triggered_buffer_cleanup(indio_dev);
return ret;
}
static int ads1015_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct ads1015_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
pm_runtime_put_noidle(&client->dev);
iio_triggered_buffer_cleanup(indio_dev);
/* power down single shot mode */
return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
ADS1015_CFG_MOD_MASK,
ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
}
#ifdef CONFIG_PM
static int ads1015_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct ads1015_data *data = iio_priv(indio_dev);
return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
ADS1015_CFG_MOD_MASK,
ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
}
static int ads1015_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct ads1015_data *data = iio_priv(indio_dev);
return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
ADS1015_CFG_MOD_MASK,
ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
}
#endif
static const struct dev_pm_ops ads1015_pm_ops = {
SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
ads1015_runtime_resume, NULL)
};
static const struct i2c_device_id ads1015_id[] = {
{"ads1015", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, ads1015_id);
static struct i2c_driver ads1015_driver = {
.driver = {
.name = ADS1015_DRV_NAME,
.pm = &ads1015_pm_ops,
},
.probe = ads1015_probe,
.remove = ads1015_remove,
.id_table = ads1015_id,
};
module_i2c_driver(ads1015_driver);
MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
MODULE_LICENSE("GPL v2");
drivers/iio/buffer/industrialio-buffer-dmaengine.c
View file @ d9750a2f
......@@ -93,12 +93,7 @@ static void iio_dmaengine_buffer_abort(struct iio_dma_buffer_queue *queue)
struct dmaengine_buffer *dmaengine_buffer =
iio_buffer_to_dmaengine_buffer(&queue->buffer);
dmaengine_terminate_all(dmaengine_buffer->chan);
/* FIXME: There is a slight chance of a race condition here.
* dmaengine_terminate_all() does not guarantee that all transfer
* callbacks have finished running. Need to introduce a
* dmaengine_terminate_all_sync().
*/
dmaengine_terminate_sync(dmaengine_buffer->chan);
iio_dma_buffer_block_list_abort(queue, &dmaengine_buffer->active);
}
......
drivers/iio/chemical/Kconfig
View file @ d9750a2f
......@@ -10,6 +10,7 @@ config ATLAS_PH_SENSOR
select REGMAP_I2C
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
select IRQ_WORK
help
Say Y here to build I2C interface support for the Atlas
Scientific OEM pH-SM sensor.
......
drivers/iio/dac/Kconfig
View file @ d9750a2f
......@@ -10,8 +10,10 @@ config AD5064
depends on (SPI_MASTER && I2C!=m) || I2C
help
Say yes here to build support for Analog Devices AD5024, AD5025, AD5044,
AD5045, AD5064, AD5064-1, AD5065, AD5628, AD5629R, AD5648, AD5666, AD5668,
AD5669R Digital to Analog Converter.
AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R, AD5627, AD5627R,
AD5628, AD5629R, AD5645R, AD5647R, AD5648, AD5665, AD5665R, AD5666,
AD5667, AD5667R, AD5668, AD5669R, LTC2606, LTC2607, LTC2609, LTC2616,
LTC2617, LTC2619, LTC2626, LTC2627, LTC2629 Digital to Analog Converter.
To compile this driver as a module, choose M here: the
module will be called ad5064.
......@@ -206,4 +208,13 @@ config MCP4922
To compile this driver as a module, choose M here: the module
will be called mcp4922.
config STX104
tristate "Apex Embedded Systems STX104 DAC driver"
depends on ISA
help
Say yes here to build support for the 2-channel DAC on the Apex
Embedded Systems STX104 integrated analog PC/104 card. The base port
addresses for the devices may be configured via the "base" module
parameter array.
endmenu
drivers/iio/dac/Makefile
View file @ d9750a2f
......@@ -22,3 +22,4 @@ obj-$(CONFIG_MAX517) += max517.o
obj-$(CONFIG_MAX5821) += max5821.o
obj-$(CONFIG_MCP4725) += mcp4725.o
obj-$(CONFIG_MCP4922) += mcp4922.o
obj-$(CONFIG_STX104) += stx104.o
drivers/iio/dac/ad5064.c
View file @ d9750a2f
/*
* AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5628, AD5629R,
* AD5648, AD5666, AD5668, AD5669R Digital to analog converters driver
* AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R,
* AD5627, AD5627R, AD5628, AD5629R, AD5645R, AD5647R, AD5648, AD5665, AD5665R,
* AD5666, AD5667, AD5667R, AD5668, AD5669R, LTC2606, LTC2607, LTC2609, LTC2616,
* LTC2617, LTC2619, LTC2626, LTC2627, LTC2629 Digital to analog converters
* driver
*
* Copyright 2011 Analog Devices Inc.
*
......@@ -39,6 +42,9 @@
#define AD5064_CMD_RESET 0x7
#define AD5064_CMD_CONFIG 0x8
#define AD5064_CMD_RESET_V2 0x5
#define AD5064_CMD_CONFIG_V2 0x7
#define AD5064_CONFIG_DAISY_CHAIN_ENABLE BIT(1)
#define AD5064_CONFIG_INT_VREF_ENABLE BIT(0)
......@@ -47,13 +53,26 @@
#define AD5064_LDAC_PWRDN_100K 0x2
#define AD5064_LDAC_PWRDN_3STATE 0x3
/**
* enum ad5064_regmap_type - Register layout variant
* @AD5064_REGMAP_ADI: Old Analog Devices register map layout
* @AD5064_REGMAP_ADI2: New Analog Devices register map layout
* @AD5064_REGMAP_LTC: LTC register map layout
*/
enum ad5064_regmap_type {
AD5064_REGMAP_ADI,
AD5064_REGMAP_ADI2,
AD5064_REGMAP_LTC,
};
/**
* struct ad5064_chip_info - chip specific information
* @shared_vref: whether the vref supply is shared between channels
* @internal_vref: internal reference voltage. 0 if the chip has no internal
* vref.
* @internal_vref: internal reference voltage. 0 if the chip has no
internal vref.
* @channel: channel specification
* @num_channels: number of channels
* @regmap_type: register map layout variant
*/
struct ad5064_chip_info {
......@@ -61,6 +80,7 @@ struct ad5064_chip_info {
unsigned long internal_vref;
const struct iio_chan_spec *channels;
unsigned int num_channels;
enum ad5064_regmap_type regmap_type;
};
struct ad5064_state;
......@@ -111,18 +131,43 @@ enum ad5064_type {
ID_AD5064,
ID_AD5064_1,
ID_AD5065,
ID_AD5625,
ID_AD5625R_1V25,
ID_AD5625R_2V5,
ID_AD5627,
ID_AD5627R_1V25,
ID_AD5627R_2V5,
ID_AD5628_1,
ID_AD5628_2,
ID_AD5629_1,
ID_AD5629_2,
ID_AD5645R_1V25,
ID_AD5645R_2V5,
ID_AD5647R_1V25,
ID_AD5647R_2V5,
ID_AD5648_1,
ID_AD5648_2,
ID_AD5665,
ID_AD5665R_1V25,
ID_AD5665R_2V5,
ID_AD5666_1,
ID_AD5666_2,
ID_AD5667,
ID_AD5667R_1V25,
ID_AD5667R_2V5,
ID_AD5668_1,
ID_AD5668_2,
ID_AD5669_1,
ID_AD5669_2,
ID_LTC2606,
ID_LTC2607,
ID_LTC2609,
ID_LTC2616,
ID_LTC2617,
ID_LTC2619,
ID_LTC2626,
ID_LTC2627,
ID_LTC2629,
};
static int ad5064_write(struct ad5064_state *st, unsigned int cmd,
......@@ -136,15 +181,27 @@ static int ad5064_write(struct ad5064_state *st, unsigned int cmd,
static int ad5064_sync_powerdown_mode(struct ad5064_state *st,
const struct iio_chan_spec *chan)
{
unsigned int val;
unsigned int val, address;
unsigned int shift;
int ret;
if (st->chip_info->regmap_type == AD5064_REGMAP_LTC) {
val = 0;
address = chan->address;
} else {
if (st->chip_info->regmap_type == AD5064_REGMAP_ADI2)
shift = 4;
else
shift = 8;
val = (0x1 << chan->address);
address = 0;
if (st->pwr_down[chan->channel])
val |= st->pwr_down_mode[chan->channel] << 8;
val |= st->pwr_down_mode[chan->channel] << shift;
}
ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, 0, val, 0);
ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, address, val, 0);
return ret;
}
......@@ -155,6 +212,10 @@ static const char * const ad5064_powerdown_modes[] = {
"three_state",
};
static const char * const ltc2617_powerdown_modes[] = {
"90kohm_to_gnd",
};
static int ad5064_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
......@@ -185,6 +246,13 @@ static const struct iio_enum ad5064_powerdown_mode_enum = {
.set = ad5064_set_powerdown_mode,
};
static const struct iio_enum ltc2617_powerdown_mode_enum = {
.items = ltc2617_powerdown_modes,
.num_items = ARRAY_SIZE(ltc2617_powerdown_modes),
.get = ad5064_get_powerdown_mode,
.set = ad5064_set_powerdown_mode,
};
static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
......@@ -295,7 +363,19 @@ static const struct iio_chan_spec_ext_info ad5064_ext_info[] = {
{ },
};
#define AD5064_CHANNEL(chan, addr, bits, _shift) { \
static const struct iio_chan_spec_ext_info ltc2617_ext_info[] = {
{
.name = "powerdown",
.read = ad5064_read_dac_powerdown,
.write = ad5064_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ltc2617_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", &ltc2617_powerdown_mode_enum),
{ },
};
#define AD5064_CHANNEL(chan, addr, bits, _shift, _ext_info) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
......@@ -309,145 +389,340 @@ static const struct iio_chan_spec_ext_info ad5064_ext_info[] = {
.storagebits = 16, \
.shift = (_shift), \
}, \
.ext_info = ad5064_ext_info, \
.ext_info = (_ext_info), \
}
#define DECLARE_AD5064_CHANNELS(name, bits, shift) \
#define DECLARE_AD5064_CHANNELS(name, bits, shift, ext_info) \
const struct iio_chan_spec name[] = { \
AD5064_CHANNEL(0, 0, bits, shift), \
AD5064_CHANNEL(1, 1, bits, shift), \
AD5064_CHANNEL(2, 2, bits, shift), \
AD5064_CHANNEL(3, 3, bits, shift), \
AD5064_CHANNEL(4, 4, bits, shift), \
AD5064_CHANNEL(5, 5, bits, shift), \
AD5064_CHANNEL(6, 6, bits, shift), \
AD5064_CHANNEL(7, 7, bits, shift), \
AD5064_CHANNEL(0, 0, bits, shift, ext_info), \
AD5064_CHANNEL(1, 1, bits, shift, ext_info), \
AD5064_CHANNEL(2, 2, bits, shift, ext_info), \
AD5064_CHANNEL(3, 3, bits, shift, ext_info), \
AD5064_CHANNEL(4, 4, bits, shift, ext_info), \
AD5064_CHANNEL(5, 5, bits, shift, ext_info), \
AD5064_CHANNEL(6, 6, bits, shift, ext_info), \
AD5064_CHANNEL(7, 7, bits, shift, ext_info), \
}
#define DECLARE_AD5065_CHANNELS(name, bits, shift) \
#define DECLARE_AD5065_CHANNELS(name, bits, shift, ext_info) \
const struct iio_chan_spec name[] = { \
AD5064_CHANNEL(0, 0, bits, shift), \
AD5064_CHANNEL(1, 3, bits, shift), \
AD5064_CHANNEL(0, 0, bits, shift, ext_info), \
AD5064_CHANNEL(1, 3, bits, shift, ext_info), \
}
static DECLARE_AD5064_CHANNELS(ad5024_channels, 12, 8);
static DECLARE_AD5064_CHANNELS(ad5044_channels, 14, 6);
static DECLARE_AD5064_CHANNELS(ad5064_channels, 16, 4);
static DECLARE_AD5064_CHANNELS(ad5024_channels, 12, 8, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ad5044_channels, 14, 6, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ad5064_channels, 16, 4, ad5064_ext_info);
static DECLARE_AD5065_CHANNELS(ad5025_channels, 12, 8, ad5064_ext_info);
static DECLARE_AD5065_CHANNELS(ad5045_channels, 14, 6, ad5064_ext_info);
static DECLARE_AD5065_CHANNELS(ad5065_channels, 16, 4, ad5064_ext_info);
static DECLARE_AD5065_CHANNELS(ad5025_channels, 12, 8);
static DECLARE_AD5065_CHANNELS(ad5045_channels, 14, 6);
static DECLARE_AD5065_CHANNELS(ad5065_channels, 16, 4);
static DECLARE_AD5064_CHANNELS(ad5629_channels, 12, 4, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ad5645_channels, 14, 2, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ad5669_channels, 16, 0, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ad5629_channels, 12, 4);
static DECLARE_AD5064_CHANNELS(ad5669_channels, 16, 0);
static DECLARE_AD5064_CHANNELS(ltc2607_channels, 16, 0, ltc2617_ext_info);
static DECLARE_AD5064_CHANNELS(ltc2617_channels, 14, 2, ltc2617_ext_info);
static DECLARE_AD5064_CHANNELS(ltc2627_channels, 12, 4, ltc2617_ext_info);
static const struct ad5064_chip_info ad5064_chip_info_tbl[] = {
[ID_AD5024] = {
.shared_vref = false,
.channels = ad5024_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5025] = {
.shared_vref = false,
.channels = ad5025_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5044] = {
.shared_vref = false,
.channels = ad5044_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5045] = {
.shared_vref = false,
.channels = ad5045_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5064] = {
.shared_vref = false,
.channels = ad5064_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5064_1] = {
.shared_vref = true,
.channels = ad5064_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5065] = {
.shared_vref = false,
.channels = ad5065_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5625] = {
.shared_vref = true,
.channels = ad5629_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5625R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5629_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5625R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5629_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5627] = {
.shared_vref = true,
.channels = ad5629_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5627R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5629_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5627R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5629_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5628_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5024_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5628_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5024_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5629_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5629_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5629_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5629_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5645R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5645_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5645R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5645_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5647R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5645_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5647R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5645_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5648_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5044_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5648_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5044_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5665] = {
.shared_vref = true,
.channels = ad5669_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5665R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5669_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5665R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5669_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5666_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5064_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5666_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5064_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5667] = {
.shared_vref = true,
.channels = ad5669_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5667R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5669_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5667R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5669_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5668_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5064_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5668_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5064_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5669_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5669_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5669_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5669_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_LTC2606] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2607_channels,
.num_channels = 1,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2607] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2607_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2609] = {
.shared_vref = false,
.internal_vref = 0,
.channels = ltc2607_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2616] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2617_channels,
.num_channels = 1,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2617] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2617_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2619] = {
.shared_vref = false,
.internal_vref = 0,
.channels = ltc2617_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2626] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2627_channels,
.num_channels = 1,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2627] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2627_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2629] = {
.shared_vref = false,
.internal_vref = 0,
.channels = ltc2627_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_LTC,
},
};
......@@ -469,6 +744,22 @@ static const char * const ad5064_vref_name(struct ad5064_state *st,
return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref];
}
static int ad5064_set_config(struct ad5064_state *st, unsigned int val)
{
unsigned int cmd;
switch (st->chip_info->regmap_type) {
case AD5064_REGMAP_ADI2:
cmd = AD5064_CMD_CONFIG_V2;
break;
default:
cmd = AD5064_CMD_CONFIG;
break;
}
return ad5064_write(st, cmd, 0, val, 0);
}
static int ad5064_probe(struct device *dev, enum ad5064_type type,
const char *name, ad5064_write_func write)
{
......@@ -498,8 +789,7 @@ static int ad5064_probe(struct device *dev, enum ad5064_type type,
if (!st->chip_info->internal_vref)
return ret;
st->use_internal_vref = true;
ret = ad5064_write(st, AD5064_CMD_CONFIG, 0,
AD5064_CONFIG_INT_VREF_ENABLE, 0);
ret = ad5064_set_config(st, AD5064_CONFIG_INT_VREF_ENABLE);
if (ret) {
dev_err(dev, "Failed to enable internal vref: %d\n",
ret);
......@@ -628,9 +918,19 @@ static int ad5064_i2c_write(struct ad5064_state *st, unsigned int cmd,
unsigned int addr, unsigned int val)
{
struct i2c_client *i2c = to_i2c_client(st->dev);
unsigned int cmd_shift;
int ret;
st->data.i2c[0] = (cmd << 4) | addr;
switch (st->chip_info->regmap_type) {
case AD5064_REGMAP_ADI2:
cmd_shift = 3;
break;
default:
cmd_shift = 4;
break;
}
st->data.i2c[0] = (cmd << cmd_shift) | addr;
put_unaligned_be16(val, &st->data.i2c[1]);
ret = i2c_master_send(i2c, st->data.i2c, 3);
......@@ -653,12 +953,35 @@ static int ad5064_i2c_remove(struct i2c_client *i2c)
}
static const struct i2c_device_id ad5064_i2c_ids[] = {
{"ad5625", ID_AD5625 },
{"ad5625r-1v25", ID_AD5625R_1V25 },
{"ad5625r-2v5", ID_AD5625R_2V5 },
{"ad5627", ID_AD5627 },
{"ad5627r-1v25", ID_AD5627R_1V25 },
{"ad5627r-2v5", ID_AD5627R_2V5 },
{"ad5629-1", ID_AD5629_1},
{"ad5629-2", ID_AD5629_2},
{"ad5629-3", ID_AD5629_2}, /* similar enough to ad5629-2 */
{"ad5645r-1v25", ID_AD5645R_1V25 },
{"ad5645r-2v5", ID_AD5645R_2V5 },
{"ad5665", ID_AD5665 },
{"ad5665r-1v25", ID_AD5665R_1V25 },
{"ad5665r-2v5", ID_AD5665R_2V5 },
{"ad5667", ID_AD5667 },
{"ad5667r-1v25", ID_AD5667R_1V25 },
{"ad5667r-2v5", ID_AD5667R_2V5 },
{"ad5669-1", ID_AD5669_1},
{"ad5669-2", ID_AD5669_2},
{"ad5669-3", ID_AD5669_2}, /* similar enough to ad5669-2 */
{"ltc2606", ID_LTC2606},
{"ltc2607", ID_LTC2607},
{"ltc2609", ID_LTC2609},
{"ltc2616", ID_LTC2616},
{"ltc2617", ID_LTC2617},
{"ltc2619", ID_LTC2619},
{"ltc2626", ID_LTC2626},
{"ltc2627", ID_LTC2627},
{"ltc2629", ID_LTC2629},
{}
};
MODULE_DEVICE_TABLE(i2c, ad5064_i2c_ids);
......
drivers/iio/dac/stx104.c 0 → 100644
View file @ d9750a2f
/*
* DAC driver for the Apex Embedded Systems STX104
* Copyright (C) 2016 William Breathitt Gray
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, version 2, as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/iio/iio.h>
#include <linux/iio/types.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/isa.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#define STX104_NUM_CHAN 2
#define STX104_CHAN(chan) { \
.type = IIO_VOLTAGE, \
.channel = chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.indexed = 1, \
.output = 1 \
}
#define STX104_EXTENT 16
/**
* The highest base address possible for an ISA device is 0x3FF; this results in
* 1024 possible base addresses. Dividing the number of possible base addresses
* by the address extent taken by each device results in the maximum number of
* devices on a system.
*/
#define MAX_NUM_STX104 (1024 / STX104_EXTENT)
static unsigned base[MAX_NUM_STX104];
static unsigned num_stx104;
module_param_array(base, uint, &num_stx104, 0);
MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
/**
* struct stx104_iio - IIO device private data structure
* @chan_out_states: channels' output states
* @base: base port address of the IIO device
*/
struct stx104_iio {
unsigned chan_out_states[STX104_NUM_CHAN];
unsigned base;
};
static int stx104_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long mask)
{
struct stx104_iio *const priv = iio_priv(indio_dev);
if (mask != IIO_CHAN_INFO_RAW)
return -EINVAL;
*val = priv->chan_out_states[chan->channel];
return IIO_VAL_INT;
}
static int stx104_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long mask)
{
struct stx104_iio *const priv = iio_priv(indio_dev);
const unsigned chan_addr_offset = 2 * chan->channel;
if (mask != IIO_CHAN_INFO_RAW)
return -EINVAL;
priv->chan_out_states[chan->channel] = val;
outw(val, priv->base + 4 + chan_addr_offset);
return 0;
}
static const struct iio_info stx104_info = {
.driver_module = THIS_MODULE,
.read_raw = stx104_read_raw,
.write_raw = stx104_write_raw
};
static const struct iio_chan_spec stx104_channels[STX104_NUM_CHAN] = {
STX104_CHAN(0),
STX104_CHAN(1)
};
static int stx104_probe(struct device *dev, unsigned int id)
{
struct iio_dev *indio_dev;
struct stx104_iio *priv;
indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
if (!indio_dev)
return -ENOMEM;
if (!devm_request_region(dev, base[id], STX104_EXTENT,
dev_name(dev))) {
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
base[id], base[id] + STX104_EXTENT);
return -EBUSY;
}
indio_dev->info = &stx104_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = stx104_channels;
indio_dev->num_channels = STX104_NUM_CHAN;
indio_dev->name = dev_name(dev);
priv = iio_priv(indio_dev);
priv->base = base[id];
/* initialize DAC output to 0V */
outw(0, base[id] + 4);
outw(0, base[id] + 6);
return devm_iio_device_register(dev, indio_dev);
}
static struct isa_driver stx104_driver = {
.probe = stx104_probe,
.driver = {
.name = "stx104"
}
};
static void __exit stx104_exit(void)
{
isa_unregister_driver(&stx104_driver);
}
static int __init stx104_init(void)
{
return isa_register_driver(&stx104_driver, num_stx104);
}
module_init(stx104_init);
module_exit(stx104_exit);
MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
MODULE_DESCRIPTION("Apex Embedded Systems STX104 DAC driver");
MODULE_LICENSE("GPL v2");
drivers/iio/health/Kconfig
View file @ d9750a2f
......@@ -3,7 +3,34 @@
#
# When adding new entries keep the list in alphabetical order
menu "Health sensors"
menu "Health Sensors"
menu "Heart Rate Monitors"
config AFE4403
tristate "TI AFE4403 Heart Rate Monitor"
depends on SPI_MASTER
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Say yes to choose the Texas Instruments AFE4403
heart rate monitor and low-cost pulse oximeter.
To compile this driver as a module, choose M here: the
module will be called afe4403.
config AFE4404
tristate "TI AFE4404 heart rate and pulse oximeter sensor"
depends on I2C
select REGMAP_I2C
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Say yes to choose the Texas Instruments AFE4404
heart rate monitor and low-cost pulse oximeter.
To compile this driver as a module, choose M here: the
module will be called afe4404.
config MAX30100
tristate "MAX30100 heart rate and pulse oximeter sensor"
......@@ -19,3 +46,5 @@ config MAX30100
module will be called max30100.
endmenu
endmenu
drivers/iio/health/Makefile
View file @ d9750a2f
......@@ -4,4 +4,6 @@
# When adding new entries keep the list in alphabetical order
obj-$(CONFIG_AFE4403) += afe4403.o
obj-$(CONFIG_AFE4404) += afe4404.o
obj-$(CONFIG_MAX30100) += max30100.o
drivers/iio/health/afe4403.c 0 → 100644
View file @ d9750a2f
/*
* AFE4403 Heart Rate Monitors and Low-Cost Pulse Oximeters
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
* Andrew F. Davis <afd@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include "afe440x.h"
#define AFE4403_DRIVER_NAME "afe4403"
/* AFE4403 Registers */
#define AFE4403_TIAGAIN 0x20
#define AFE4403_TIA_AMB_GAIN 0x21
/* AFE4403 GAIN register fields */
#define AFE4403_TIAGAIN_RES_MASK GENMASK(2, 0)
#define AFE4403_TIAGAIN_RES_SHIFT 0
#define AFE4403_TIAGAIN_CAP_MASK GENMASK(7, 3)
#define AFE4403_TIAGAIN_CAP_SHIFT 3
/* AFE4403 LEDCNTRL register fields */
#define AFE440X_LEDCNTRL_LED1_MASK GENMASK(15, 8)
#define AFE440X_LEDCNTRL_LED1_SHIFT 8
#define AFE440X_LEDCNTRL_LED2_MASK GENMASK(7, 0)
#define AFE440X_LEDCNTRL_LED2_SHIFT 0
#define AFE440X_LEDCNTRL_LED_RANGE_MASK GENMASK(17, 16)
#define AFE440X_LEDCNTRL_LED_RANGE_SHIFT 16
/* AFE4403 CONTROL2 register fields */
#define AFE440X_CONTROL2_PWR_DWN_TX BIT(2)
#define AFE440X_CONTROL2_EN_SLOW_DIAG BIT(8)
#define AFE440X_CONTROL2_DIAG_OUT_TRI BIT(10)
#define AFE440X_CONTROL2_TX_BRDG_MOD BIT(11)
#define AFE440X_CONTROL2_TX_REF_MASK GENMASK(18, 17)
#define AFE440X_CONTROL2_TX_REF_SHIFT 17
/* AFE4404 NULL fields */
#define NULL_MASK 0
#define NULL_SHIFT 0
/* AFE4403 LEDCNTRL values */
#define AFE440X_LEDCNTRL_RANGE_TX_HALF 0x1
#define AFE440X_LEDCNTRL_RANGE_TX_FULL 0x2
#define AFE440X_LEDCNTRL_RANGE_TX_OFF 0x3
/* AFE4403 CONTROL2 values */
#define AFE440X_CONTROL2_TX_REF_025 0x0
#define AFE440X_CONTROL2_TX_REF_050 0x1
#define AFE440X_CONTROL2_TX_REF_100 0x2
#define AFE440X_CONTROL2_TX_REF_075 0x3
/* AFE4403 CONTROL3 values */
#define AFE440X_CONTROL3_CLK_DIV_2 0x0
#define AFE440X_CONTROL3_CLK_DIV_4 0x2
#define AFE440X_CONTROL3_CLK_DIV_6 0x3
#define AFE440X_CONTROL3_CLK_DIV_8 0x4
#define AFE440X_CONTROL3_CLK_DIV_12 0x5
#define AFE440X_CONTROL3_CLK_DIV_1 0x7
/* AFE4403 TIAGAIN_CAP values */
#define AFE4403_TIAGAIN_CAP_5_P 0x0
#define AFE4403_TIAGAIN_CAP_10_P 0x1
#define AFE4403_TIAGAIN_CAP_20_P 0x2
#define AFE4403_TIAGAIN_CAP_30_P 0x3
#define AFE4403_TIAGAIN_CAP_55_P 0x8
#define AFE4403_TIAGAIN_CAP_155_P 0x10
/* AFE4403 TIAGAIN_RES values */
#define AFE4403_TIAGAIN_RES_500_K 0x0
#define AFE4403_TIAGAIN_RES_250_K 0x1
#define AFE4403_TIAGAIN_RES_100_K 0x2
#define AFE4403_TIAGAIN_RES_50_K 0x3
#define AFE4403_TIAGAIN_RES_25_K 0x4
#define AFE4403_TIAGAIN_RES_10_K 0x5
#define AFE4403_TIAGAIN_RES_1_M 0x6
#define AFE4403_TIAGAIN_RES_NONE 0x7
/**
* struct afe4403_data
* @dev - Device structure
* @spi - SPI device handle
* @regmap - Register map of the device
* @regulator - Pointer to the regulator for the IC
* @trig - IIO trigger for this device
* @irq - ADC_RDY line interrupt number
*/
struct afe4403_data {
struct device *dev;
struct spi_device *spi;
struct regmap *regmap;
struct regulator *regulator;
struct iio_trigger *trig;
int irq;
};
enum afe4403_chan_id {
LED1,
ALED1,
LED2,
ALED2,
LED1_ALED1,
LED2_ALED2,
ILED1,
ILED2,
};
static const struct afe440x_reg_info afe4403_reg_info[] = {
[LED1] = AFE440X_REG_INFO(AFE440X_LED1VAL, 0, NULL),
[ALED1] = AFE440X_REG_INFO(AFE440X_ALED1VAL, 0, NULL),
[LED2] = AFE440X_REG_INFO(AFE440X_LED2VAL, 0, NULL),
[ALED2] = AFE440X_REG_INFO(AFE440X_ALED2VAL, 0, NULL),
[LED1_ALED1] = AFE440X_REG_INFO(AFE440X_LED1_ALED1VAL, 0, NULL),
[LED2_ALED2] = AFE440X_REG_INFO(AFE440X_LED2_ALED2VAL, 0, NULL),
[ILED1] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE440X_LEDCNTRL_LED1),
[ILED2] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE440X_LEDCNTRL_LED2),
};
static const struct iio_chan_spec afe4403_channels[] = {
/* ADC values */
AFE440X_INTENSITY_CHAN(LED1, "led1", 0),
AFE440X_INTENSITY_CHAN(ALED1, "led1_ambient", 0),
AFE440X_INTENSITY_CHAN(LED2, "led2", 0),
AFE440X_INTENSITY_CHAN(ALED2, "led2_ambient", 0),
AFE440X_INTENSITY_CHAN(LED1_ALED1, "led1-led1_ambient", 0),
AFE440X_INTENSITY_CHAN(LED2_ALED2, "led2-led2_ambient", 0),
/* LED current */
AFE440X_CURRENT_CHAN(ILED1, "led1"),
AFE440X_CURRENT_CHAN(ILED2, "led2"),
};
static const struct afe440x_val_table afe4403_res_table[] = {
{ 500000 }, { 250000 }, { 100000 }, { 50000 },
{ 25000 }, { 10000 }, { 1000000 }, { 0 },
};
AFE440X_TABLE_ATTR(tia_resistance_available, afe4403_res_table);
static const struct afe440x_val_table afe4403_cap_table[] = {
{ 0, 5000 }, { 0, 10000 }, { 0, 20000 }, { 0, 25000 },
{ 0, 30000 }, { 0, 35000 }, { 0, 45000 }, { 0, 50000 },
{ 0, 55000 }, { 0, 60000 }, { 0, 70000 }, { 0, 75000 },
{ 0, 80000 }, { 0, 85000 }, { 0, 95000 }, { 0, 100000 },
{ 0, 155000 }, { 0, 160000 }, { 0, 170000 }, { 0, 175000 },
{ 0, 180000 }, { 0, 185000 }, { 0, 195000 }, { 0, 200000 },
{ 0, 205000 }, { 0, 210000 }, { 0, 220000 }, { 0, 225000 },
{ 0, 230000 }, { 0, 235000 }, { 0, 245000 }, { 0, 250000 },
};
AFE440X_TABLE_ATTR(tia_capacitance_available, afe4403_cap_table);
static ssize_t afe440x_show_register(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4403_data *afe = iio_priv(indio_dev);
struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
unsigned int reg_val, type;
int vals[2];
int ret, val_len;
ret = regmap_read(afe->regmap, afe440x_attr->reg, &reg_val);
if (ret)
return ret;
reg_val &= afe440x_attr->mask;
reg_val >>= afe440x_attr->shift;
switch (afe440x_attr->type) {
case SIMPLE:
type = IIO_VAL_INT;
val_len = 1;
vals[0] = reg_val;
break;
case RESISTANCE:
case CAPACITANCE:
type = IIO_VAL_INT_PLUS_MICRO;
val_len = 2;
if (reg_val < afe440x_attr->table_size) {
vals[0] = afe440x_attr->val_table[reg_val].integer;
vals[1] = afe440x_attr->val_table[reg_val].fract;
break;
}
return -EINVAL;
default:
return -EINVAL;
}
return iio_format_value(buf, type, val_len, vals);
}
static ssize_t afe440x_store_register(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4403_data *afe = iio_priv(indio_dev);
struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
int val, integer, fract, ret;
ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
if (ret)
return ret;
switch (afe440x_attr->type) {
case SIMPLE:
val = integer;
break;
case RESISTANCE:
case CAPACITANCE:
for (val = 0; val < afe440x_attr->table_size; val++)
if (afe440x_attr->val_table[val].integer == integer &&
afe440x_attr->val_table[val].fract == fract)
break;
if (val == afe440x_attr->table_size)
return -EINVAL;
break;
default:
return -EINVAL;
}
ret = regmap_update_bits(afe->regmap, afe440x_attr->reg,
afe440x_attr->mask,
(val << afe440x_attr->shift));
if (ret)
return ret;
return count;
}
static AFE440X_ATTR(tia_separate_en, AFE4403_TIAGAIN, AFE440X_TIAGAIN_ENSEPGAIN, SIMPLE, NULL, 0);
static AFE440X_ATTR(tia_resistance1, AFE4403_TIAGAIN, AFE4403_TIAGAIN_RES, RESISTANCE, afe4403_res_table, ARRAY_SIZE(afe4403_res_table));
static AFE440X_ATTR(tia_capacitance1, AFE4403_TIAGAIN, AFE4403_TIAGAIN_CAP, CAPACITANCE, afe4403_cap_table, ARRAY_SIZE(afe4403_cap_table));
static AFE440X_ATTR(tia_resistance2, AFE4403_TIA_AMB_GAIN, AFE4403_TIAGAIN_RES, RESISTANCE, afe4403_res_table, ARRAY_SIZE(afe4403_res_table));
static AFE440X_ATTR(tia_capacitance2, AFE4403_TIA_AMB_GAIN, AFE4403_TIAGAIN_RES, CAPACITANCE, afe4403_cap_table, ARRAY_SIZE(afe4403_cap_table));
static struct attribute *afe440x_attributes[] = {
&afe440x_attr_tia_separate_en.dev_attr.attr,
&afe440x_attr_tia_resistance1.dev_attr.attr,
&afe440x_attr_tia_capacitance1.dev_attr.attr,
&afe440x_attr_tia_resistance2.dev_attr.attr,
&afe440x_attr_tia_capacitance2.dev_attr.attr,
&dev_attr_tia_resistance_available.attr,
&dev_attr_tia_capacitance_available.attr,
NULL
};
static const struct attribute_group afe440x_attribute_group = {
.attrs = afe440x_attributes
};
static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val)
{
u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
u8 rx[3];
int ret;
/* Enable reading from the device */
ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
if (ret)
return ret;
ret = spi_write_then_read(afe->spi, &reg, 1, rx, 3);
if (ret)
return ret;
*val = (rx[0] << 16) |
(rx[1] << 8) |
(rx[2]);
/* Disable reading from the device */
tx[3] = AFE440X_CONTROL0_WRITE;
ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
if (ret)
return ret;
return 0;
}
static int afe4403_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct afe4403_data *afe = iio_priv(indio_dev);
const struct afe440x_reg_info reg_info = afe4403_reg_info[chan->address];
int ret;
switch (chan->type) {
case IIO_INTENSITY:
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = afe4403_read(afe, reg_info.reg, val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
ret = regmap_read(afe->regmap, reg_info.offreg,
val);
if (ret)
return ret;
*val &= reg_info.mask;
*val >>= reg_info.shift;
return IIO_VAL_INT;
}
break;
case IIO_CURRENT:
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = regmap_read(afe->regmap, reg_info.reg, val);
if (ret)
return ret;
*val &= reg_info.mask;
*val >>= reg_info.shift;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 0;
*val2 = 800000;
return IIO_VAL_INT_PLUS_MICRO;
}
break;
default:
break;
}
return -EINVAL;
}
static int afe4403_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct afe4403_data *afe = iio_priv(indio_dev);
const struct afe440x_reg_info reg_info = afe4403_reg_info[chan->address];
switch (chan->type) {
case IIO_INTENSITY:
switch (mask) {
case IIO_CHAN_INFO_OFFSET:
return regmap_update_bits(afe->regmap,
reg_info.offreg,
reg_info.mask,
(val << reg_info.shift));
}
break;
case IIO_CURRENT:
switch (mask) {
case IIO_CHAN_INFO_RAW:
return regmap_update_bits(afe->regmap,
reg_info.reg,
reg_info.mask,
(val << reg_info.shift));
}
break;
default:
break;
}
return -EINVAL;
}
static const struct iio_info afe4403_iio_info = {
.attrs = &afe440x_attribute_group,
.read_raw = afe4403_read_raw,
.write_raw = afe4403_write_raw,
.driver_module = THIS_MODULE,
};
static irqreturn_t afe4403_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct afe4403_data *afe = iio_priv(indio_dev);
int ret, bit, i = 0;
s32 buffer[8];
u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
u8 rx[3];
/* Enable reading from the device */
ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
if (ret)
goto err;
for_each_set_bit(bit, indio_dev->active_scan_mask,
indio_dev->masklength) {
ret = spi_write_then_read(afe->spi,
&afe4403_reg_info[bit].reg, 1,
rx, 3);
if (ret)
goto err;
buffer[i++] = (rx[0] << 16) |
(rx[1] << 8) |
(rx[2]);
}
/* Disable reading from the device */
tx[3] = AFE440X_CONTROL0_WRITE;
ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
if (ret)
goto err;
iio_push_to_buffers_with_timestamp(indio_dev, buffer, pf->timestamp);
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static const struct iio_trigger_ops afe4403_trigger_ops = {
.owner = THIS_MODULE,
};
#define AFE4403_TIMING_PAIRS \
{ AFE440X_LED2STC, 0x000050 }, \
{ AFE440X_LED2ENDC, 0x0003e7 }, \
{ AFE440X_LED1LEDSTC, 0x0007d0 }, \
{ AFE440X_LED1LEDENDC, 0x000bb7 }, \
{ AFE440X_ALED2STC, 0x000438 }, \
{ AFE440X_ALED2ENDC, 0x0007cf }, \
{ AFE440X_LED1STC, 0x000820 }, \
{ AFE440X_LED1ENDC, 0x000bb7 }, \
{ AFE440X_LED2LEDSTC, 0x000000 }, \
{ AFE440X_LED2LEDENDC, 0x0003e7 }, \
{ AFE440X_ALED1STC, 0x000c08 }, \
{ AFE440X_ALED1ENDC, 0x000f9f }, \
{ AFE440X_LED2CONVST, 0x0003ef }, \
{ AFE440X_LED2CONVEND, 0x0007cf }, \
{ AFE440X_ALED2CONVST, 0x0007d7 }, \
{ AFE440X_ALED2CONVEND, 0x000bb7 }, \
{ AFE440X_LED1CONVST, 0x000bbf }, \
{ AFE440X_LED1CONVEND, 0x009c3f }, \
{ AFE440X_ALED1CONVST, 0x000fa7 }, \
{ AFE440X_ALED1CONVEND, 0x001387 }, \
{ AFE440X_ADCRSTSTCT0, 0x0003e8 }, \
{ AFE440X_ADCRSTENDCT0, 0x0003eb }, \
{ AFE440X_ADCRSTSTCT1, 0x0007d0 }, \
{ AFE440X_ADCRSTENDCT1, 0x0007d3 }, \
{ AFE440X_ADCRSTSTCT2, 0x000bb8 }, \
{ AFE440X_ADCRSTENDCT2, 0x000bbb }, \
{ AFE440X_ADCRSTSTCT3, 0x000fa0 }, \
{ AFE440X_ADCRSTENDCT3, 0x000fa3 }, \
{ AFE440X_PRPCOUNT, 0x009c3f }, \
{ AFE440X_PDNCYCLESTC, 0x001518 }, \
{ AFE440X_PDNCYCLEENDC, 0x00991f }
static const struct reg_sequence afe4403_reg_sequences[] = {
AFE4403_TIMING_PAIRS,
{ AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN | 0x000007},
{ AFE4403_TIA_AMB_GAIN, AFE4403_TIAGAIN_RES_1_M },
{ AFE440X_LEDCNTRL, (0x14 << AFE440X_LEDCNTRL_LED1_SHIFT) |
(0x14 << AFE440X_LEDCNTRL_LED2_SHIFT) },
{ AFE440X_CONTROL2, AFE440X_CONTROL2_TX_REF_050 <<
AFE440X_CONTROL2_TX_REF_SHIFT },
};
static const struct regmap_range afe4403_yes_ranges[] = {
regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
};
static const struct regmap_access_table afe4403_volatile_table = {
.yes_ranges = afe4403_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(afe4403_yes_ranges),
};
static const struct regmap_config afe4403_regmap_config = {
.reg_bits = 8,
.val_bits = 24,
.max_register = AFE440X_PDNCYCLEENDC,
.cache_type = REGCACHE_RBTREE,
.volatile_table = &afe4403_volatile_table,
};
#ifdef CONFIG_OF
static const struct of_device_id afe4403_of_match[] = {
{ .compatible = "ti,afe4403", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, afe4403_of_match);
#endif
static int afe4403_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4403_data *afe = iio_priv(indio_dev);
int ret;
ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
AFE440X_CONTROL2_PDN_AFE,
AFE440X_CONTROL2_PDN_AFE);
if (ret)
return ret;
ret = regulator_disable(afe->regulator);
if (ret) {
dev_err(dev, "Unable to disable regulator\n");
return ret;
}
return 0;
}
static int afe4403_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4403_data *afe = iio_priv(indio_dev);
int ret;
ret = regulator_enable(afe->regulator);
if (ret) {
dev_err(dev, "Unable to enable regulator\n");
return ret;
}
ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
AFE440X_CONTROL2_PDN_AFE, 0);
if (ret)
return ret;
return 0;
}
static SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend, afe4403_resume);
static int afe4403_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct afe4403_data *afe;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*afe));
if (!indio_dev)
return -ENOMEM;
afe = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
afe->dev = &spi->dev;
afe->spi = spi;
afe->irq = spi->irq;
afe->regmap = devm_regmap_init_spi(spi, &afe4403_regmap_config);
if (IS_ERR(afe->regmap)) {
dev_err(afe->dev, "Unable to allocate register map\n");
return PTR_ERR(afe->regmap);
}
afe->regulator = devm_regulator_get(afe->dev, "tx_sup");
if (IS_ERR(afe->regulator)) {
dev_err(afe->dev, "Unable to get regulator\n");
return PTR_ERR(afe->regulator);
}
ret = regulator_enable(afe->regulator);
if (ret) {
dev_err(afe->dev, "Unable to enable regulator\n");
return ret;
}
ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
AFE440X_CONTROL0_SW_RESET);
if (ret) {
dev_err(afe->dev, "Unable to reset device\n");
goto err_disable_reg;
}
ret = regmap_multi_reg_write(afe->regmap, afe4403_reg_sequences,
ARRAY_SIZE(afe4403_reg_sequences));
if (ret) {
dev_err(afe->dev, "Unable to set register defaults\n");
goto err_disable_reg;
}
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->dev.parent = afe->dev;
indio_dev->channels = afe4403_channels;
indio_dev->num_channels = ARRAY_SIZE(afe4403_channels);
indio_dev->name = AFE4403_DRIVER_NAME;
indio_dev->info = &afe4403_iio_info;
if (afe->irq > 0) {
afe->trig = devm_iio_trigger_alloc(afe->dev,
"%s-dev%d",
indio_dev->name,
indio_dev->id);
if (!afe->trig) {
dev_err(afe->dev, "Unable to allocate IIO trigger\n");
ret = -ENOMEM;
goto err_disable_reg;
}
iio_trigger_set_drvdata(afe->trig, indio_dev);
afe->trig->ops = &afe4403_trigger_ops;
afe->trig->dev.parent = afe->dev;
ret = iio_trigger_register(afe->trig);
if (ret) {
dev_err(afe->dev, "Unable to register IIO trigger\n");
goto err_disable_reg;
}
ret = devm_request_threaded_irq(afe->dev, afe->irq,
iio_trigger_generic_data_rdy_poll,
NULL, IRQF_ONESHOT,
AFE4403_DRIVER_NAME,
afe->trig);
if (ret) {
dev_err(afe->dev, "Unable to request IRQ\n");
goto err_trig;
}
}
ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
afe4403_trigger_handler, NULL);
if (ret) {
dev_err(afe->dev, "Unable to setup buffer\n");
goto err_trig;
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(afe->dev, "Unable to register IIO device\n");
goto err_buff;
}
return 0;
err_buff:
iio_triggered_buffer_cleanup(indio_dev);
err_trig:
if (afe->irq > 0)
iio_trigger_unregister(afe->trig);
err_disable_reg:
regulator_disable(afe->regulator);
return ret;
}
static int afe4403_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct afe4403_data *afe = iio_priv(indio_dev);
int ret;
iio_device_unregister(indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
if (afe->irq > 0)
iio_trigger_unregister(afe->trig);
ret = regulator_disable(afe->regulator);
if (ret) {
dev_err(afe->dev, "Unable to disable regulator\n");
return ret;
}
return 0;
}
static const struct spi_device_id afe4403_ids[] = {
{ "afe4403", 0 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(spi, afe4403_ids);
static struct spi_driver afe4403_spi_driver = {
.driver = {
.name = AFE4403_DRIVER_NAME,
.of_match_table = of_match_ptr(afe4403_of_match),
.pm = &afe4403_pm_ops,
},
.probe = afe4403_probe,
.remove = afe4403_remove,
.id_table = afe4403_ids,
};
module_spi_driver(afe4403_spi_driver);
MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
MODULE_DESCRIPTION("TI AFE4403 Heart Rate and Pulse Oximeter");
MODULE_LICENSE("GPL v2");
drivers/iio/health/afe4404.c 0 → 100644
View file @ d9750a2f
/*
* AFE4404 Heart Rate Monitors and Low-Cost Pulse Oximeters
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
* Andrew F. Davis <afd@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include "afe440x.h"
#define AFE4404_DRIVER_NAME "afe4404"
/* AFE4404 registers */
#define AFE4404_TIA_GAIN_SEP 0x20
#define AFE4404_TIA_GAIN 0x21
#define AFE4404_PROG_TG_STC 0x34
#define AFE4404_PROG_TG_ENDC 0x35
#define AFE4404_LED3LEDSTC 0x36
#define AFE4404_LED3LEDENDC 0x37
#define AFE4404_CLKDIV_PRF 0x39
#define AFE4404_OFFDAC 0x3a
#define AFE4404_DEC 0x3d
#define AFE4404_AVG_LED2_ALED2VAL 0x3f
#define AFE4404_AVG_LED1_ALED1VAL 0x40
/* AFE4404 GAIN register fields */
#define AFE4404_TIA_GAIN_RES_MASK GENMASK(2, 0)
#define AFE4404_TIA_GAIN_RES_SHIFT 0
#define AFE4404_TIA_GAIN_CAP_MASK GENMASK(5, 3)
#define AFE4404_TIA_GAIN_CAP_SHIFT 3
/* AFE4404 LEDCNTRL register fields */
#define AFE4404_LEDCNTRL_ILED1_MASK GENMASK(5, 0)
#define AFE4404_LEDCNTRL_ILED1_SHIFT 0
#define AFE4404_LEDCNTRL_ILED2_MASK GENMASK(11, 6)
#define AFE4404_LEDCNTRL_ILED2_SHIFT 6
#define AFE4404_LEDCNTRL_ILED3_MASK GENMASK(17, 12)
#define AFE4404_LEDCNTRL_ILED3_SHIFT 12
/* AFE4404 CONTROL2 register fields */
#define AFE440X_CONTROL2_ILED_2X_MASK BIT(17)
#define AFE440X_CONTROL2_ILED_2X_SHIFT 17
/* AFE4404 CONTROL3 register fields */
#define AFE440X_CONTROL3_OSC_ENABLE BIT(9)
/* AFE4404 OFFDAC register current fields */
#define AFE4404_OFFDAC_CURR_LED1_MASK GENMASK(9, 5)
#define AFE4404_OFFDAC_CURR_LED1_SHIFT 5
#define AFE4404_OFFDAC_CURR_LED2_MASK GENMASK(19, 15)
#define AFE4404_OFFDAC_CURR_LED2_SHIFT 15
#define AFE4404_OFFDAC_CURR_LED3_MASK GENMASK(4, 0)
#define AFE4404_OFFDAC_CURR_LED3_SHIFT 0
#define AFE4404_OFFDAC_CURR_ALED1_MASK GENMASK(14, 10)
#define AFE4404_OFFDAC_CURR_ALED1_SHIFT 10
#define AFE4404_OFFDAC_CURR_ALED2_MASK GENMASK(4, 0)
#define AFE4404_OFFDAC_CURR_ALED2_SHIFT 0
/* AFE4404 NULL fields */
#define NULL_MASK 0
#define NULL_SHIFT 0
/* AFE4404 TIA_GAIN_CAP values */
#define AFE4404_TIA_GAIN_CAP_5_P 0x0
#define AFE4404_TIA_GAIN_CAP_2_5_P 0x1
#define AFE4404_TIA_GAIN_CAP_10_P 0x2
#define AFE4404_TIA_GAIN_CAP_7_5_P 0x3
#define AFE4404_TIA_GAIN_CAP_20_P 0x4
#define AFE4404_TIA_GAIN_CAP_17_5_P 0x5
#define AFE4404_TIA_GAIN_CAP_25_P 0x6
#define AFE4404_TIA_GAIN_CAP_22_5_P 0x7
/* AFE4404 TIA_GAIN_RES values */
#define AFE4404_TIA_GAIN_RES_500_K 0x0
#define AFE4404_TIA_GAIN_RES_250_K 0x1
#define AFE4404_TIA_GAIN_RES_100_K 0x2
#define AFE4404_TIA_GAIN_RES_50_K 0x3
#define AFE4404_TIA_GAIN_RES_25_K 0x4
#define AFE4404_TIA_GAIN_RES_10_K 0x5
#define AFE4404_TIA_GAIN_RES_1_M 0x6
#define AFE4404_TIA_GAIN_RES_2_M 0x7
/**
* struct afe4404_data
* @dev - Device structure
* @regmap - Register map of the device
* @regulator - Pointer to the regulator for the IC
* @trig - IIO trigger for this device
* @irq - ADC_RDY line interrupt number
*/
struct afe4404_data {
struct device *dev;
struct regmap *regmap;
struct regulator *regulator;
struct iio_trigger *trig;
int irq;
};
enum afe4404_chan_id {
LED1,
ALED1,
LED2,
ALED2,
LED3,
LED1_ALED1,
LED2_ALED2,
ILED1,
ILED2,
ILED3,
};
static const struct afe440x_reg_info afe4404_reg_info[] = {
[LED1] = AFE440X_REG_INFO(AFE440X_LED1VAL, AFE4404_OFFDAC, AFE4404_OFFDAC_CURR_LED1),
[ALED1] = AFE440X_REG_INFO(AFE440X_ALED1VAL, AFE4404_OFFDAC, AFE4404_OFFDAC_CURR_ALED1),
[LED2] = AFE440X_REG_INFO(AFE440X_LED2VAL, AFE4404_OFFDAC, AFE4404_OFFDAC_CURR_LED2),
[ALED2] = AFE440X_REG_INFO(AFE440X_ALED2VAL, AFE4404_OFFDAC, AFE4404_OFFDAC_CURR_ALED2),
[LED3] = AFE440X_REG_INFO(AFE440X_ALED2VAL, 0, NULL),
[LED1_ALED1] = AFE440X_REG_INFO(AFE440X_LED1_ALED1VAL, 0, NULL),
[LED2_ALED2] = AFE440X_REG_INFO(AFE440X_LED2_ALED2VAL, 0, NULL),
[ILED1] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE4404_LEDCNTRL_ILED1),
[ILED2] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE4404_LEDCNTRL_ILED2),
[ILED3] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE4404_LEDCNTRL_ILED3),
};
static const struct iio_chan_spec afe4404_channels[] = {
/* ADC values */
AFE440X_INTENSITY_CHAN(LED1, "led1", BIT(IIO_CHAN_INFO_OFFSET)),
AFE440X_INTENSITY_CHAN(ALED1, "led1_ambient", BIT(IIO_CHAN_INFO_OFFSET)),
AFE440X_INTENSITY_CHAN(LED2, "led2", BIT(IIO_CHAN_INFO_OFFSET)),
AFE440X_INTENSITY_CHAN(ALED2, "led2_ambient", BIT(IIO_CHAN_INFO_OFFSET)),
AFE440X_INTENSITY_CHAN(LED3, "led3", BIT(IIO_CHAN_INFO_OFFSET)),
AFE440X_INTENSITY_CHAN(LED1_ALED1, "led1-led1_ambient", 0),
AFE440X_INTENSITY_CHAN(LED2_ALED2, "led2-led2_ambient", 0),
/* LED current */
AFE440X_CURRENT_CHAN(ILED1, "led1"),
AFE440X_CURRENT_CHAN(ILED2, "led2"),
AFE440X_CURRENT_CHAN(ILED3, "led3"),
};
static const struct afe440x_val_table afe4404_res_table[] = {
{ .integer = 500000, .fract = 0 },
{ .integer = 250000, .fract = 0 },
{ .integer = 100000, .fract = 0 },
{ .integer = 50000, .fract = 0 },
{ .integer = 25000, .fract = 0 },
{ .integer = 10000, .fract = 0 },
{ .integer = 1000000, .fract = 0 },
{ .integer = 2000000, .fract = 0 },
};
AFE440X_TABLE_ATTR(tia_resistance_available, afe4404_res_table);
static const struct afe440x_val_table afe4404_cap_table[] = {
{ .integer = 0, .fract = 5000 },
{ .integer = 0, .fract = 2500 },
{ .integer = 0, .fract = 10000 },
{ .integer = 0, .fract = 7500 },
{ .integer = 0, .fract = 20000 },
{ .integer = 0, .fract = 17500 },
{ .integer = 0, .fract = 25000 },
{ .integer = 0, .fract = 22500 },
};
AFE440X_TABLE_ATTR(tia_capacitance_available, afe4404_cap_table);
static ssize_t afe440x_show_register(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4404_data *afe = iio_priv(indio_dev);
struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
unsigned int reg_val, type;
int vals[2];
int ret, val_len;
ret = regmap_read(afe->regmap, afe440x_attr->reg, &reg_val);
if (ret)
return ret;
reg_val &= afe440x_attr->mask;
reg_val >>= afe440x_attr->shift;
switch (afe440x_attr->type) {
case SIMPLE:
type = IIO_VAL_INT;
val_len = 1;
vals[0] = reg_val;
break;
case RESISTANCE:
case CAPACITANCE:
type = IIO_VAL_INT_PLUS_MICRO;
val_len = 2;
if (reg_val < afe440x_attr->table_size) {
vals[0] = afe440x_attr->val_table[reg_val].integer;
vals[1] = afe440x_attr->val_table[reg_val].fract;
break;
}
return -EINVAL;
default:
return -EINVAL;
}
return iio_format_value(buf, type, val_len, vals);
}
static ssize_t afe440x_store_register(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4404_data *afe = iio_priv(indio_dev);
struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
int val, integer, fract, ret;
ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
if (ret)
return ret;
switch (afe440x_attr->type) {
case SIMPLE:
val = integer;
break;
case RESISTANCE:
case CAPACITANCE:
for (val = 0; val < afe440x_attr->table_size; val++)
if (afe440x_attr->val_table[val].integer == integer &&
afe440x_attr->val_table[val].fract == fract)
break;
if (val == afe440x_attr->table_size)
return -EINVAL;
break;
default:
return -EINVAL;
}
ret = regmap_update_bits(afe->regmap, afe440x_attr->reg,
afe440x_attr->mask,
(val << afe440x_attr->shift));
if (ret)
return ret;
return count;
}
static AFE440X_ATTR(tia_separate_en, AFE4404_TIA_GAIN_SEP, AFE440X_TIAGAIN_ENSEPGAIN, SIMPLE, NULL, 0);
static AFE440X_ATTR(tia_resistance1, AFE4404_TIA_GAIN, AFE4404_TIA_GAIN_RES, RESISTANCE, afe4404_res_table, ARRAY_SIZE(afe4404_res_table));
static AFE440X_ATTR(tia_capacitance1, AFE4404_TIA_GAIN, AFE4404_TIA_GAIN_CAP, CAPACITANCE, afe4404_cap_table, ARRAY_SIZE(afe4404_cap_table));
static AFE440X_ATTR(tia_resistance2, AFE4404_TIA_GAIN_SEP, AFE4404_TIA_GAIN_RES, RESISTANCE, afe4404_res_table, ARRAY_SIZE(afe4404_res_table));
static AFE440X_ATTR(tia_capacitance2, AFE4404_TIA_GAIN_SEP, AFE4404_TIA_GAIN_CAP, CAPACITANCE, afe4404_cap_table, ARRAY_SIZE(afe4404_cap_table));
static struct attribute *afe440x_attributes[] = {
&afe440x_attr_tia_separate_en.dev_attr.attr,
&afe440x_attr_tia_resistance1.dev_attr.attr,
&afe440x_attr_tia_capacitance1.dev_attr.attr,
&afe440x_attr_tia_resistance2.dev_attr.attr,
&afe440x_attr_tia_capacitance2.dev_attr.attr,
&dev_attr_tia_resistance_available.attr,
&dev_attr_tia_capacitance_available.attr,
NULL
};
static const struct attribute_group afe440x_attribute_group = {
.attrs = afe440x_attributes
};
static int afe4404_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct afe4404_data *afe = iio_priv(indio_dev);
const struct afe440x_reg_info reg_info = afe4404_reg_info[chan->address];
int ret;
switch (chan->type) {
case IIO_INTENSITY:
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = regmap_read(afe->regmap, reg_info.reg, val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
ret = regmap_read(afe->regmap, reg_info.offreg,
val);
if (ret)
return ret;
*val &= reg_info.mask;
*val >>= reg_info.shift;
return IIO_VAL_INT;
}
break;
case IIO_CURRENT:
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = regmap_read(afe->regmap, reg_info.reg, val);
if (ret)
return ret;
*val &= reg_info.mask;
*val >>= reg_info.shift;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 0;
*val2 = 800000;
return IIO_VAL_INT_PLUS_MICRO;
}
break;
default:
break;
}
return -EINVAL;
}
static int afe4404_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct afe4404_data *afe = iio_priv(indio_dev);
const struct afe440x_reg_info reg_info = afe4404_reg_info[chan->address];
switch (chan->type) {
case IIO_INTENSITY:
switch (mask) {
case IIO_CHAN_INFO_OFFSET:
return regmap_update_bits(afe->regmap,
reg_info.offreg,
reg_info.mask,
(val << reg_info.shift));
}
break;
case IIO_CURRENT:
switch (mask) {
case IIO_CHAN_INFO_RAW:
return regmap_update_bits(afe->regmap,
reg_info.reg,
reg_info.mask,
(val << reg_info.shift));
}
break;
default:
break;
}
return -EINVAL;
}
static const struct iio_info afe4404_iio_info = {
.attrs = &afe440x_attribute_group,
.read_raw = afe4404_read_raw,
.write_raw = afe4404_write_raw,
.driver_module = THIS_MODULE,
};
static irqreturn_t afe4404_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct afe4404_data *afe = iio_priv(indio_dev);
int ret, bit, i = 0;
s32 buffer[10];
for_each_set_bit(bit, indio_dev->active_scan_mask,
indio_dev->masklength) {
ret = regmap_read(afe->regmap, afe4404_reg_info[bit].reg,
&buffer[i++]);
if (ret)
goto err;
}
iio_push_to_buffers_with_timestamp(indio_dev, buffer, pf->timestamp);
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static const struct iio_trigger_ops afe4404_trigger_ops = {
.owner = THIS_MODULE,
};
/* Default timings from data-sheet */
#define AFE4404_TIMING_PAIRS \
{ AFE440X_PRPCOUNT, 39999 }, \
{ AFE440X_LED2LEDSTC, 0 }, \
{ AFE440X_LED2LEDENDC, 398 }, \
{ AFE440X_LED2STC, 80 }, \
{ AFE440X_LED2ENDC, 398 }, \
{ AFE440X_ADCRSTSTCT0, 5600 }, \
{ AFE440X_ADCRSTENDCT0, 5606 }, \
{ AFE440X_LED2CONVST, 5607 }, \
{ AFE440X_LED2CONVEND, 6066 }, \
{ AFE4404_LED3LEDSTC, 400 }, \
{ AFE4404_LED3LEDENDC, 798 }, \
{ AFE440X_ALED2STC, 480 }, \
{ AFE440X_ALED2ENDC, 798 }, \
{ AFE440X_ADCRSTSTCT1, 6068 }, \
{ AFE440X_ADCRSTENDCT1, 6074 }, \
{ AFE440X_ALED2CONVST, 6075 }, \
{ AFE440X_ALED2CONVEND, 6534 }, \
{ AFE440X_LED1LEDSTC, 800 }, \
{ AFE440X_LED1LEDENDC, 1198 }, \
{ AFE440X_LED1STC, 880 }, \
{ AFE440X_LED1ENDC, 1198 }, \
{ AFE440X_ADCRSTSTCT2, 6536 }, \
{ AFE440X_ADCRSTENDCT2, 6542 }, \
{ AFE440X_LED1CONVST, 6543 }, \
{ AFE440X_LED1CONVEND, 7003 }, \
{ AFE440X_ALED1STC, 1280 }, \
{ AFE440X_ALED1ENDC, 1598 }, \
{ AFE440X_ADCRSTSTCT3, 7005 }, \
{ AFE440X_ADCRSTENDCT3, 7011 }, \
{ AFE440X_ALED1CONVST, 7012 }, \
{ AFE440X_ALED1CONVEND, 7471 }, \
{ AFE440X_PDNCYCLESTC, 7671 }, \
{ AFE440X_PDNCYCLEENDC, 39199 }
static const struct reg_sequence afe4404_reg_sequences[] = {
AFE4404_TIMING_PAIRS,
{ AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN },
{ AFE4404_TIA_GAIN, AFE4404_TIA_GAIN_RES_50_K },
{ AFE440X_LEDCNTRL, (0xf << AFE4404_LEDCNTRL_ILED1_SHIFT) |
(0x3 << AFE4404_LEDCNTRL_ILED2_SHIFT) |
(0x3 << AFE4404_LEDCNTRL_ILED3_SHIFT) },
{ AFE440X_CONTROL2, AFE440X_CONTROL3_OSC_ENABLE },
};
static const struct regmap_range afe4404_yes_ranges[] = {
regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
regmap_reg_range(AFE4404_AVG_LED2_ALED2VAL, AFE4404_AVG_LED1_ALED1VAL),
};
static const struct regmap_access_table afe4404_volatile_table = {
.yes_ranges = afe4404_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(afe4404_yes_ranges),
};
static const struct regmap_config afe4404_regmap_config = {
.reg_bits = 8,
.val_bits = 24,
.max_register = AFE4404_AVG_LED1_ALED1VAL,
.cache_type = REGCACHE_RBTREE,
.volatile_table = &afe4404_volatile_table,
};
#ifdef CONFIG_OF
static const struct of_device_id afe4404_of_match[] = {
{ .compatible = "ti,afe4404", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, afe4404_of_match);
#endif
static int afe4404_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4404_data *afe = iio_priv(indio_dev);
int ret;
ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
AFE440X_CONTROL2_PDN_AFE,
AFE440X_CONTROL2_PDN_AFE);
if (ret)
return ret;
ret = regulator_disable(afe->regulator);
if (ret) {
dev_err(dev, "Unable to disable regulator\n");
return ret;
}
return 0;
}
static int afe4404_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4404_data *afe = iio_priv(indio_dev);
int ret;
ret = regulator_enable(afe->regulator);
if (ret) {
dev_err(dev, "Unable to enable regulator\n");
return ret;
}
ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
AFE440X_CONTROL2_PDN_AFE, 0);
if (ret)
return ret;
return 0;
}
static SIMPLE_DEV_PM_OPS(afe4404_pm_ops, afe4404_suspend, afe4404_resume);
static int afe4404_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct iio_dev *indio_dev;
struct afe4404_data *afe;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*afe));
if (!indio_dev)
return -ENOMEM;
afe = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
afe->dev = &client->dev;
afe->irq = client->irq;
afe->regmap = devm_regmap_init_i2c(client, &afe4404_regmap_config);
if (IS_ERR(afe->regmap)) {
dev_err(afe->dev, "Unable to allocate register map\n");
return PTR_ERR(afe->regmap);
}
afe->regulator = devm_regulator_get(afe->dev, "tx_sup");
if (IS_ERR(afe->regulator)) {
dev_err(afe->dev, "Unable to get regulator\n");
return PTR_ERR(afe->regulator);
}
ret = regulator_enable(afe->regulator);
if (ret) {
dev_err(afe->dev, "Unable to enable regulator\n");
return ret;
}
ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
AFE440X_CONTROL0_SW_RESET);
if (ret) {
dev_err(afe->dev, "Unable to reset device\n");
goto disable_reg;
}
ret = regmap_multi_reg_write(afe->regmap, afe4404_reg_sequences,
ARRAY_SIZE(afe4404_reg_sequences));
if (ret) {
dev_err(afe->dev, "Unable to set register defaults\n");
goto disable_reg;
}
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->dev.parent = afe->dev;
indio_dev->channels = afe4404_channels;
indio_dev->num_channels = ARRAY_SIZE(afe4404_channels);
indio_dev->name = AFE4404_DRIVER_NAME;
indio_dev->info = &afe4404_iio_info;
if (afe->irq > 0) {
afe->trig = devm_iio_trigger_alloc(afe->dev,
"%s-dev%d",
indio_dev->name,
indio_dev->id);
if (!afe->trig) {
dev_err(afe->dev, "Unable to allocate IIO trigger\n");
ret = -ENOMEM;
goto disable_reg;
}
iio_trigger_set_drvdata(afe->trig, indio_dev);
afe->trig->ops = &afe4404_trigger_ops;
afe->trig->dev.parent = afe->dev;
ret = iio_trigger_register(afe->trig);
if (ret) {
dev_err(afe->dev, "Unable to register IIO trigger\n");
goto disable_reg;
}
ret = devm_request_threaded_irq(afe->dev, afe->irq,
iio_trigger_generic_data_rdy_poll,
NULL, IRQF_ONESHOT,
AFE4404_DRIVER_NAME,
afe->trig);
if (ret) {
dev_err(afe->dev, "Unable to request IRQ\n");
goto disable_reg;
}
}
ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
afe4404_trigger_handler, NULL);
if (ret) {
dev_err(afe->dev, "Unable to setup buffer\n");
goto unregister_trigger;
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(afe->dev, "Unable to register IIO device\n");
goto unregister_triggered_buffer;
}
return 0;
unregister_triggered_buffer:
iio_triggered_buffer_cleanup(indio_dev);
unregister_trigger:
if (afe->irq > 0)
iio_trigger_unregister(afe->trig);
disable_reg:
regulator_disable(afe->regulator);
return ret;
}
static int afe4404_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct afe4404_data *afe = iio_priv(indio_dev);
int ret;
iio_device_unregister(indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
if (afe->irq > 0)
iio_trigger_unregister(afe->trig);
ret = regulator_disable(afe->regulator);
if (ret) {
dev_err(afe->dev, "Unable to disable regulator\n");
return ret;
}
return 0;
}
static const struct i2c_device_id afe4404_ids[] = {
{ "afe4404", 0 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(i2c, afe4404_ids);
static struct i2c_driver afe4404_i2c_driver = {
.driver = {
.name = AFE4404_DRIVER_NAME,
.of_match_table = of_match_ptr(afe4404_of_match),
.pm = &afe4404_pm_ops,
},
.probe = afe4404_probe,
.remove = afe4404_remove,
.id_table = afe4404_ids,
};
module_i2c_driver(afe4404_i2c_driver);
MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
MODULE_DESCRIPTION("TI AFE4404 Heart Rate and Pulse Oximeter");
MODULE_LICENSE("GPL v2");
drivers/iio/health/afe440x.h 0 → 100644
View file @ d9750a2f
/*
* AFE440X Heart Rate Monitors and Low-Cost Pulse Oximeters
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
* Andrew F. Davis <afd@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#ifndef _AFE440X_H
#define _AFE440X_H
/* AFE440X registers */
#define AFE440X_CONTROL0 0x00
#define AFE440X_LED2STC 0x01
#define AFE440X_LED2ENDC 0x02
#define AFE440X_LED1LEDSTC 0x03
#define AFE440X_LED1LEDENDC 0x04
#define AFE440X_ALED2STC 0x05
#define AFE440X_ALED2ENDC 0x06
#define AFE440X_LED1STC 0x07
#define AFE440X_LED1ENDC 0x08
#define AFE440X_LED2LEDSTC 0x09
#define AFE440X_LED2LEDENDC 0x0a
#define AFE440X_ALED1STC 0x0b
#define AFE440X_ALED1ENDC 0x0c
#define AFE440X_LED2CONVST 0x0d
#define AFE440X_LED2CONVEND 0x0e
#define AFE440X_ALED2CONVST 0x0f
#define AFE440X_ALED2CONVEND 0x10
#define AFE440X_LED1CONVST 0x11
#define AFE440X_LED1CONVEND 0x12
#define AFE440X_ALED1CONVST 0x13
#define AFE440X_ALED1CONVEND 0x14
#define AFE440X_ADCRSTSTCT0 0x15
#define AFE440X_ADCRSTENDCT0 0x16
#define AFE440X_ADCRSTSTCT1 0x17
#define AFE440X_ADCRSTENDCT1 0x18
#define AFE440X_ADCRSTSTCT2 0x19
#define AFE440X_ADCRSTENDCT2 0x1a
#define AFE440X_ADCRSTSTCT3 0x1b
#define AFE440X_ADCRSTENDCT3 0x1c
#define AFE440X_PRPCOUNT 0x1d
#define AFE440X_CONTROL1 0x1e
#define AFE440X_LEDCNTRL 0x22
#define AFE440X_CONTROL2 0x23
#define AFE440X_ALARM 0x29
#define AFE440X_LED2VAL 0x2a
#define AFE440X_ALED2VAL 0x2b
#define AFE440X_LED1VAL 0x2c
#define AFE440X_ALED1VAL 0x2d
#define AFE440X_LED2_ALED2VAL 0x2e
#define AFE440X_LED1_ALED1VAL 0x2f
#define AFE440X_CONTROL3 0x31
#define AFE440X_PDNCYCLESTC 0x32
#define AFE440X_PDNCYCLEENDC 0x33
/* CONTROL0 register fields */
#define AFE440X_CONTROL0_REG_READ BIT(0)
#define AFE440X_CONTROL0_TM_COUNT_RST BIT(1)
#define AFE440X_CONTROL0_SW_RESET BIT(3)
/* CONTROL1 register fields */
#define AFE440X_CONTROL1_TIMEREN BIT(8)
/* TIAGAIN register fields */
#define AFE440X_TIAGAIN_ENSEPGAIN_MASK BIT(15)
#define AFE440X_TIAGAIN_ENSEPGAIN_SHIFT 15
/* CONTROL2 register fields */
#define AFE440X_CONTROL2_PDN_AFE BIT(0)
#define AFE440X_CONTROL2_PDN_RX BIT(1)
#define AFE440X_CONTROL2_DYNAMIC4 BIT(3)
#define AFE440X_CONTROL2_DYNAMIC3 BIT(4)
#define AFE440X_CONTROL2_DYNAMIC2 BIT(14)
#define AFE440X_CONTROL2_DYNAMIC1 BIT(20)
/* CONTROL3 register fields */
#define AFE440X_CONTROL3_CLKDIV GENMASK(2, 0)
/* CONTROL0 values */
#define AFE440X_CONTROL0_WRITE 0x0
#define AFE440X_CONTROL0_READ 0x1
struct afe440x_reg_info {
unsigned int reg;
unsigned int offreg;
unsigned int shift;
unsigned int mask;
};
#define AFE440X_REG_INFO(_reg, _offreg, _sm) \
{ \
.reg = _reg, \
.offreg = _offreg, \
.shift = _sm ## _SHIFT, \
.mask = _sm ## _MASK, \
}
#define AFE440X_INTENSITY_CHAN(_index, _name, _mask) \
{ \
.type = IIO_INTENSITY, \
.channel = _index, \
.address = _index, \
.scan_index = _index, \
.scan_type = { \
.sign = 's', \
.realbits = 24, \
.storagebits = 32, \
.endianness = IIO_CPU, \
}, \
.extend_name = _name, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
_mask, \
}
#define AFE440X_CURRENT_CHAN(_index, _name) \
{ \
.type = IIO_CURRENT, \
.channel = _index, \
.address = _index, \
.scan_index = _index, \
.extend_name = _name, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.output = true, \
}
enum afe440x_reg_type {
SIMPLE,
RESISTANCE,
CAPACITANCE,
};
struct afe440x_val_table {
int integer;
int fract;
};
#define AFE440X_TABLE_ATTR(_name, _table) \
static ssize_t _name ## _show(struct device *dev, \
struct device_attribute *attr, char *buf) \
{ \
ssize_t len = 0; \
int i; \
\
for (i = 0; i < ARRAY_SIZE(_table); i++) \
len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06u ", \
_table[i].integer, \
_table[i].fract); \
\
buf[len - 1] = '\n'; \
\
return len; \
} \
static DEVICE_ATTR_RO(_name)
struct afe440x_attr {
struct device_attribute dev_attr;
unsigned int reg;
unsigned int shift;
unsigned int mask;
enum afe440x_reg_type type;
const struct afe440x_val_table *val_table;
unsigned int table_size;
};
#define to_afe440x_attr(_dev_attr) \
container_of(_dev_attr, struct afe440x_attr, dev_attr)
#define AFE440X_ATTR(_name, _reg, _field, _type, _table, _size) \
struct afe440x_attr afe440x_attr_##_name = { \
.dev_attr = __ATTR(_name, (S_IRUGO | S_IWUSR), \
afe440x_show_register, \
afe440x_store_register), \
.reg = _reg, \
.shift = _field ## _SHIFT, \
.mask = _field ## _MASK, \
.type = _type, \
.val_table = _table, \
.table_size = _size, \
}
#endif /* _AFE440X_H */
drivers/iio/imu/inv_mpu6050/Kconfig
View file @ d9750a2f
......@@ -3,15 +3,31 @@
#
config INV_MPU6050_IIO
tristate "Invensense MPU6050 devices"
depends on I2C && SYSFS
depends on I2C_MUX
tristate
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
config INV_MPU6050_I2C
tristate "Invensense MPU6050 devices (I2C)"
depends on I2C
select INV_MPU6050_IIO
select I2C_MUX
select REGMAP_I2C
help
This driver supports the Invensense MPU6050 devices.
This driver can also support MPU6500 in MPU6050 compatibility mode
and also in MPU6500 mode with some limitations.
It is a gyroscope/accelerometer combo device.
This driver can be built as a module. The module will be called
inv-mpu6050.
inv-mpu6050-i2c.
config INV_MPU6050_SPI
tristate "Invensense MPU6050 devices (SPI)"
depends on SPI_MASTER
select INV_MPU6050_IIO
select REGMAP_SPI
help
This driver supports the Invensense MPU6050 devices.
It is a gyroscope/accelerometer combo device.
This driver can be built as a module. The module will be called
inv-mpu6050-spi.
drivers/iio/imu/inv_mpu6050/Makefile
View file @ d9750a2f
......@@ -3,4 +3,10 @@
#
obj-$(CONFIG_INV_MPU6050_IIO) += inv-mpu6050.o
inv-mpu6050-objs := inv_mpu_core.o inv_mpu_ring.o inv_mpu_trigger.o inv_mpu_acpi.o
inv-mpu6050-objs := inv_mpu_core.o inv_mpu_ring.o inv_mpu_trigger.o
obj-$(CONFIG_INV_MPU6050_I2C) += inv-mpu6050-i2c.o
inv-mpu6050-i2c-objs := inv_mpu_i2c.o inv_mpu_acpi.o
obj-$(CONFIG_INV_MPU6050_SPI) += inv-mpu6050-spi.o
inv-mpu6050-spi-objs := inv_mpu_spi.o
drivers/iio/imu/inv_mpu6050/inv_mpu_acpi.c
View file @ d9750a2f
......@@ -139,22 +139,23 @@ static int inv_mpu_process_acpi_config(struct i2c_client *client,
return 0;
}
int inv_mpu_acpi_create_mux_client(struct inv_mpu6050_state *st)
int inv_mpu_acpi_create_mux_client(struct i2c_client *client)
{
struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(&client->dev));
st->mux_client = NULL;
if (ACPI_HANDLE(&st->client->dev)) {
if (ACPI_HANDLE(&client->dev)) {
struct i2c_board_info info;
struct acpi_device *adev;
int ret = -1;
adev = ACPI_COMPANION(&st->client->dev);
adev = ACPI_COMPANION(&client->dev);
memset(&info, 0, sizeof(info));
dmi_check_system(inv_mpu_dev_list);
switch (matched_product_name) {
case INV_MPU_ASUS_T100TA:
ret = asus_acpi_get_sensor_info(adev, st->client,
ret = asus_acpi_get_sensor_info(adev, client,
&info);
break;
/* Add more matched product processing here */
......@@ -166,7 +167,7 @@ int inv_mpu_acpi_create_mux_client(struct inv_mpu6050_state *st)
/* No matching DMI, so create device on INV6XX type */
unsigned short primary, secondary;
ret = inv_mpu_process_acpi_config(st->client, &primary,
ret = inv_mpu_process_acpi_config(client, &primary,
&secondary);
if (!ret && secondary) {
char *name;
......@@ -191,8 +192,9 @@ int inv_mpu_acpi_create_mux_client(struct inv_mpu6050_state *st)
return 0;
}
void inv_mpu_acpi_delete_mux_client(struct inv_mpu6050_state *st)
void inv_mpu_acpi_delete_mux_client(struct i2c_client *client)
{
struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(&client->dev));
if (st->mux_client)
i2c_unregister_device(st->mux_client);
}
......@@ -200,12 +202,12 @@ void inv_mpu_acpi_delete_mux_client(struct inv_mpu6050_state *st)
#include "inv_mpu_iio.h"
int inv_mpu_acpi_create_mux_client(struct inv_mpu6050_state *st)
int inv_mpu_acpi_create_mux_client(struct i2c_client *client)
{
return 0;
}
void inv_mpu_acpi_delete_mux_client(struct inv_mpu6050_state *st)
void inv_mpu_acpi_delete_mux_client(struct i2c_client *client)
{
}
#endif
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
View file @ d9750a2f
......@@ -75,100 +75,17 @@ static const struct inv_mpu6050_hw hw_info[INV_NUM_PARTS] = {
},
};
int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 d)
{
return i2c_smbus_write_i2c_block_data(st->client, reg, 1, &d);
}
/*
* The i2c read/write needs to happen in unlocked mode. As the parent
* adapter is common. If we use locked versions, it will fail as
* the mux adapter will lock the parent i2c adapter, while calling
* select/deselect functions.
*/
static int inv_mpu6050_write_reg_unlocked(struct inv_mpu6050_state *st,
u8 reg, u8 d)
{
int ret;
u8 buf[2];
struct i2c_msg msg[1] = {
{
.addr = st->client->addr,
.flags = 0,
.len = sizeof(buf),
.buf = buf,
}
};
buf[0] = reg;
buf[1] = d;
ret = __i2c_transfer(st->client->adapter, msg, 1);
if (ret != 1)
return ret;
return 0;
}
static int inv_mpu6050_select_bypass(struct i2c_adapter *adap, void *mux_priv,
u32 chan_id)
{
struct iio_dev *indio_dev = mux_priv;
struct inv_mpu6050_state *st = iio_priv(indio_dev);
int ret = 0;
/* Use the same mutex which was used everywhere to protect power-op */
mutex_lock(&indio_dev->mlock);
if (!st->powerup_count) {
ret = inv_mpu6050_write_reg_unlocked(st, st->reg->pwr_mgmt_1,
0);
if (ret)
goto write_error;
msleep(INV_MPU6050_REG_UP_TIME);
}
if (!ret) {
st->powerup_count++;
ret = inv_mpu6050_write_reg_unlocked(st, st->reg->int_pin_cfg,
st->client->irq |
INV_MPU6050_BIT_BYPASS_EN);
}
write_error:
mutex_unlock(&indio_dev->mlock);
return ret;
}
static int inv_mpu6050_deselect_bypass(struct i2c_adapter *adap,
void *mux_priv, u32 chan_id)
{
struct iio_dev *indio_dev = mux_priv;
struct inv_mpu6050_state *st = iio_priv(indio_dev);
mutex_lock(&indio_dev->mlock);
/* It doesn't really mattter, if any of the calls fails */
inv_mpu6050_write_reg_unlocked(st, st->reg->int_pin_cfg,
st->client->irq);
st->powerup_count--;
if (!st->powerup_count)
inv_mpu6050_write_reg_unlocked(st, st->reg->pwr_mgmt_1,
INV_MPU6050_BIT_SLEEP);
mutex_unlock(&indio_dev->mlock);
return 0;
}
int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask)
{
u8 d, mgmt_1;
unsigned int d, mgmt_1;
int result;
/* switch clock needs to be careful. Only when gyro is on, can
clock source be switched to gyro. Otherwise, it must be set to
internal clock */
if (INV_MPU6050_BIT_PWR_GYRO_STBY == mask) {
result = i2c_smbus_read_i2c_block_data(st->client,
st->reg->pwr_mgmt_1, 1, &mgmt_1);
if (result != 1)
result = regmap_read(st->map, st->reg->pwr_mgmt_1, &mgmt_1);
if (result)
return result;
mgmt_1 &= ~INV_MPU6050_BIT_CLK_MASK;
......@@ -178,20 +95,19 @@ int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask)
/* turning off gyro requires switch to internal clock first.
Then turn off gyro engine */
mgmt_1 |= INV_CLK_INTERNAL;
result = inv_mpu6050_write_reg(st, st->reg->pwr_mgmt_1, mgmt_1);
result = regmap_write(st->map, st->reg->pwr_mgmt_1, mgmt_1);
if (result)
return result;
}
result = i2c_smbus_read_i2c_block_data(st->client,
st->reg->pwr_mgmt_2, 1, &d);
if (result != 1)
result = regmap_read(st->map, st->reg->pwr_mgmt_2, &d);
if (result)
return result;
if (en)
d &= ~mask;
else
d |= mask;
result = inv_mpu6050_write_reg(st, st->reg->pwr_mgmt_2, d);
result = regmap_write(st->map, st->reg->pwr_mgmt_2, d);
if (result)
return result;
......@@ -201,7 +117,7 @@ int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask)
if (INV_MPU6050_BIT_PWR_GYRO_STBY == mask) {
/* switch internal clock to PLL */
mgmt_1 |= INV_CLK_PLL;
result = inv_mpu6050_write_reg(st,
result = regmap_write(st->map,
st->reg->pwr_mgmt_1, mgmt_1);
if (result)
return result;
......@@ -218,14 +134,13 @@ int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on)
if (power_on) {
/* Already under indio-dev->mlock mutex */
if (!st->powerup_count)
result = inv_mpu6050_write_reg(st, st->reg->pwr_mgmt_1,
0);
result = regmap_write(st->map, st->reg->pwr_mgmt_1, 0);
if (!result)
st->powerup_count++;
} else {
st->powerup_count--;
if (!st->powerup_count)
result = inv_mpu6050_write_reg(st, st->reg->pwr_mgmt_1,
result = regmap_write(st->map, st->reg->pwr_mgmt_1,
INV_MPU6050_BIT_SLEEP);
}
......@@ -237,6 +152,7 @@ int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on)
return 0;
}
EXPORT_SYMBOL_GPL(inv_mpu6050_set_power_itg);
/**
* inv_mpu6050_init_config() - Initialize hardware, disable FIFO.
......@@ -257,22 +173,22 @@ static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
if (result)
return result;
d = (INV_MPU6050_FSR_2000DPS << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
result = inv_mpu6050_write_reg(st, st->reg->gyro_config, d);
result = regmap_write(st->map, st->reg->gyro_config, d);
if (result)
return result;
d = INV_MPU6050_FILTER_20HZ;
result = inv_mpu6050_write_reg(st, st->reg->lpf, d);
result = regmap_write(st->map, st->reg->lpf, d);
if (result)
return result;
d = INV_MPU6050_ONE_K_HZ / INV_MPU6050_INIT_FIFO_RATE - 1;
result = inv_mpu6050_write_reg(st, st->reg->sample_rate_div, d);
result = regmap_write(st->map, st->reg->sample_rate_div, d);
if (result)
return result;
d = (INV_MPU6050_FS_02G << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
result = inv_mpu6050_write_reg(st, st->reg->accl_config, d);
result = regmap_write(st->map, st->reg->accl_config, d);
if (result)
return result;
......@@ -290,9 +206,8 @@ static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
__be16 d;
ind = (axis - IIO_MOD_X) * 2;
result = i2c_smbus_read_i2c_block_data(st->client, reg + ind, 2,
(u8 *)&d);
if (result != 2)
result = regmap_bulk_read(st->map, reg + ind, (u8 *)&d, 2);
if (result)
return -EINVAL;
*val = (short)be16_to_cpup(&d);
......@@ -418,8 +333,7 @@ static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val)
for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
if (gyro_scale_6050[i] == val) {
d = (i << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
result = inv_mpu6050_write_reg(st,
st->reg->gyro_config, d);
result = regmap_write(st->map, st->reg->gyro_config, d);
if (result)
return result;
......@@ -456,8 +370,7 @@ static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val)
for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
if (accel_scale[i] == val) {
d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
result = inv_mpu6050_write_reg(st,
st->reg->accl_config, d);
result = regmap_write(st->map, st->reg->accl_config, d);
if (result)
return result;
......@@ -537,7 +450,7 @@ static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))
i++;
data = d[i];
result = inv_mpu6050_write_reg(st, st->reg->lpf, data);
result = regmap_write(st->map, st->reg->lpf, data);
if (result)
return result;
st->chip_config.lpf = data;
......@@ -575,7 +488,7 @@ static ssize_t inv_mpu6050_fifo_rate_store(struct device *dev,
goto fifo_rate_fail;
d = INV_MPU6050_ONE_K_HZ / fifo_rate - 1;
result = inv_mpu6050_write_reg(st, st->reg->sample_rate_div, d);
result = regmap_write(st->map, st->reg->sample_rate_div, d);
if (result)
goto fifo_rate_fail;
st->chip_config.fifo_rate = fifo_rate;
......@@ -736,7 +649,7 @@ static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
st->reg = hw_info[st->chip_type].reg;
/* reset to make sure previous state are not there */
result = inv_mpu6050_write_reg(st, st->reg->pwr_mgmt_1,
result = regmap_write(st->map, st->reg->pwr_mgmt_1,
INV_MPU6050_BIT_H_RESET);
if (result)
return result;
......@@ -764,33 +677,24 @@ static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
return 0;
}
/**
* inv_mpu_probe() - probe function.
* @client: i2c client.
* @id: i2c device id.
*
* Returns 0 on success, a negative error code otherwise.
*/
static int inv_mpu_probe(struct i2c_client *client,
const struct i2c_device_id *id)
int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
int (*inv_mpu_bus_setup)(struct iio_dev *))
{
struct inv_mpu6050_state *st;
struct iio_dev *indio_dev;
struct inv_mpu6050_platform_data *pdata;
struct device *dev = regmap_get_device(regmap);
int result;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_I2C_BLOCK))
return -ENOSYS;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->client = client;
st->powerup_count = 0;
pdata = dev_get_platdata(&client->dev);
st->irq = irq;
st->map = regmap;
pdata = dev_get_platdata(dev);
if (pdata)
st->plat_data = *pdata;
/* power is turned on inside check chip type*/
......@@ -798,20 +702,22 @@ static int inv_mpu_probe(struct i2c_client *client,
if (result)
return result;
if (inv_mpu_bus_setup)
inv_mpu_bus_setup(indio_dev);
result = inv_mpu6050_init_config(indio_dev);
if (result) {
dev_err(&client->dev,
"Could not initialize device.\n");
dev_err(dev, "Could not initialize device.\n");
return result;
}
i2c_set_clientdata(client, indio_dev);
indio_dev->dev.parent = &client->dev;
/* id will be NULL when enumerated via ACPI */
if (id)
indio_dev->name = (char *)id->name;
dev_set_drvdata(dev, indio_dev);
indio_dev->dev.parent = dev;
/* name will be NULL when enumerated via ACPI */
if (name)
indio_dev->name = name;
else
indio_dev->name = (char *)dev_name(&client->dev);
indio_dev->name = dev_name(dev);
indio_dev->channels = inv_mpu_channels;
indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
......@@ -823,13 +729,12 @@ static int inv_mpu_probe(struct i2c_client *client,
inv_mpu6050_read_fifo,
NULL);
if (result) {
dev_err(&st->client->dev, "configure buffer fail %d\n",
result);
dev_err(dev, "configure buffer fail %d\n", result);
return result;
}
result = inv_mpu6050_probe_trigger(indio_dev);
if (result) {
dev_err(&st->client->dev, "trigger probe fail %d\n", result);
dev_err(dev, "trigger probe fail %d\n", result);
goto out_unreg_ring;
}
......@@ -837,102 +742,47 @@ static int inv_mpu_probe(struct i2c_client *client,
spin_lock_init(&st->time_stamp_lock);
result = iio_device_register(indio_dev);
if (result) {
dev_err(&st->client->dev, "IIO register fail %d\n", result);
dev_err(dev, "IIO register fail %d\n", result);
goto out_remove_trigger;
}
st->mux_adapter = i2c_add_mux_adapter(client->adapter,
&client->dev,
indio_dev,
0, 0, 0,
inv_mpu6050_select_bypass,
inv_mpu6050_deselect_bypass);
if (!st->mux_adapter) {
result = -ENODEV;
goto out_unreg_device;
}
result = inv_mpu_acpi_create_mux_client(st);
if (result)
goto out_del_mux;
return 0;
out_del_mux:
i2c_del_mux_adapter(st->mux_adapter);
out_unreg_device:
iio_device_unregister(indio_dev);
out_remove_trigger:
inv_mpu6050_remove_trigger(st);
out_unreg_ring:
iio_triggered_buffer_cleanup(indio_dev);
return result;
}
EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
static int inv_mpu_remove(struct i2c_client *client)
int inv_mpu_core_remove(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct inv_mpu6050_state *st = iio_priv(indio_dev);
struct iio_dev *indio_dev = dev_get_drvdata(dev);
inv_mpu_acpi_delete_mux_client(st);
i2c_del_mux_adapter(st->mux_adapter);
iio_device_unregister(indio_dev);
inv_mpu6050_remove_trigger(st);
inv_mpu6050_remove_trigger(iio_priv(indio_dev));
iio_triggered_buffer_cleanup(indio_dev);
return 0;
}
EXPORT_SYMBOL_GPL(inv_mpu_core_remove);
#ifdef CONFIG_PM_SLEEP
static int inv_mpu_resume(struct device *dev)
{
return inv_mpu6050_set_power_itg(
iio_priv(i2c_get_clientdata(to_i2c_client(dev))), true);
return inv_mpu6050_set_power_itg(iio_priv(dev_get_drvdata(dev)), true);
}
static int inv_mpu_suspend(struct device *dev)
{
return inv_mpu6050_set_power_itg(
iio_priv(i2c_get_clientdata(to_i2c_client(dev))), false);
return inv_mpu6050_set_power_itg(iio_priv(dev_get_drvdata(dev)), false);
}
static SIMPLE_DEV_PM_OPS(inv_mpu_pmops, inv_mpu_suspend, inv_mpu_resume);
#define INV_MPU6050_PMOPS (&inv_mpu_pmops)
#else
#define INV_MPU6050_PMOPS NULL
#endif /* CONFIG_PM_SLEEP */
/*
* device id table is used to identify what device can be
* supported by this driver
*/
static const struct i2c_device_id inv_mpu_id[] = {
{"mpu6050", INV_MPU6050},
{"mpu6500", INV_MPU6500},
{}
};
MODULE_DEVICE_TABLE(i2c, inv_mpu_id);
static const struct acpi_device_id inv_acpi_match[] = {
{"INVN6500", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, inv_acpi_match);
static struct i2c_driver inv_mpu_driver = {
.probe = inv_mpu_probe,
.remove = inv_mpu_remove,
.id_table = inv_mpu_id,
.driver = {
.name = "inv-mpu6050",
.pm = INV_MPU6050_PMOPS,
.acpi_match_table = ACPI_PTR(inv_acpi_match),
},
};
module_i2c_driver(inv_mpu_driver);
SIMPLE_DEV_PM_OPS(inv_mpu_pmops, inv_mpu_suspend, inv_mpu_resume);
EXPORT_SYMBOL_GPL(inv_mpu_pmops);
MODULE_AUTHOR("Invensense Corporation");
MODULE_DESCRIPTION("Invensense device MPU6050 driver");
......
drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c 0 → 100644
View file @ d9750a2f
/*
* Copyright (C) 2012 Invensense, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/i2c-mux.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include "inv_mpu_iio.h"
static const struct regmap_config inv_mpu_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
/*
* The i2c read/write needs to happen in unlocked mode. As the parent
* adapter is common. If we use locked versions, it will fail as
* the mux adapter will lock the parent i2c adapter, while calling
* select/deselect functions.
*/
static int inv_mpu6050_write_reg_unlocked(struct i2c_client *client,
u8 reg, u8 d)
{
int ret;
u8 buf[2] = {reg, d};
struct i2c_msg msg[1] = {
{
.addr = client->addr,
.flags = 0,
.len = sizeof(buf),
.buf = buf,
}
};
ret = __i2c_transfer(client->adapter, msg, 1);
if (ret != 1)
return ret;
return 0;
}
static int inv_mpu6050_select_bypass(struct i2c_adapter *adap, void *mux_priv,
u32 chan_id)
{
struct i2c_client *client = mux_priv;
struct iio_dev *indio_dev = dev_get_drvdata(&client->dev);
struct inv_mpu6050_state *st = iio_priv(indio_dev);
int ret = 0;
/* Use the same mutex which was used everywhere to protect power-op */
mutex_lock(&indio_dev->mlock);
if (!st->powerup_count) {
ret = inv_mpu6050_write_reg_unlocked(client,
st->reg->pwr_mgmt_1, 0);
if (ret)
goto write_error;
msleep(INV_MPU6050_REG_UP_TIME);
}
if (!ret) {
st->powerup_count++;
ret = inv_mpu6050_write_reg_unlocked(client,
st->reg->int_pin_cfg,
INV_MPU6050_INT_PIN_CFG |
INV_MPU6050_BIT_BYPASS_EN);
}
write_error:
mutex_unlock(&indio_dev->mlock);
return ret;
}
static int inv_mpu6050_deselect_bypass(struct i2c_adapter *adap,
void *mux_priv, u32 chan_id)
{
struct i2c_client *client = mux_priv;
struct iio_dev *indio_dev = dev_get_drvdata(&client->dev);
struct inv_mpu6050_state *st = iio_priv(indio_dev);
mutex_lock(&indio_dev->mlock);
/* It doesn't really mattter, if any of the calls fails */
inv_mpu6050_write_reg_unlocked(client, st->reg->int_pin_cfg,
INV_MPU6050_INT_PIN_CFG);
st->powerup_count--;
if (!st->powerup_count)
inv_mpu6050_write_reg_unlocked(client, st->reg->pwr_mgmt_1,
INV_MPU6050_BIT_SLEEP);
mutex_unlock(&indio_dev->mlock);
return 0;
}
/**
* inv_mpu_probe() - probe function.
* @client: i2c client.
* @id: i2c device id.
*
* Returns 0 on success, a negative error code otherwise.
*/
static int inv_mpu_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct inv_mpu6050_state *st;
int result;
const char *name = id ? id->name : NULL;
struct regmap *regmap;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_I2C_BLOCK))
return -ENOSYS;
regmap = devm_regmap_init_i2c(client, &inv_mpu_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "Failed to register i2c regmap %d\n",
(int)PTR_ERR(regmap));
return PTR_ERR(regmap);
}
result = inv_mpu_core_probe(regmap, client->irq, name, NULL);
if (result < 0)
return result;
st = iio_priv(dev_get_drvdata(&client->dev));
st->mux_adapter = i2c_add_mux_adapter(client->adapter,
&client->dev,
client,
0, 0, 0,
inv_mpu6050_select_bypass,
inv_mpu6050_deselect_bypass);
if (!st->mux_adapter) {
result = -ENODEV;
goto out_unreg_device;
}
result = inv_mpu_acpi_create_mux_client(client);
if (result)
goto out_del_mux;
return 0;
out_del_mux:
i2c_del_mux_adapter(st->mux_adapter);
out_unreg_device:
inv_mpu_core_remove(&client->dev);
return result;
}
static int inv_mpu_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct inv_mpu6050_state *st = iio_priv(indio_dev);
inv_mpu_acpi_delete_mux_client(client);
i2c_del_mux_adapter(st->mux_adapter);
return inv_mpu_core_remove(&client->dev);
}
/*
* device id table is used to identify what device can be
* supported by this driver
*/
static const struct i2c_device_id inv_mpu_id[] = {
{"mpu6050", INV_MPU6050},
{"mpu6500", INV_MPU6500},
{}
};
MODULE_DEVICE_TABLE(i2c, inv_mpu_id);
static const struct acpi_device_id inv_acpi_match[] = {
{"INVN6500", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, inv_acpi_match);
static struct i2c_driver inv_mpu_driver = {
.probe = inv_mpu_probe,
.remove = inv_mpu_remove,
.id_table = inv_mpu_id,
.driver = {
.acpi_match_table = ACPI_PTR(inv_acpi_match),
.name = "inv-mpu6050-i2c",
.pm = &inv_mpu_pmops,
},
};
module_i2c_driver(inv_mpu_driver);
MODULE_AUTHOR("Invensense Corporation");
MODULE_DESCRIPTION("Invensense device MPU6050 driver");
MODULE_LICENSE("GPL");
drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
View file @ d9750a2f
......@@ -15,6 +15,7 @@
#include <linux/spinlock.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/regmap.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/kfifo_buf.h>
#include <linux/iio/trigger.h>
......@@ -61,6 +62,7 @@ struct inv_mpu6050_reg_map {
enum inv_devices {
INV_MPU6050,
INV_MPU6500,
INV_MPU6000,
INV_NUM_PARTS
};
......@@ -107,9 +109,10 @@ struct inv_mpu6050_hw {
* @hw: Other hardware-specific information.
* @chip_type: chip type.
* @time_stamp_lock: spin lock to time stamp.
* @client: i2c client handle.
* @plat_data: platform data.
* @timestamps: kfifo queue to store time stamp.
* @map regmap pointer.
* @irq interrupt number.
*/
struct inv_mpu6050_state {
#define TIMESTAMP_FIFO_SIZE 16
......@@ -119,12 +122,13 @@ struct inv_mpu6050_state {
const struct inv_mpu6050_hw *hw;
enum inv_devices chip_type;
spinlock_t time_stamp_lock;
struct i2c_client *client;
struct i2c_adapter *mux_adapter;
struct i2c_client *mux_client;
unsigned int powerup_count;
struct inv_mpu6050_platform_data plat_data;
DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE);
struct regmap *map;
int irq;
};
/*register and associated bit definition*/
......@@ -151,6 +155,7 @@ struct inv_mpu6050_state {
#define INV_MPU6050_BIT_I2C_MST_EN 0x20
#define INV_MPU6050_BIT_FIFO_EN 0x40
#define INV_MPU6050_BIT_DMP_EN 0x80
#define INV_MPU6050_BIT_I2C_IF_DIS 0x10
#define INV_MPU6050_REG_PWR_MGMT_1 0x6B
#define INV_MPU6050_BIT_H_RESET 0x80
......@@ -185,6 +190,7 @@ struct inv_mpu6050_state {
#define INV_MPU6050_REG_INT_PIN_CFG 0x37
#define INV_MPU6050_BIT_BYPASS_EN 0x2
#define INV_MPU6050_INT_PIN_CFG 0
/* init parameters */
#define INV_MPU6050_INIT_FIFO_RATE 50
......@@ -252,5 +258,10 @@ int inv_reset_fifo(struct iio_dev *indio_dev);
int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
int inv_mpu_acpi_create_mux_client(struct inv_mpu6050_state *st);
void inv_mpu_acpi_delete_mux_client(struct inv_mpu6050_state *st);
int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
int (*inv_mpu_bus_setup)(struct iio_dev *));
int inv_mpu_core_remove(struct device *dev);
int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
extern const struct dev_pm_ops inv_mpu_pmops;
drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c
View file @ d9750a2f
......@@ -13,7 +13,6 @@
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/sysfs.h>
......@@ -41,22 +40,23 @@ int inv_reset_fifo(struct iio_dev *indio_dev)
struct inv_mpu6050_state *st = iio_priv(indio_dev);
/* disable interrupt */
result = inv_mpu6050_write_reg(st, st->reg->int_enable, 0);
result = regmap_write(st->map, st->reg->int_enable, 0);
if (result) {
dev_err(&st->client->dev, "int_enable failed %d\n", result);
dev_err(regmap_get_device(st->map), "int_enable failed %d\n",
result);
return result;
}
/* disable the sensor output to FIFO */
result = inv_mpu6050_write_reg(st, st->reg->fifo_en, 0);
result = regmap_write(st->map, st->reg->fifo_en, 0);
if (result)
goto reset_fifo_fail;
/* disable fifo reading */
result = inv_mpu6050_write_reg(st, st->reg->user_ctrl, 0);
result = regmap_write(st->map, st->reg->user_ctrl, 0);
if (result)
goto reset_fifo_fail;
/* reset FIFO*/
result = inv_mpu6050_write_reg(st, st->reg->user_ctrl,
result = regmap_write(st->map, st->reg->user_ctrl,
INV_MPU6050_BIT_FIFO_RST);
if (result)
goto reset_fifo_fail;
......@@ -67,13 +67,13 @@ int inv_reset_fifo(struct iio_dev *indio_dev)
/* enable interrupt */
if (st->chip_config.accl_fifo_enable ||
st->chip_config.gyro_fifo_enable) {
result = inv_mpu6050_write_reg(st, st->reg->int_enable,
result = regmap_write(st->map, st->reg->int_enable,
INV_MPU6050_BIT_DATA_RDY_EN);
if (result)
return result;
}
/* enable FIFO reading and I2C master interface*/
result = inv_mpu6050_write_reg(st, st->reg->user_ctrl,
result = regmap_write(st->map, st->reg->user_ctrl,
INV_MPU6050_BIT_FIFO_EN);
if (result)
goto reset_fifo_fail;
......@@ -83,15 +83,15 @@ int inv_reset_fifo(struct iio_dev *indio_dev)
d |= INV_MPU6050_BITS_GYRO_OUT;
if (st->chip_config.accl_fifo_enable)
d |= INV_MPU6050_BIT_ACCEL_OUT;
result = inv_mpu6050_write_reg(st, st->reg->fifo_en, d);
result = regmap_write(st->map, st->reg->fifo_en, d);
if (result)
goto reset_fifo_fail;
return 0;
reset_fifo_fail:
dev_err(&st->client->dev, "reset fifo failed %d\n", result);
result = inv_mpu6050_write_reg(st, st->reg->int_enable,
dev_err(regmap_get_device(st->map), "reset fifo failed %d\n", result);
result = regmap_write(st->map, st->reg->int_enable,
INV_MPU6050_BIT_DATA_RDY_EN);
return result;
......@@ -143,10 +143,10 @@ irqreturn_t inv_mpu6050_read_fifo(int irq, void *p)
* read fifo_count register to know how many bytes inside FIFO
* right now
*/
result = i2c_smbus_read_i2c_block_data(st->client,
result = regmap_bulk_read(st->map,
st->reg->fifo_count_h,
INV_MPU6050_FIFO_COUNT_BYTE, data);
if (result != INV_MPU6050_FIFO_COUNT_BYTE)
data, INV_MPU6050_FIFO_COUNT_BYTE);
if (result)
goto end_session;
fifo_count = be16_to_cpup((__be16 *)(&data[0]));
if (fifo_count < bytes_per_datum)
......@@ -161,10 +161,9 @@ irqreturn_t inv_mpu6050_read_fifo(int irq, void *p)
fifo_count / bytes_per_datum + INV_MPU6050_TIME_STAMP_TOR)
goto flush_fifo;
while (fifo_count >= bytes_per_datum) {
result = i2c_smbus_read_i2c_block_data(st->client,
st->reg->fifo_r_w,
bytes_per_datum, data);
if (result != bytes_per_datum)
result = regmap_bulk_read(st->map, st->reg->fifo_r_w,
data, bytes_per_datum);
if (result)
goto flush_fifo;
result = kfifo_out(&st->timestamps, &timestamp, 1);
......
drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c 0 → 100644
View file @ d9750a2f
/*
* Copyright (C) 2015 Intel Corporation Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/acpi.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include "inv_mpu_iio.h"
static const struct regmap_config inv_mpu_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static int inv_mpu_i2c_disable(struct iio_dev *indio_dev)
{
struct inv_mpu6050_state *st = iio_priv(indio_dev);
int ret = 0;
ret = inv_mpu6050_set_power_itg(st, true);
if (ret)
return ret;
ret = regmap_write(st->map, INV_MPU6050_REG_USER_CTRL,
INV_MPU6050_BIT_I2C_IF_DIS);
if (ret) {
inv_mpu6050_set_power_itg(st, false);
return ret;
}
return inv_mpu6050_set_power_itg(st, false);
}
static int inv_mpu_probe(struct spi_device *spi)
{
struct regmap *regmap;
const struct spi_device_id *id = spi_get_device_id(spi);
const char *name = id ? id->name : NULL;
regmap = devm_regmap_init_spi(spi, &inv_mpu_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&spi->dev, "Failed to register spi regmap %d\n",
(int)PTR_ERR(regmap));
return PTR_ERR(regmap);
}
return inv_mpu_core_probe(regmap, spi->irq, name, inv_mpu_i2c_disable);
}
static int inv_mpu_remove(struct spi_device *spi)
{
return inv_mpu_core_remove(&spi->dev);
}
/*
* device id table is used to identify what device can be
* supported by this driver
*/
static const struct spi_device_id inv_mpu_id[] = {
{"mpu6000", INV_MPU6000},
{}
};
MODULE_DEVICE_TABLE(spi, inv_mpu_id);
static const struct acpi_device_id inv_acpi_match[] = {
{"INVN6000", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, inv_acpi_match);
static struct spi_driver inv_mpu_driver = {
.probe = inv_mpu_probe,
.remove = inv_mpu_remove,
.id_table = inv_mpu_id,
.driver = {
.acpi_match_table = ACPI_PTR(inv_acpi_match),
.name = "inv-mpu6000-spi",
.pm = &inv_mpu_pmops,
},
};
module_spi_driver(inv_mpu_driver);
MODULE_AUTHOR("Adriana Reus <adriana.reus@intel.com>");
MODULE_DESCRIPTION("Invensense device MPU6000 driver");
MODULE_LICENSE("GPL");
drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c
View file @ d9750a2f
......@@ -65,15 +65,15 @@ static int inv_mpu6050_set_enable(struct iio_dev *indio_dev, bool enable)
if (result)
return result;
} else {
result = inv_mpu6050_write_reg(st, st->reg->fifo_en, 0);
result = regmap_write(st->map, st->reg->fifo_en, 0);
if (result)
return result;
result = inv_mpu6050_write_reg(st, st->reg->int_enable, 0);
result = regmap_write(st->map, st->reg->int_enable, 0);
if (result)
return result;
result = inv_mpu6050_write_reg(st, st->reg->user_ctrl, 0);
result = regmap_write(st->map, st->reg->user_ctrl, 0);
if (result)
return result;
......@@ -123,7 +123,7 @@ int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev)
if (!st->trig)
return -ENOMEM;
ret = devm_request_irq(&indio_dev->dev, st->client->irq,
ret = devm_request_irq(&indio_dev->dev, st->irq,
&iio_trigger_generic_data_rdy_poll,
IRQF_TRIGGER_RISING,
"inv_mpu",
......@@ -131,7 +131,7 @@ int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev)
if (ret)
return ret;
st->trig->dev.parent = &st->client->dev;
st->trig->dev.parent = regmap_get_device(st->map);
st->trig->ops = &inv_mpu_trigger_ops;
iio_trigger_set_drvdata(st->trig, indio_dev);
......
drivers/iio/industrialio-buffer.c
View file @ d9750a2f
......@@ -512,33 +512,41 @@ static ssize_t iio_buffer_show_enable(struct device *dev,
return sprintf(buf, "%d\n", iio_buffer_is_active(indio_dev->buffer));
}
static unsigned int iio_storage_bytes_for_si(struct iio_dev *indio_dev,
unsigned int scan_index)
{
const struct iio_chan_spec *ch;
unsigned int bytes;
ch = iio_find_channel_from_si(indio_dev, scan_index);
bytes = ch->scan_type.storagebits / 8;
if (ch->scan_type.repeat > 1)
bytes *= ch->scan_type.repeat;
return bytes;
}
static unsigned int iio_storage_bytes_for_timestamp(struct iio_dev *indio_dev)
{
return iio_storage_bytes_for_si(indio_dev,
indio_dev->scan_index_timestamp);
}
static int iio_compute_scan_bytes(struct iio_dev *indio_dev,
const unsigned long *mask, bool timestamp)
{
const struct iio_chan_spec *ch;
unsigned bytes = 0;
int length, i;
/* How much space will the demuxed element take? */
for_each_set_bit(i, mask,
indio_dev->masklength) {
ch = iio_find_channel_from_si(indio_dev, i);
if (ch->scan_type.repeat > 1)
length = ch->scan_type.storagebits / 8 *
ch->scan_type.repeat;
else
length = ch->scan_type.storagebits / 8;
length = iio_storage_bytes_for_si(indio_dev, i);
bytes = ALIGN(bytes, length);
bytes += length;
}
if (timestamp) {
ch = iio_find_channel_from_si(indio_dev,
indio_dev->scan_index_timestamp);
if (ch->scan_type.repeat > 1)
length = ch->scan_type.storagebits / 8 *
ch->scan_type.repeat;
else
length = ch->scan_type.storagebits / 8;
length = iio_storage_bytes_for_timestamp(indio_dev);
bytes = ALIGN(bytes, length);
bytes += length;
}
......@@ -1288,7 +1296,6 @@ static int iio_buffer_add_demux(struct iio_buffer *buffer,
static int iio_buffer_update_demux(struct iio_dev *indio_dev,
struct iio_buffer *buffer)
{
const struct iio_chan_spec *ch;
int ret, in_ind = -1, out_ind, length;
unsigned in_loc = 0, out_loc = 0;
struct iio_demux_table *p = NULL;
......@@ -1315,21 +1322,11 @@ static int iio_buffer_update_demux(struct iio_dev *indio_dev,
in_ind = find_next_bit(indio_dev->active_scan_mask,
indio_dev->masklength,
in_ind + 1);
ch = iio_find_channel_from_si(indio_dev, in_ind);
if (ch->scan_type.repeat > 1)
length = ch->scan_type.storagebits / 8 *
ch->scan_type.repeat;
else
length = ch->scan_type.storagebits / 8;
length = iio_storage_bytes_for_si(indio_dev, in_ind);
/* Make sure we are aligned */
in_loc = roundup(in_loc, length) + length;
}
ch = iio_find_channel_from_si(indio_dev, in_ind);
if (ch->scan_type.repeat > 1)
length = ch->scan_type.storagebits / 8 *
ch->scan_type.repeat;
else
length = ch->scan_type.storagebits / 8;
length = iio_storage_bytes_for_si(indio_dev, in_ind);
out_loc = roundup(out_loc, length);
in_loc = roundup(in_loc, length);
ret = iio_buffer_add_demux(buffer, &p, in_loc, out_loc, length);
......@@ -1340,13 +1337,7 @@ static int iio_buffer_update_demux(struct iio_dev *indio_dev,
}
/* Relies on scan_timestamp being last */
if (buffer->scan_timestamp) {
ch = iio_find_channel_from_si(indio_dev,
indio_dev->scan_index_timestamp);
if (ch->scan_type.repeat > 1)
length = ch->scan_type.storagebits / 8 *
ch->scan_type.repeat;
else
length = ch->scan_type.storagebits / 8;
length = iio_storage_bytes_for_timestamp(indio_dev);
out_loc = roundup(out_loc, length);
in_loc = roundup(in_loc, length);
ret = iio_buffer_add_demux(buffer, &p, in_loc, out_loc, length);
......
drivers/iio/pressure/Kconfig
View file @ d9750a2f
......@@ -69,6 +69,7 @@ config MPL3115
config MS5611
tristate "Measurement Specialties MS5611 pressure sensor driver"
select IIO_TRIGGERED_BUFFER
help
Say Y here to build support for the Measurement Specialties
MS5611, MS5607 pressure and temperature sensors.
......
drivers/iio/pressure/ms5611.h
View file @ d9750a2f
......@@ -52,5 +52,6 @@ struct ms5611_state {
};
int ms5611_probe(struct iio_dev *indio_dev, struct device *dev, int type);
int ms5611_remove(struct iio_dev *indio_dev);
#endif /* _MS5611_H */
drivers/iio/pressure/ms5611_core.c
View file @ d9750a2f
......@@ -17,6 +17,9 @@
#include <linux/iio/iio.h>
#include <linux/delay.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include "ms5611.h"
static bool ms5611_prom_is_valid(u16 *prom, size_t len)
......@@ -173,6 +176,28 @@ static int ms5611_reset(struct iio_dev *indio_dev)
return 0;
}
static irqreturn_t ms5611_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct ms5611_state *st = iio_priv(indio_dev);
s32 buf[4]; /* s32 (pressure) + s32 (temp) + 2 * s32 (timestamp) */
int ret;
mutex_lock(&st->lock);
ret = ms5611_read_temp_and_pressure(indio_dev, &buf[1], &buf[0]);
mutex_unlock(&st->lock);
if (ret < 0)
goto err;
iio_push_to_buffers_with_timestamp(indio_dev, buf, iio_get_time_ns());
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int ms5611_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
......@@ -201,11 +226,25 @@ static int ms5611_read_raw(struct iio_dev *indio_dev,
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_TEMP:
*val = 10;
return IIO_VAL_INT;
case IIO_PRESSURE:
*val = 0;
*val2 = 1000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
return -EINVAL;
}
static const unsigned long ms5611_scan_masks[] = {0x3, 0};
static struct ms5611_chip_info chip_info_tbl[] = {
[MS5611] = {
.temp_and_pressure_compensate = ms5611_temp_and_pressure_compensate,
......@@ -218,12 +257,29 @@ static struct ms5611_chip_info chip_info_tbl[] = {
static const struct iio_chan_spec ms5611_channels[] = {
{
.type = IIO_PRESSURE,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 's',
.realbits = 32,
.storagebits = 32,
.endianness = IIO_CPU,
},
},
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
}
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 1,
.scan_type = {
.sign = 's',
.realbits = 32,
.storagebits = 32,
.endianness = IIO_CPU,
},
},
IIO_CHAN_SOFT_TIMESTAMP(2),
};
static const struct iio_info ms5611_info = {
......@@ -255,15 +311,43 @@ int ms5611_probe(struct iio_dev *indio_dev, struct device *dev, int type)
indio_dev->channels = ms5611_channels;
indio_dev->num_channels = ARRAY_SIZE(ms5611_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->available_scan_masks = ms5611_scan_masks;
ret = ms5611_init(indio_dev);
if (ret < 0)
return ret;
return devm_iio_device_register(dev, indio_dev);
ret = iio_triggered_buffer_setup(indio_dev, NULL,
ms5611_trigger_handler, NULL);
if (ret < 0) {
dev_err(dev, "iio triggered buffer setup failed\n");
return ret;
}
ret = iio_device_register(indio_dev);
if (ret < 0) {
dev_err(dev, "unable to register iio device\n");
goto err_buffer_cleanup;
}
return 0;
err_buffer_cleanup:
iio_triggered_buffer_cleanup(indio_dev);
return ret;
}
EXPORT_SYMBOL(ms5611_probe);
int ms5611_remove(struct iio_dev *indio_dev)
{
iio_device_unregister(indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
return 0;
}
EXPORT_SYMBOL(ms5611_remove);
MODULE_AUTHOR("Tomasz Duszynski <tduszyns@gmail.com>");
MODULE_DESCRIPTION("MS5611 core driver");
MODULE_LICENSE("GPL v2");
drivers/iio/pressure/ms5611_i2c.c
View file @ d9750a2f
......@@ -99,6 +99,7 @@ static int ms5611_i2c_probe(struct i2c_client *client,
return -ENOMEM;
st = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
st->reset = ms5611_i2c_reset;
st->read_prom_word = ms5611_i2c_read_prom_word;
st->read_adc_temp_and_pressure = ms5611_i2c_read_adc_temp_and_pressure;
......@@ -107,6 +108,11 @@ static int ms5611_i2c_probe(struct i2c_client *client,
return ms5611_probe(indio_dev, &client->dev, id->driver_data);
}
static int ms5611_i2c_remove(struct i2c_client *client)
{
return ms5611_remove(i2c_get_clientdata(client));
}
static const struct i2c_device_id ms5611_id[] = {
{ "ms5611", MS5611 },
{ "ms5607", MS5607 },
......@@ -120,6 +126,7 @@ static struct i2c_driver ms5611_driver = {
},
.id_table = ms5611_id,
.probe = ms5611_i2c_probe,
.remove = ms5611_i2c_remove,
};
module_i2c_driver(ms5611_driver);
......
drivers/iio/pressure/ms5611_spi.c
View file @ d9750a2f
......@@ -90,6 +90,8 @@ static int ms5611_spi_probe(struct spi_device *spi)
if (!indio_dev)
return -ENOMEM;
spi_set_drvdata(spi, indio_dev);
spi->mode = SPI_MODE_0;
spi->max_speed_hz = 20000000;
spi->bits_per_word = 8;
......@@ -107,6 +109,11 @@ static int ms5611_spi_probe(struct spi_device *spi)
spi_get_device_id(spi)->driver_data);
}
static int ms5611_spi_remove(struct spi_device *spi)
{
return ms5611_remove(spi_get_drvdata(spi));
}
static const struct spi_device_id ms5611_id[] = {
{ "ms5611", MS5611 },
{ "ms5607", MS5607 },
......@@ -120,6 +127,7 @@ static struct spi_driver ms5611_driver = {
},
.id_table = ms5611_id,
.probe = ms5611_spi_probe,
.remove = ms5611_spi_remove,
};
module_spi_driver(ms5611_driver);
......
drivers/staging/iio/adc/Kconfig
View file @ d9750a2f
......@@ -59,12 +59,12 @@ config AD7816
temperature sensors and ADC.
config AD7192
tristate "Analog Devices AD7190 AD7192 AD7195 ADC driver"
tristate "Analog Devices AD7190 AD7192 AD7193 AD7195 ADC driver"
depends on SPI
select AD_SIGMA_DELTA
help
Say yes here to build support for Analog Devices AD7190,
AD7192 or AD7195 SPI analog to digital converters (ADC).
AD7192, AD7193 or AD7195 SPI analog to digital converters (ADC).
If unsure, say N (but it's safe to say "Y").
To compile this driver as a module, choose M here: the
......@@ -92,20 +92,6 @@ config LPC32XX_ADC
activate only one via device tree selection. Provides direct access
via sysfs.
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
depends on INPUT
select STMP_DEVICE
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Say yes here to build support for i.MX23/i.MX28 LRADC convertor
built into these chips.
To compile this driver as a module, choose M here: the
module will be called mxs-lradc.
config SPEAR_ADC
tristate "ST SPEAr ADC"
depends on PLAT_SPEAR || COMPILE_TEST
......
drivers/staging/iio/adc/Makefile
View file @ d9750a2f
......@@ -12,5 +12,4 @@ obj-$(CONFIG_AD7816) += ad7816.o
obj-$(CONFIG_AD7192) += ad7192.o
obj-$(CONFIG_AD7280) += ad7280a.o
obj-$(CONFIG_LPC32XX_ADC) += lpc32xx_adc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_SPEAR_ADC) += spear_adc.o
drivers/staging/iio/adc/ad7192.c
View file @ d9750a2f
/*
* AD7190 AD7192 AD7195 SPI ADC driver
* AD7190 AD7192 AD7193 AD7195 SPI ADC driver
*
* Copyright 2011-2012 Analog Devices Inc.
* Copyright 2011-2015 Analog Devices Inc.
*
* Licensed under the GPL-2.
*/
......@@ -92,26 +92,43 @@
#define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
#define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
#define AD7192_CONF_CHAN(x) (((1 << (x)) & 0xFF) << 8) /* Channel select */
#define AD7192_CONF_CHAN_MASK (0xFF << 8) /* Channel select mask */
#define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
#define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
#define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
#define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
#define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
#define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
#define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
#define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */
#define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */
#define AD7192_CH_TEMP 2 /* Temp Sensor */
#define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */
#define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */
#define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */
#define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */
#define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */
#define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
#define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
#define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
#define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
#define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
#define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
#define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
#define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
#define AD7193_CH_AIN1P_AIN2M 0x000 /* AIN1(+) - AIN2(-) */
#define AD7193_CH_AIN3P_AIN4M 0x001 /* AIN3(+) - AIN4(-) */
#define AD7193_CH_AIN5P_AIN6M 0x002 /* AIN5(+) - AIN6(-) */
#define AD7193_CH_AIN7P_AIN8M 0x004 /* AIN7(+) - AIN8(-) */
#define AD7193_CH_TEMP 0x100 /* Temp senseor */
#define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
#define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
#define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
#define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
#define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
#define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
#define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
#define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
#define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
#define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
/* ID Register Bit Designations (AD7192_REG_ID) */
#define ID_AD7190 0x4
#define ID_AD7192 0x0
#define ID_AD7193 0x2
#define ID_AD7195 0x6
#define AD7192_ID_MASK 0x0F
......@@ -607,6 +624,24 @@ static const struct iio_chan_spec ad7192_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(8),
};
static const struct iio_chan_spec ad7193_channels[] = {
AD_SD_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M, 24, 32, 0),
AD_SD_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M, 24, 32, 0),
AD_SD_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M, 24, 32, 0),
AD_SD_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M, 24, 32, 0),
AD_SD_TEMP_CHANNEL(4, AD7193_CH_TEMP, 24, 32, 0),
AD_SD_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M, 24, 32, 0),
AD_SD_CHANNEL(6, 1, AD7193_CH_AIN1, 24, 32, 0),
AD_SD_CHANNEL(7, 2, AD7193_CH_AIN2, 24, 32, 0),
AD_SD_CHANNEL(8, 3, AD7193_CH_AIN3, 24, 32, 0),
AD_SD_CHANNEL(9, 4, AD7193_CH_AIN4, 24, 32, 0),
AD_SD_CHANNEL(10, 5, AD7193_CH_AIN5, 24, 32, 0),
AD_SD_CHANNEL(11, 6, AD7193_CH_AIN6, 24, 32, 0),
AD_SD_CHANNEL(12, 7, AD7193_CH_AIN7, 24, 32, 0),
AD_SD_CHANNEL(13, 8, AD7193_CH_AIN8, 24, 32, 0),
IIO_CHAN_SOFT_TIMESTAMP(14),
};
static int ad7192_probe(struct spi_device *spi)
{
const struct ad7192_platform_data *pdata = dev_get_platdata(&spi->dev);
......@@ -651,8 +686,18 @@ static int ad7192_probe(struct spi_device *spi)
indio_dev->dev.parent = &spi->dev;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
switch (st->devid) {
case ID_AD7193:
indio_dev->channels = ad7193_channels;
indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
break;
default:
indio_dev->channels = ad7192_channels;
indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
break;
}
if (st->devid == ID_AD7195)
indio_dev->info = &ad7195_info;
else
......@@ -699,6 +744,7 @@ static int ad7192_remove(struct spi_device *spi)
static const struct spi_device_id ad7192_id[] = {
{"ad7190", ID_AD7190},
{"ad7192", ID_AD7192},
{"ad7193", ID_AD7193},
{"ad7195", ID_AD7195},
{}
};
......@@ -715,5 +761,5 @@ static struct spi_driver ad7192_driver = {
module_spi_driver(ad7192_driver);
MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC");
MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
MODULE_LICENSE("GPL v2");
drivers/staging/iio/adc/ad7606.h
View file @ d9750a2f
......@@ -85,8 +85,6 @@ struct ad7606_bus_ops {
int (*read_block)(struct device *, int, void *);
};
void ad7606_suspend(struct iio_dev *indio_dev);
void ad7606_resume(struct iio_dev *indio_dev);
struct iio_dev *ad7606_probe(struct device *dev, int irq,
void __iomem *base_address, unsigned id,
const struct ad7606_bus_ops *bops);
......@@ -101,4 +99,12 @@ enum ad7606_supported_device_ids {
int ad7606_register_ring_funcs_and_init(struct iio_dev *indio_dev);
void ad7606_ring_cleanup(struct iio_dev *indio_dev);
#ifdef CONFIG_PM_SLEEP
extern const struct dev_pm_ops ad7606_pm_ops;
#define AD7606_PM_OPS (&ad7606_pm_ops)
#else
#define AD7606_PM_OPS NULL
#endif
#endif /* IIO_ADC_AD7606_H_ */
drivers/staging/iio/adc/ad7606_core.c
View file @ d9750a2f
......@@ -250,7 +250,8 @@ static const struct attribute_group ad7606_attribute_group_range = {
}, \
}
static const struct iio_chan_spec ad7606_8_channels[] = {
static const struct iio_chan_spec ad7606_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(8),
AD7606_CHANNEL(0),
AD7606_CHANNEL(1),
AD7606_CHANNEL(2),
......@@ -259,25 +260,6 @@ static const struct iio_chan_spec ad7606_8_channels[] = {
AD7606_CHANNEL(5),
AD7606_CHANNEL(6),
AD7606_CHANNEL(7),
IIO_CHAN_SOFT_TIMESTAMP(8),
};
static const struct iio_chan_spec ad7606_6_channels[] = {
AD7606_CHANNEL(0),
AD7606_CHANNEL(1),
AD7606_CHANNEL(2),
AD7606_CHANNEL(3),
AD7606_CHANNEL(4),
AD7606_CHANNEL(5),
IIO_CHAN_SOFT_TIMESTAMP(6),
};
static const struct iio_chan_spec ad7606_4_channels[] = {
AD7606_CHANNEL(0),
AD7606_CHANNEL(1),
AD7606_CHANNEL(2),
AD7606_CHANNEL(3),
IIO_CHAN_SOFT_TIMESTAMP(4),
};
static const struct ad7606_chip_info ad7606_chip_info_tbl[] = {
......@@ -287,20 +269,20 @@ static const struct ad7606_chip_info ad7606_chip_info_tbl[] = {
[ID_AD7606_8] = {
.name = "ad7606",
.int_vref_mv = 2500,
.channels = ad7606_8_channels,
.num_channels = 8,
.channels = ad7606_channels,
.num_channels = 9,
},
[ID_AD7606_6] = {
.name = "ad7606-6",
.int_vref_mv = 2500,
.channels = ad7606_6_channels,
.num_channels = 6,
.channels = ad7606_channels,
.num_channels = 7,
},
[ID_AD7606_4] = {
.name = "ad7606-4",
.int_vref_mv = 2500,
.channels = ad7606_4_channels,
.num_channels = 4,
.channels = ad7606_channels,
.num_channels = 5,
},
};
......@@ -578,8 +560,11 @@ int ad7606_remove(struct iio_dev *indio_dev, int irq)
}
EXPORT_SYMBOL_GPL(ad7606_remove);
void ad7606_suspend(struct iio_dev *indio_dev)
#ifdef CONFIG_PM_SLEEP
static int ad7606_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct ad7606_state *st = iio_priv(indio_dev);
if (gpio_is_valid(st->pdata->gpio_stby)) {
......@@ -587,11 +572,13 @@ void ad7606_suspend(struct iio_dev *indio_dev)
gpio_set_value(st->pdata->gpio_range, 1);
gpio_set_value(st->pdata->gpio_stby, 0);
}
return 0;
}
EXPORT_SYMBOL_GPL(ad7606_suspend);
void ad7606_resume(struct iio_dev *indio_dev)
static int ad7606_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct ad7606_state *st = iio_priv(indio_dev);
if (gpio_is_valid(st->pdata->gpio_stby)) {
......@@ -602,8 +589,14 @@ void ad7606_resume(struct iio_dev *indio_dev)
gpio_set_value(st->pdata->gpio_stby, 1);
ad7606_reset(st);
}
return 0;
}
EXPORT_SYMBOL_GPL(ad7606_resume);
SIMPLE_DEV_PM_OPS(ad7606_pm_ops, ad7606_suspend, ad7606_resume);
EXPORT_SYMBOL_GPL(ad7606_pm_ops);
#endif
MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
MODULE_DESCRIPTION("Analog Devices AD7606 ADC");
......
drivers/staging/iio/adc/ad7606_par.c
View file @ d9750a2f
......@@ -90,36 +90,6 @@ static int ad7606_par_remove(struct platform_device *pdev)
return 0;
}
#ifdef CONFIG_PM
static int ad7606_par_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
ad7606_suspend(indio_dev);
return 0;
}
static int ad7606_par_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
ad7606_resume(indio_dev);
return 0;
}
static const struct dev_pm_ops ad7606_pm_ops = {
.suspend = ad7606_par_suspend,
.resume = ad7606_par_resume,
};
#define AD7606_PAR_PM_OPS (&ad7606_pm_ops)
#else
#define AD7606_PAR_PM_OPS NULL
#endif /* CONFIG_PM */
static const struct platform_device_id ad7606_driver_ids[] = {
{
.name = "ad7606-8",
......@@ -142,7 +112,7 @@ static struct platform_driver ad7606_driver = {
.id_table = ad7606_driver_ids,
.driver = {
.name = "ad7606",
.pm = AD7606_PAR_PM_OPS,
.pm = AD7606_PM_OPS,
},
};
......
drivers/staging/iio/adc/ad7606_spi.c
View file @ d9750a2f
......@@ -62,36 +62,6 @@ static int ad7606_spi_remove(struct spi_device *spi)
return ad7606_remove(indio_dev, spi->irq);
}
#ifdef CONFIG_PM
static int ad7606_spi_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
ad7606_suspend(indio_dev);
return 0;
}
static int ad7606_spi_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
ad7606_resume(indio_dev);
return 0;
}
static const struct dev_pm_ops ad7606_pm_ops = {
.suspend = ad7606_spi_suspend,
.resume = ad7606_spi_resume,
};
#define AD7606_SPI_PM_OPS (&ad7606_pm_ops)
#else
#define AD7606_SPI_PM_OPS NULL
#endif
static const struct spi_device_id ad7606_id[] = {
{"ad7606-8", ID_AD7606_8},
{"ad7606-6", ID_AD7606_6},
......@@ -103,7 +73,7 @@ MODULE_DEVICE_TABLE(spi, ad7606_id);
static struct spi_driver ad7606_driver = {
.driver = {
.name = "ad7606",
.pm = AD7606_SPI_PM_OPS,
.pm = AD7606_PM_OPS,
},
.probe = ad7606_spi_probe,
.remove = ad7606_spi_remove,
......
drivers/staging/iio/adc/spear_adc.c
View file @ d9750a2f
......@@ -288,7 +288,7 @@ static int spear_adc_probe(struct platform_device *pdev)
st->adc_base_spear3xx =
(struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx;
st->clk = clk_get(dev, NULL);
st->clk = devm_clk_get(dev, NULL);
if (IS_ERR(st->clk)) {
dev_err(dev, "failed getting clock\n");
goto errout1;
......@@ -297,28 +297,28 @@ static int spear_adc_probe(struct platform_device *pdev)
ret = clk_prepare_enable(st->clk);
if (ret) {
dev_err(dev, "failed enabling clock\n");
goto errout2;
goto errout1;
}
irq = platform_get_irq(pdev, 0);
if (irq <= 0) {
dev_err(dev, "failed getting interrupt resource\n");
ret = -EINVAL;
goto errout3;
goto errout2;
}
ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME,
st);
if (ret < 0) {
dev_err(dev, "failed requesting interrupt\n");
goto errout3;
goto errout2;
}
if (of_property_read_u32(np, "sampling-frequency",
&st->sampling_freq)) {
dev_err(dev, "sampling-frequency missing in DT\n");
ret = -EINVAL;
goto errout3;
goto errout2;
}
/*
......@@ -348,16 +348,14 @@ static int spear_adc_probe(struct platform_device *pdev)
ret = iio_device_register(indio_dev);
if (ret)
goto errout3;
goto errout2;
dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq);
return 0;
errout3:
clk_disable_unprepare(st->clk);
errout2:
clk_put(st->clk);
clk_disable_unprepare(st->clk);
errout1:
iounmap(st->adc_base_spear6xx);
return ret;
......@@ -370,7 +368,6 @@ static int spear_adc_remove(struct platform_device *pdev)
iio_device_unregister(indio_dev);
clk_disable_unprepare(st->clk);
clk_put(st->clk);
iounmap(st->adc_base_spear6xx);
return 0;
......
drivers/staging/iio/impedance-analyzer/ad5933.c
View file @ d9750a2f
......@@ -558,7 +558,7 @@ static int ad5933_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info ad5933_info = {
.read_raw = &ad5933_read_raw,
.read_raw = ad5933_read_raw,
.attrs = &ad5933_attribute_group,
.driver_module = THIS_MODULE,
};
......@@ -616,9 +616,9 @@ static int ad5933_ring_postdisable(struct iio_dev *indio_dev)
}
static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = {
.preenable = &ad5933_ring_preenable,
.postenable = &ad5933_ring_postenable,
.postdisable = &ad5933_ring_postdisable,
.preenable = ad5933_ring_preenable,
.postenable = ad5933_ring_postenable,
.postdisable = ad5933_ring_postdisable,
};
static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
......
drivers/staging/iio/magnetometer/hmc5843.h
View file @ d9750a2f
......@@ -7,8 +7,7 @@
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* */
*/
#ifndef HMC5843_CORE_H
#define HMC5843_CORE_H
......@@ -38,7 +37,7 @@ enum hmc5843_ids {
* @regmap: hardware access register maps
* @variant: describe chip variants
* @buffer: 3x 16-bit channels + padding + 64-bit timestamp
**/
*/
struct hmc5843_data {
struct device *dev;
struct mutex lock;
......
drivers/staging/iio/magnetometer/hmc5843_core.c
View file @ d9750a2f
......@@ -565,14 +565,14 @@ static const unsigned long hmc5843_scan_masks[] = {0x7, 0};
int hmc5843_common_suspend(struct device *dev)
{
return hmc5843_set_mode(iio_priv(dev_get_drvdata(dev)),
HMC5843_MODE_CONVERSION_CONTINUOUS);
HMC5843_MODE_SLEEP);
}
EXPORT_SYMBOL(hmc5843_common_suspend);
int hmc5843_common_resume(struct device *dev)
{
return hmc5843_set_mode(iio_priv(dev_get_drvdata(dev)),
HMC5843_MODE_SLEEP);
HMC5843_MODE_CONVERSION_CONTINUOUS);
}
EXPORT_SYMBOL(hmc5843_common_resume);
......
drivers/staging/iio/magnetometer/hmc5843_i2c.c
View file @ d9750a2f
......@@ -7,8 +7,7 @@
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* */
*/
#include <linux/module.h>
#include <linux/i2c.h>
......
drivers/staging/iio/magnetometer/hmc5843_spi.c
View file @ d9750a2f
......@@ -6,8 +6,7 @@
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* */
*/
#include <linux/module.h>
#include <linux/spi/spi.h>
......
include/linux/iio/iio.h
View file @ d9750a2f
......@@ -448,7 +448,7 @@ struct iio_buffer_setup_ops {
* @buffer: [DRIVER] any buffer present
* @buffer_list: [INTERN] list of all buffers currently attached
* @scan_bytes: [INTERN] num bytes captured to be fed to buffer demux
* @mlock: [INTERN] lock used to prevent simultaneous device state
* @mlock: [DRIVER] lock used to prevent simultaneous device state
* changes
* @available_scan_masks: [DRIVER] optional array of allowed bitmasks
* @masklength: [INTERN] the length of the mask established from
......
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