drm/amd/display: add line number to reg_wait timeout print

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dc_helper.c

@@ -129,7 +129,7 @@ uint32_t generic_reg_get(const struct dc_context *ctx,
 uint32_t generic_reg_wait(const struct dc_context *ctx,
 	uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
 	unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
-	const char *func_name)
+	const char *func_name, int line)
 {
 	uint32_t field_value;
 	uint32_t reg_val;
@@ -158,8 +158,8 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
 			return reg_val;
 	}
 
-	dm_error("REG_WAIT timeout %dus * %d tries - %s\n",
-			delay_between_poll_us, time_out_num_tries, func_name);
+	dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
+			delay_between_poll_us, time_out_num_tries, func_name, line);
 
 	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 		BREAK_TO_DEBUGGER();

drivers/gpu/drm/amd/display/dc/dm_services.h

@@ -194,7 +194,7 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
 unsigned int generic_reg_wait(const struct dc_context *ctx,
 	uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
 	unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
-	const char *func_name);
+	const char *func_name, int line);
 
 
 /* These macros need to be used with soc15 registers in order to retrieve

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

@@ -188,7 +188,7 @@
 #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try)	\
 		generic_reg_wait(CTX, \
 				REG(reg_name), FN(reg_name, field), val,\
-				delay_between_poll_us, max_try, __func__)
+				delay_between_poll_us, max_try, __func__, __LINE__)
 
 /* macro to update (read, modify, write) register fields
  */