Commit db2c1f9e authored by Andrew Jackson's avatar Andrew Jackson Committed by Mark Brown

ASoC: dwc: Iterate over all channels

The Designware core can be configured with up to four stereo channels.
Each stereo channel is individually configured so, when the driver's
hw_params call is made, each requested stereo channel has to be
programmed.
Signed-off-by: default avatarAndrew Jackson <Andrew.Jackson@arm.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 3475c3d0
...@@ -209,16 +209,9 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, ...@@ -209,16 +209,9 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
switch (config->chan_nr) { switch (config->chan_nr) {
case EIGHT_CHANNEL_SUPPORT: case EIGHT_CHANNEL_SUPPORT:
ch_reg = 3;
break;
case SIX_CHANNEL_SUPPORT: case SIX_CHANNEL_SUPPORT:
ch_reg = 2;
break;
case FOUR_CHANNEL_SUPPORT: case FOUR_CHANNEL_SUPPORT:
ch_reg = 1;
break;
case TWO_CHANNEL_SUPPORT: case TWO_CHANNEL_SUPPORT:
ch_reg = 0;
break; break;
default: default:
dev_err(dev->dev, "channel not supported\n"); dev_err(dev->dev, "channel not supported\n");
...@@ -227,19 +220,23 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, ...@@ -227,19 +220,23 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
i2s_disable_channels(dev, substream->stream); i2s_disable_channels(dev, substream->stream);
for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution); i2s_write_reg(dev->i2s_base, TCR(ch_reg),
xfer_resolution);
i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
} else { } else {
i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution); i2s_write_reg(dev->i2s_base, RCR(ch_reg),
xfer_resolution);
i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
} }
}
i2s_write_reg(dev->i2s_base, CCR, ccr); i2s_write_reg(dev->i2s_base, CCR, ccr);
......
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