Commit dcb09a97 authored by Jens Axboe's avatar Jens Axboe

amd74xx update

parent 737eac1e
...@@ -25,15 +25,14 @@ ...@@ -25,15 +25,14 @@
#include <asm/irq.h> #include <asm/irq.h>
#include "ide_modes.h" #include "ide_modes.h"
#include "amd74xx.h"
#define DISPLAY_VIPER_TIMINGS
#if defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS) #if defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h> #include <linux/stat.h>
#include <linux/proc_fs.h> #include <linux/proc_fs.h>
static int amd74xx_get_info(char *, char **, off_t, int); static u8 amd74xx_proc = 0;
extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
static struct pci_dev *bmide_dev; static struct pci_dev *bmide_dev;
static int amd74xx_get_info (char *buffer, char **addr, off_t offset, int count) static int amd74xx_get_info (char *buffer, char **addr, off_t offset, int count)
...@@ -46,8 +45,8 @@ static int amd74xx_get_info (char *buffer, char **addr, off_t offset, int count) ...@@ -46,8 +45,8 @@ static int amd74xx_get_info (char *buffer, char **addr, off_t offset, int count)
* at that point bibma+0x2 et bibma+0xa are byte registers * at that point bibma+0x2 et bibma+0xa are byte registers
* to investigate: * to investigate:
*/ */
c0 = IN_BYTE((unsigned short)bibma + 0x02); c0 = inb((unsigned short)bibma + 0x02);
c1 = IN_BYTE((unsigned short)bibma + 0x0a); c1 = inb((unsigned short)bibma + 0x0a);
p += sprintf(p, "\n " p += sprintf(p, "\n "
"AMD %04X VIPER Chipset.\n", bmide_dev->device); "AMD %04X VIPER Chipset.\n", bmide_dev->device);
...@@ -72,13 +71,12 @@ static int amd74xx_get_info (char *buffer, char **addr, off_t offset, int count) ...@@ -72,13 +71,12 @@ static int amd74xx_get_info (char *buffer, char **addr, off_t offset, int count)
} }
#endif /* defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS) */ #endif /* defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS) */
byte amd74xx_proc = 0;
static int amd74xx_mode5_check (struct pci_dev *dev) static int amd74xx_mode5_check (struct pci_dev *dev)
{ {
switch(dev->device) { switch(dev->device) {
case PCI_DEVICE_ID_AMD_VIPER_7411: case PCI_DEVICE_ID_AMD_VIPER_7411:
case PCI_DEVICE_ID_AMD_OPUS_7441: case PCI_DEVICE_ID_AMD_VIPER_7441:
case PCI_DEVICE_ID_AMD_8111_IDE:
return 1; return 1;
default: default:
return 0; return 0;
...@@ -97,79 +95,51 @@ static unsigned int amd74xx_swdma_check (struct pci_dev *dev) ...@@ -97,79 +95,51 @@ static unsigned int amd74xx_swdma_check (struct pci_dev *dev)
return ((int) (class_rev >= 7) ? 1 : 0); return ((int) (class_rev >= 7) ? 1 : 0);
} }
static int amd74xx_swdma_error (ide_drive_t *drive) static u8 amd74xx_ratemask (ide_drive_t *drive)
{ {
printk("%s: single-word DMA not support (revision < C4)\n", drive->name); u8 mode;
return 0;
}
static byte amd74xx_ratemask (ide_drive_t *drive) switch(HWIF(drive)->pci_dev->device) {
{ case PCI_DEVICE_ID_AMD_8111_IDE:
struct pci_dev *dev = HWIF(drive)->pci_dev; case PCI_DEVICE_ID_AMD_VIPER_7441:
byte mode = 0x00; case PCI_DEVICE_ID_AMD_VIPER_7411:
mode = 3;
switch(dev->device) { break;
case PCI_DEVICE_ID_AMD_OPUS_7441: case PCI_DEVICE_ID_AMD_VIPER_7409:
case PCI_DEVICE_ID_AMD_VIPER_7411: { mode |= 0x03; break; } mode = 2;
case PCI_DEVICE_ID_AMD_VIPER_7409: { mode |= 0x02; break; } break;
case PCI_DEVICE_ID_AMD_COBRA_7401: { mode |= 0x01; break; } case PCI_DEVICE_ID_AMD_COBRA_7401:
return 1;
default: default:
return (mode &= ~0xFF); return 0;
} }
if (!eighty_ninty_three(drive)) { if (!eighty_ninty_three(drive))
mode &= ~0xFE; mode = min(mode, (u8)1);
mode |= 0x01;
}
return (mode &= ~0xF8);
}
static byte amd74xx_ratefilter (ide_drive_t *drive, byte speed) return mode;
{
#ifdef CONFIG_BLK_DEV_IDEDMA
byte mode = amd74xx_ratemask(drive);
switch(mode) {
case 0x04: // while (speed > XFER_UDMA_6) speed--; break;
case 0x03: while (speed > XFER_UDMA_5) speed--; break;
case 0x02: while (speed > XFER_UDMA_4) speed--; break;
case 0x01: while (speed > XFER_UDMA_2) speed--; break;
case 0x00:
default: while (speed > XFER_MW_DMA_2) speed--; break;
break;
}
#else
while (speed > XFER_PIO_4) speed--;
#endif /* CONFIG_BLK_DEV_IDEDMA */
// printk("%s: mode == %02x speed == %02x\n", drive->name, mode, speed);
return speed;
} }
/* /*
* Here is where all the hard work goes to program the chipset. * Here is where all the hard work goes to program the chipset.
*/ */
static int amd74xx_tune_chipset (ide_drive_t *drive, byte xferspeed) static int amd74xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{ {
u8 drive_pci[] = { 0x53, 0x52, 0x51, 0x50 };
u8 drive_pci2[] = { 0x4b, 0x4a, 0x49, 0x48 };
#if 0
u8 ultra_rate[] = { 0x42, 0x41, 0x40, 0x44, 0x45, 0x46 };
u8 mwdma_rate[] = { 0x77, 0x21, 0x20 };
u8 swdma_rate[] = { 0xA8, 0x65, 0x42 };
u8 pio_rate[] = { 0xA8, 0x65, 0x42, 0x22, 0x20};
#endif
ide_hwif_t *hwif = HWIF(drive); ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev; struct pci_dev *dev = hwif->pci_dev;
byte speed = amd74xx_ratefilter(drive, xferspeed); u8 speed = ide_rate_filter(amd74xx_ratemask(drive), xferspeed);
byte drive_pci = 0x00; u8 ultra_timing = 0, dma_pio_timing = 0, pio_timing = 0;
byte drive_pci2 = 0x00;
byte ultra_timing = 0x00;
byte dma_pio_timing = 0x00;
byte pio_timing = 0x00;
switch (drive->dn) {
case 0: drive_pci = 0x53; drive_pci2 = 0x4b; break;
case 1: drive_pci = 0x52; drive_pci2 = 0x4a; break;
case 2: drive_pci = 0x51; drive_pci2 = 0x49; break;
case 3: drive_pci = 0x50; drive_pci2 = 0x48; break;
default:
return -1;
}
pci_read_config_byte(dev, drive_pci, &ultra_timing); pci_read_config_byte(dev, drive_pci[drive->dn], &ultra_timing);
pci_read_config_byte(dev, drive_pci2, &dma_pio_timing); pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_pio_timing);
pci_read_config_byte(dev, 0x4c, &pio_timing); pci_read_config_byte(dev, 0x4c, &pio_timing);
ultra_timing &= ~0xC7; ultra_timing &= ~0xC7;
...@@ -215,18 +185,12 @@ static int amd74xx_tune_chipset (ide_drive_t *drive, byte xferspeed) ...@@ -215,18 +185,12 @@ static int amd74xx_tune_chipset (ide_drive_t *drive, byte xferspeed)
dma_pio_timing |= 0x77; dma_pio_timing |= 0x77;
break; break;
case XFER_SW_DMA_2: case XFER_SW_DMA_2:
if (!amd74xx_swdma_check(dev))
return amd74xx_swdma_error(drive);
dma_pio_timing |= 0x42; dma_pio_timing |= 0x42;
break; break;
case XFER_SW_DMA_1: case XFER_SW_DMA_1:
if (!amd74xx_swdma_check(dev))
return amd74xx_swdma_error(drive);
dma_pio_timing |= 0x65; dma_pio_timing |= 0x65;
break; break;
case XFER_SW_DMA_0: case XFER_SW_DMA_0:
if (!amd74xx_swdma_check(dev))
return amd74xx_swdma_error(drive);
dma_pio_timing |= 0xA8; dma_pio_timing |= 0xA8;
break; break;
#endif /* CONFIG_BLK_DEV_IDEDMA */ #endif /* CONFIG_BLK_DEV_IDEDMA */
...@@ -251,26 +215,18 @@ static int amd74xx_tune_chipset (ide_drive_t *drive, byte xferspeed) ...@@ -251,26 +215,18 @@ static int amd74xx_tune_chipset (ide_drive_t *drive, byte xferspeed)
pio_timing |= (0x03 << drive->dn); pio_timing |= (0x03 << drive->dn);
#ifdef CONFIG_BLK_DEV_IDEDMA #ifdef CONFIG_BLK_DEV_IDEDMA
pci_write_config_byte(dev, drive_pci, ultra_timing); pci_write_config_byte(dev, drive_pci[drive->dn], ultra_timing);
#endif /* CONFIG_BLK_DEV_IDEDMA */ #endif /* CONFIG_BLK_DEV_IDEDMA */
pci_write_config_byte(dev, drive_pci2, dma_pio_timing); pci_write_config_byte(dev, drive_pci2[drive->dn], dma_pio_timing);
pci_write_config_byte(dev, 0x4c, pio_timing); pci_write_config_byte(dev, 0x4c, pio_timing);
return (ide_config_drive_speed(drive, speed)); return (ide_config_drive_speed(drive, speed));
} }
static void amd74xx_tune_drive (ide_drive_t *drive, byte pio) static void amd74xx_tune_drive (ide_drive_t *drive, u8 pio)
{ {
byte speed;
pio = ide_get_best_pio_mode(drive, pio, 5, NULL); pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
switch(pio) { (void) amd74xx_tune_chipset(drive, (XFER_PIO_0 + pio));
case 4: speed = XFER_PIO_4;break;
case 3: speed = XFER_PIO_3;break;
case 2: speed = XFER_PIO_2;break;
case 1: speed = XFER_PIO_1;break;
default: speed = XFER_PIO_0;break;
}
(void) amd74xx_tune_chipset(drive, speed);
} }
#ifdef CONFIG_BLK_DEV_IDEDMA #ifdef CONFIG_BLK_DEV_IDEDMA
...@@ -281,169 +237,84 @@ static void amd74xx_tune_drive (ide_drive_t *drive, byte pio) ...@@ -281,169 +237,84 @@ static void amd74xx_tune_drive (ide_drive_t *drive, byte pio)
*/ */
static int config_chipset_for_dma (ide_drive_t *drive) static int config_chipset_for_dma (ide_drive_t *drive)
{ {
struct hd_driveid *id = drive->id; u8 speed = ide_dma_speed(drive, amd74xx_ratemask(drive));
byte mode = amd74xx_ratemask(drive);
byte swdma = amd74xx_swdma_check(HWIF(drive)->pci_dev); if (!(speed))
byte speed = 0; return 0;
int rval;
amd74xx_tune_drive(drive, 5);
switch(mode) {
case 0x04:
if (id->dma_ultra & 0x0040)
{ speed = XFER_UDMA_6; break; }
case 0x03:
if (id->dma_ultra & 0x0020)
{ speed = XFER_UDMA_5; break; }
case 0x02:
if (id->dma_ultra & 0x0010)
{ speed = XFER_UDMA_4; break; }
if (id->dma_ultra & 0x0008)
{ speed = XFER_UDMA_3; break; }
case 0x01:
if (id->dma_ultra & 0x0004)
{ speed = XFER_UDMA_2; break; }
if (id->dma_ultra & 0x0002)
{ speed = XFER_UDMA_1; break; }
if (id->dma_ultra & 0x0001)
{ speed = XFER_UDMA_0; break; }
case 0x00:
if (id->dma_mword & 0x0004)
{ speed = XFER_MW_DMA_2; break; }
if (id->dma_mword & 0x0002)
{ speed = XFER_MW_DMA_1; break; }
if (id->dma_mword & 0x0001)
{ speed = XFER_MW_DMA_0; break; }
if ((id->dma_1word & 0x0004) && (swdma))
{ speed = XFER_SW_DMA_2; break; }
if ((id->dma_1word & 0x0002) && (swdma))
{ speed = XFER_SW_DMA_1; break; }
if ((id->dma_1word & 0x0001) && (swdma))
{ speed = XFER_SW_DMA_0; break; }
default:
return ((int) ide_dma_off_quietly);
}
(void) amd74xx_tune_chipset(drive, speed); (void) amd74xx_tune_chipset(drive, speed);
// return ((int) (dma) ? ide_dma_on : ide_dma_off_quietly); return ide_dma_enable(drive);
rval = (int)( ((id->dma_ultra >> 11) & 7) ? ide_dma_on :
((id->dma_ultra >> 8) & 7) ? ide_dma_on :
((id->dma_mword >> 8) & 7) ? ide_dma_on :
(((id->dma_1word >> 8) & 7) && (swdma)) ? ide_dma_on :
ide_dma_off_quietly);
return rval;
} }
static int config_drive_xfer_rate (ide_drive_t *drive) static int amd74xx_config_drive_xfer_rate (ide_drive_t *drive)
{ {
struct hd_driveid *id = drive->id;
ide_hwif_t *hwif = HWIF(drive); ide_hwif_t *hwif = HWIF(drive);
ide_dma_action_t dma_func = ide_dma_on; struct hd_driveid *id = drive->id;
drive->init_speed = 0; drive->init_speed = 0;
if (id && (id->capability & 1) && hwif->autodma) { if (id && (id->capability & 1) && drive->autodma) {
/* Consult the list of known "bad" drives */ /* Consult the list of known "bad" drives */
if (ide_dmaproc(ide_dma_bad_drive, drive)) { if (hwif->ide_dma_bad_drive(drive))
dma_func = ide_dma_off;
goto fast_ata_pio; goto fast_ata_pio;
}
dma_func = ide_dma_off_quietly;
if (id->field_valid & 4) { if (id->field_valid & 4) {
if (id->dma_ultra & 0x003F) { if (id->dma_ultra & hwif->ultra_mask) {
/* Force if Capable UltraDMA */ /* Force if Capable UltraDMA */
dma_func = config_chipset_for_dma(drive); int dma = config_chipset_for_dma(drive);
if ((id->field_valid & 2) && if ((id->field_valid & 2) && dma)
(dma_func != ide_dma_on))
goto try_dma_modes; goto try_dma_modes;
} }
} else if (id->field_valid & 2) { } else if (id->field_valid & 2) {
try_dma_modes: try_dma_modes:
if ((id->dma_mword & 0x0007) || if ((id->dma_mword & hwif->mwdma_mask) ||
((id->dma_1word & 0x007) && (id->dma_1word & hwif->swdma_mask)) {
(amd74xx_swdma_check(HWIF(drive)->pci_dev)))) {
/* Force if Capable regular DMA modes */ /* Force if Capable regular DMA modes */
dma_func = config_chipset_for_dma(drive); if (!config_chipset_for_dma(drive))
if (dma_func != ide_dma_on)
goto no_dma_set; goto no_dma_set;
} }
} else if (ide_dmaproc(ide_dma_good_drive, drive)) { } else if (hwif->ide_dma_good_drive(drive) &&
if (id->eide_dma_time > 150) { (id->eide_dma_time < 150)) {
goto no_dma_set;
}
/* Consult the list of known "good" drives */ /* Consult the list of known "good" drives */
dma_func = config_chipset_for_dma(drive); if (!config_chipset_for_dma(drive))
if (dma_func != ide_dma_on)
goto no_dma_set; goto no_dma_set;
} else { } else {
goto fast_ata_pio; goto fast_ata_pio;
} }
} else if ((id->capability & 8) || (id->field_valid & 2)) { } else if ((id->capability & 8) || (id->field_valid & 2)) {
fast_ata_pio: fast_ata_pio:
dma_func = ide_dma_off_quietly;
no_dma_set: no_dma_set:
amd74xx_tune_drive(drive, 5); amd74xx_tune_drive(drive, 5);
return hwif->ide_dma_off_quietly(drive);
} }
return HWIF(drive)->dmaproc(dma_func, drive); return hwif->ide_dma_on(drive);
}
/*
* amd74xx_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
*/
int amd74xx_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
{
switch (func) {
case ide_dma_check:
return config_drive_xfer_rate(drive);
default:
break;
}
return ide_dmaproc(func, drive); /* use standard DMA stuff */
} }
#endif /* CONFIG_BLK_DEV_IDEDMA */ #endif /* CONFIG_BLK_DEV_IDEDMA */
unsigned int __init pci_init_amd74xx (struct pci_dev *dev, const char *name) static unsigned int __init init_chipset_amd74xx (struct pci_dev *dev, const char *name)
{ {
unsigned long fixdma_base = pci_resource_start(dev, 4);
#ifdef CONFIG_BLK_DEV_IDEDMA #ifdef CONFIG_BLK_DEV_IDEDMA
if (!amd74xx_swdma_check(dev)) if (!amd74xx_swdma_check(dev))
printk("%s: disabling single-word DMA support (revision < C4)\n", name); printk("%s: disabling single-word DMA support (revision < C4)\n", name);
#endif /* CONFIG_BLK_DEV_IDEDMA */ #endif /* CONFIG_BLK_DEV_IDEDMA */
if (!fixdma_base) {
/*
*
*/
} else {
/*
* enable DMA capable bit, and "not" simplex only
*/
OUT_BYTE(IN_BYTE(fixdma_base+2) & 0x60, fixdma_base+2);
if (IN_BYTE(fixdma_base+2) & 0x80)
printk("%s: simplex device: DMA will fail!!\n", name);
}
#if defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS) #if defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS)
if (!amd74xx_proc) { if (!amd74xx_proc) {
amd74xx_proc = 1; amd74xx_proc = 1;
bmide_dev = dev; bmide_dev = dev;
amd74xx_display_info = &amd74xx_get_info; ide_pci_register_host_proc(&amd74xx_procs[0]);
} }
#endif /* DISPLAY_VIPER_TIMINGS && CONFIG_PROC_FS */ #endif /* DISPLAY_VIPER_TIMINGS && CONFIG_PROC_FS */
return 0; return 0;
} }
unsigned int __init ata66_amd74xx (ide_hwif_t *hwif) static unsigned int __init ata66_amd74xx (ide_hwif_t *hwif)
{ {
struct pci_dev *dev = hwif->pci_dev; struct pci_dev *dev = hwif->pci_dev;
byte cable_80_pin[2] = { 0, 0 }; u8 cable_80_pin[2] = { 0, 0 };
byte ata66 = 0; u8 ata66 = 0;
byte tmpbyte; u8 tmpbyte;
/* /*
* Ultra66 cable detection (from Host View) * Ultra66 cable detection (from Host View)
...@@ -464,7 +335,11 @@ unsigned int __init ata66_amd74xx (ide_hwif_t *hwif) ...@@ -464,7 +335,11 @@ unsigned int __init ata66_amd74xx (ide_hwif_t *hwif)
if (tmpbyte & 0x04) cable_80_pin[1] = 1; if (tmpbyte & 0x04) cable_80_pin[1] = 1;
switch(dev->device) { switch(dev->device) {
case PCI_DEVICE_ID_AMD_OPUS_7441: case PCI_DEVICE_ID_AMD_COBRA_7401:
cable_80_pin[hwif->channel] = 0;
return 0;
case PCI_DEVICE_ID_AMD_8111_IDE:
case PCI_DEVICE_ID_AMD_VIPER_7441:
case PCI_DEVICE_ID_AMD_VIPER_7411: case PCI_DEVICE_ID_AMD_VIPER_7411:
ata66 = (hwif->channel) ? ata66 = (hwif->channel) ?
cable_80_pin[1] : cable_80_pin[1] :
...@@ -479,41 +354,64 @@ unsigned int __init ata66_amd74xx (ide_hwif_t *hwif) ...@@ -479,41 +354,64 @@ unsigned int __init ata66_amd74xx (ide_hwif_t *hwif)
#endif /* CONFIG_AMD74XX_OVERRIDE */ #endif /* CONFIG_AMD74XX_OVERRIDE */
} }
void __init ide_init_amd74xx (ide_hwif_t *hwif) static void __init init_hwif_amd74xx (ide_hwif_t *hwif)
{ {
hwif->autodma = 0;
hwif->tuneproc = &amd74xx_tune_drive; hwif->tuneproc = &amd74xx_tune_drive;
hwif->speedproc = &amd74xx_tune_chipset; hwif->speedproc = &amd74xx_tune_chipset;
if (!hwif->dma_base) { if (!hwif->dma_base) {
hwif->drives[0].autotune = 1; hwif->drives[0].autotune = 1;
hwif->drives[1].autotune = 1; hwif->drives[1].autotune = 1;
hwif->autodma = 0;
return; return;
} }
#ifndef CONFIG_BLK_DEV_IDEDMA hwif->atapi_dma = 1;
hwif->dmaproc = &amd74xx_dmaproc; hwif->ultra_mask = 0x3f;
#ifdef CONFIG_IDEDMA_AUTO hwif->mwdma_mask = 0x07;
if (amd74xx_swdma_check(hwif->pci_dev))
hwif->swdma_mask = 0x07;
#ifdef CONFIG_BLK_DEV_IDEDMA
if (!(hwif->udma_four))
hwif->udma_four = ata66_amd74xx(hwif);
hwif->ide_dma_check = &amd74xx_config_drive_xfer_rate;
if (!noautodma) if (!noautodma)
hwif->autodma = 1; hwif->autodma = 1;
#endif /* CONFIG_IDEDMA_AUTO */ hwif->drives[0].autodma = hwif->autodma;
hwif->drives[1].autodma = hwif->autodma;
#endif /* CONFIG_BLK_DEV_IDEDMA */ #endif /* CONFIG_BLK_DEV_IDEDMA */
} }
void __init ide_dmacapable_amd74xx (ide_hwif_t *hwif, unsigned long dmabase) static void __init init_dma_amd74xx (ide_hwif_t *hwif, unsigned long dmabase)
{ {
if (!(hwif->channel))
hwif->OUTB(hwif->INB(dmabase+2) & 0x60, dmabase+2);
ide_setup_dma(hwif, dmabase, 8); ide_setup_dma(hwif, dmabase, 8);
} }
extern void ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *d); extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
void __init fixup_device_amd74xx (struct pci_dev *dev, ide_pci_device_t *d) static void __init init_setup_amd74xx (struct pci_dev *dev, ide_pci_device_t *d)
{ {
if (dev->resource[0].start != 0x01F1)
ide_register_xp_fix(dev);
printk("%s: IDE controller on PCI bus %02x dev %02x\n",
d->name, dev->bus->number, dev->devfn);
ide_setup_pci_device(dev, d); ide_setup_pci_device(dev, d);
} }
int __init amd74xx_scan_pcidev (struct pci_dev *dev)
{
ide_pci_device_t *d;
if (dev->vendor != PCI_VENDOR_ID_AMD)
return 0;
for (d = amd74xx_chipsets; d && d->vendor && d->device; ++d) {
if (((d->vendor == dev->vendor) &&
(d->device == dev->device)) &&
(d->init_setup)) {
d->init_setup(dev, d);
return 1;
}
}
return 0;
}
#ifndef AMD74XX_H
#define AMD74XX_H
#include <linux/config.h>
#include <linux/pci.h>
#include <linux/ide.h>
#define DISPLAY_VIPER_TIMINGS
#if defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
static u8 amd74xx_proc;
static int amd74xx_get_info(char *, char **, off_t, int);
static ide_pci_host_proc_t amd74xx_procs[] __initdata = {
{
name: "amd74xx",
set: 1,
get_info: amd74xx_get_info,
parent: NULL,
},
};
#endif /* defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS) */
static void init_setup_amd74xx(struct pci_dev *, ide_pci_device_t *);
static unsigned int init_chipset_amd74xx(struct pci_dev *, const char *);
static void init_hwif_amd74xx(ide_hwif_t *);
static void init_dma_amd74xx(ide_hwif_t *, unsigned long);
static ide_pci_device_t amd74xx_chipsets[] __initdata = {
{
vendor: PCI_VENDOR_ID_AMD,
device: PCI_DEVICE_ID_AMD_COBRA_7401,
name: "AMD7401",
init_setup: init_setup_amd74xx,
init_chipset: init_chipset_amd74xx,
init_iops: NULL,
init_hwif: init_hwif_amd74xx,
init_dma: init_dma_amd74xx,
channels: 2,
autodma: AUTODMA,
enablebits: {{0x40,0x01,0x01}, {0x40,0x02,0x02}},
bootable: ON_BOARD,
extra: 0
},{
vendor: PCI_VENDOR_ID_AMD,
device: PCI_DEVICE_ID_AMD_VIPER_7409,
name: "AMD7409",
init_setup: init_setup_amd74xx,
init_chipset: init_chipset_amd74xx,
init_iops: NULL,
init_hwif: init_hwif_amd74xx,
init_dma: init_dma_amd74xx,
channels: 2,
autodma: AUTODMA,
enablebits: {{0x40,0x01,0x01}, {0x40,0x02,0x02}},
bootable: ON_BOARD,
extra: 0
},{
vendor: PCI_VENDOR_ID_AMD,
device: PCI_DEVICE_ID_AMD_VIPER_7411,
name: "AMD7411",
init_setup: init_setup_amd74xx,
init_chipset: init_chipset_amd74xx,
init_iops: NULL,
init_hwif: init_hwif_amd74xx,
init_dma: init_dma_amd74xx,
channels: 2,
autodma: AUTODMA,
enablebits: {{0x40,0x01,0x01}, {0x40,0x02,0x02}},
bootable: ON_BOARD,
extra: 0
},{
vendor: PCI_VENDOR_ID_AMD,
device: PCI_DEVICE_ID_AMD_OPUS_7441,
name: "AMD7441",
init_setup: init_setup_amd74xx,
init_chipset: init_chipset_amd74xx,
init_iops: NULL,
init_hwif: init_hwif_amd74xx,
init_dma: init_dma_amd74xx,
channels: 2,
autodma: AUTODMA,
enablebits: {{0x40,0x01,0x01}, {0x40,0x02,0x02}},
bootable: ON_BOARD,
extra: 0
},{
vendor: PCI_VENDOR_ID_AMD,
device: PCI_DEVICE_ID_AMD_8111_IDE,
name: "AMD8111",
init_setup: init_setup_amd74xx,
init_chipset: init_chipset_amd74xx,
init_iops: NULL,
init_hwif: init_hwif_amd74xx,
init_dma: init_dma_amd74xx,
autodma: AUTODMA,
channels: 2,
enablebits: {{0x40,0x01,0x01}, {0x40,0x02,0x02}},
bootable: ON_BOARD,
extra: 0
},{
vendor: 0,
device: 0,
channels: 0,
bootable: EOL,
}
};
#endif /* AMD74XX_H */
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