Commit e5655492 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Felix Fietkau

mt76: dma: rely on mt76_queue in mt76_dma_tx_cleanup signature

This is a preliminary patch to move data queues in mt76_phy and properly
support dbdc
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 264b7b19
...@@ -217,9 +217,8 @@ mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) ...@@ -217,9 +217,8 @@ mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
} }
static void static void
mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush) mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
{ {
struct mt76_queue *q = dev->q_tx[qid];
struct mt76_queue_entry entry; struct mt76_queue_entry entry;
bool wake = false; bool wake = false;
int last; int last;
...@@ -255,7 +254,7 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush) ...@@ -255,7 +254,7 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush)
} }
wake = wake && q->stopped && wake = wake && q->stopped &&
qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8; q->qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8;
if (wake) if (wake)
q->stopped = false; q->stopped = false;
...@@ -263,7 +262,7 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush) ...@@ -263,7 +262,7 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush)
wake_up(&dev->tx_wait); wake_up(&dev->tx_wait);
if (wake) if (wake)
ieee80211_wake_queue(dev->hw, qid); ieee80211_wake_queue(dev->hw, q->qid);
} }
static void * static void *
...@@ -664,7 +663,7 @@ void mt76_dma_cleanup(struct mt76_dev *dev) ...@@ -664,7 +663,7 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
mt76_worker_disable(&dev->tx_worker); mt76_worker_disable(&dev->tx_worker);
netif_napi_del(&dev->tx_napi); netif_napi_del(&dev->tx_napi);
for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++) for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++)
mt76_dma_tx_cleanup(dev, i, true); mt76_dma_tx_cleanup(dev, dev->q_tx[i], true);
mt76_for_each_q_rx(dev, i) { mt76_for_each_q_rx(dev, i) {
netif_napi_del(&dev->napi[i]); netif_napi_del(&dev->napi[i]);
......
...@@ -122,7 +122,8 @@ int mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, ...@@ -122,7 +122,8 @@ int mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
len -= cur_len; len -= cur_len;
if (dev->queue_ops->tx_cleanup) if (dev->queue_ops->tx_cleanup)
dev->queue_ops->tx_cleanup(dev, MT_TXQ_FWDL, false); dev->queue_ops->tx_cleanup(dev, dev->q_tx[MT_TXQ_FWDL],
false);
} }
return 0; return 0;
......
...@@ -179,7 +179,7 @@ struct mt76_queue_ops { ...@@ -179,7 +179,7 @@ struct mt76_queue_ops {
void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
void (*tx_cleanup)(struct mt76_dev *dev, enum mt76_txq_id qid, void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q,
bool flush); bool flush);
void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
......
...@@ -89,7 +89,7 @@ void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t) ...@@ -89,7 +89,7 @@ void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t)
/* Flush all previous CAB queue packets */ /* Flush all previous CAB queue packets */
mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0)); mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0));
mt76_queue_tx_cleanup(dev, MT_TXQ_CAB, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_CAB], false);
mt76_csa_check(&dev->mt76); mt76_csa_check(&dev->mt76);
if (dev->mt76.csa_complete) if (dev->mt76.csa_complete)
...@@ -135,7 +135,7 @@ void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t) ...@@ -135,7 +135,7 @@ void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t)
((1 << (MT7603_MAX_INTERFACES - 1)) - 1))); ((1 << (MT7603_MAX_INTERFACES - 1)) - 1)));
out: out:
mt76_queue_tx_cleanup(dev, MT_TXQ_BEACON, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_BEACON], false);
if (dev->mt76.q_tx[MT_TXQ_BEACON]->queued > if (dev->mt76.q_tx[MT_TXQ_BEACON]->queued >
hweight8(dev->mt76.beacon_mask)) hweight8(dev->mt76.beacon_mask))
dev->beacon_check++; dev->beacon_check++;
......
...@@ -147,13 +147,13 @@ static int mt7603_poll_tx(struct napi_struct *napi, int budget) ...@@ -147,13 +147,13 @@ static int mt7603_poll_tx(struct napi_struct *napi, int budget)
dev->tx_dma_check = 0; dev->tx_dma_check = 0;
for (i = MT_TXQ_MCU; i >= 0; i--) for (i = MT_TXQ_MCU; i >= 0; i--)
mt76_queue_tx_cleanup(dev, i, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], false);
if (napi_complete_done(napi, 0)) if (napi_complete_done(napi, 0))
mt7603_irq_enable(dev, MT_INT_TX_DONE_ALL); mt7603_irq_enable(dev, MT_INT_TX_DONE_ALL);
for (i = MT_TXQ_MCU; i >= 0; i--) for (i = MT_TXQ_MCU; i >= 0; i--)
mt76_queue_tx_cleanup(dev, i, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], false);
mt7603_mac_sta_poll(dev); mt7603_mac_sta_poll(dev);
......
...@@ -1435,7 +1435,7 @@ static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev) ...@@ -1435,7 +1435,7 @@ static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
mt7603_pse_client_reset(dev); mt7603_pse_client_reset(dev);
for (i = 0; i < __MT_TXQ_MAX; i++) for (i = 0; i < __MT_TXQ_MAX; i++)
mt76_queue_tx_cleanup(dev, i, true); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], true);
mt76_for_each_q_rx(&dev->mt76, i) { mt76_for_each_q_rx(&dev->mt76, i) {
mt76_queue_rx_reset(dev, i); mt76_queue_rx_reset(dev, i);
......
...@@ -75,7 +75,7 @@ static int mt7615_poll_tx(struct napi_struct *napi, int budget) ...@@ -75,7 +75,7 @@ static int mt7615_poll_tx(struct napi_struct *napi, int budget)
dev = container_of(napi, struct mt7615_dev, mt76.tx_napi); dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_MCU], false);
if (napi_complete_done(napi, 0)) if (napi_complete_done(napi, 0))
mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev)); mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev));
......
...@@ -1435,12 +1435,12 @@ static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb) ...@@ -1435,12 +1435,12 @@ static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data; struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
u8 i, count; u8 i, count;
mt76_queue_tx_cleanup(dev, MT_TXQ_PSD, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_PSD], false);
if (is_mt7615(&dev->mt76)) { if (is_mt7615(&dev->mt76)) {
mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_BE], false);
} else { } else {
for (i = 0; i < IEEE80211_NUM_ACS; i++) for (i = 0; i < IEEE80211_NUM_ACS; i++)
mt76_queue_tx_cleanup(dev, i, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], false);
} }
count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl)); count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
...@@ -2045,7 +2045,7 @@ void mt7615_dma_reset(struct mt7615_dev *dev) ...@@ -2045,7 +2045,7 @@ void mt7615_dma_reset(struct mt7615_dev *dev)
usleep_range(1000, 2000); usleep_range(1000, 2000);
for (i = 0; i < __MT_TXQ_MAX; i++) for (i = 0; i < __MT_TXQ_MAX; i++)
mt76_queue_tx_cleanup(dev, i, true); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], true);
mt76_for_each_q_rx(&dev->mt76, i) { mt76_for_each_q_rx(&dev->mt76, i) {
mt76_queue_rx_reset(dev, i); mt76_queue_rx_reset(dev, i);
......
...@@ -2464,7 +2464,7 @@ int mt7615_mcu_init(struct mt7615_dev *dev) ...@@ -2464,7 +2464,7 @@ int mt7615_mcu_init(struct mt7615_dev *dev)
if (ret) if (ret)
return ret; return ret;
mt76_queue_tx_cleanup(dev, MT_TXQ_FWDL, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_FWDL], false);
dev_dbg(dev->mt76.dev, "Firmware init done\n"); dev_dbg(dev->mt76.dev, "Firmware init done\n");
set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
mt7615_mcu_fw_log_2_host(dev, 0); mt7615_mcu_fw_log_2_host(dev, 0);
......
...@@ -164,13 +164,13 @@ static int mt76x02_poll_tx(struct napi_struct *napi, int budget) ...@@ -164,13 +164,13 @@ static int mt76x02_poll_tx(struct napi_struct *napi, int budget)
mt76x02_mac_poll_tx_status(dev, false); mt76x02_mac_poll_tx_status(dev, false);
for (i = MT_TXQ_MCU; i >= 0; i--) for (i = MT_TXQ_MCU; i >= 0; i--)
mt76_queue_tx_cleanup(dev, i, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], false);
if (napi_complete_done(napi, 0)) if (napi_complete_done(napi, 0))
mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL); mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
for (i = MT_TXQ_MCU; i >= 0; i--) for (i = MT_TXQ_MCU; i >= 0; i--)
mt76_queue_tx_cleanup(dev, i, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], false);
mt76_worker_schedule(&dev->mt76.tx_worker); mt76_worker_schedule(&dev->mt76.tx_worker);
...@@ -469,7 +469,7 @@ static void mt76x02_watchdog_reset(struct mt76x02_dev *dev) ...@@ -469,7 +469,7 @@ static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
mt76_mcu_restart(dev); mt76_mcu_restart(dev);
for (i = 0; i < __MT_TXQ_MAX; i++) for (i = 0; i < __MT_TXQ_MAX; i++)
mt76_queue_tx_cleanup(dev, i, true); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], true);
mt76_for_each_q_rx(&dev->mt76, i) { mt76_for_each_q_rx(&dev->mt76, i) {
mt76_queue_rx_reset(dev, i); mt76_queue_rx_reset(dev, i);
......
...@@ -56,8 +56,8 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, ...@@ -56,8 +56,8 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
static void static void
mt7915_tx_cleanup(struct mt7915_dev *dev) mt7915_tx_cleanup(struct mt7915_dev *dev)
{ {
mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_MCU], false);
mt76_queue_tx_cleanup(dev, MT_TXQ_MCU_WA, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_MCU_WA], false);
} }
static int mt7915_poll_tx(struct napi_struct *napi, int budget) static int mt7915_poll_tx(struct napi_struct *napi, int budget)
......
...@@ -1072,8 +1072,8 @@ void mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb) ...@@ -1072,8 +1072,8 @@ void mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb)
u8 i, count; u8 i, count;
/* clean DMA queues and unmap buffers first */ /* clean DMA queues and unmap buffers first */
mt76_queue_tx_cleanup(dev, MT_TXQ_PSD, false); mt76_queue_tx_cleanup(dev, mdev->q_tx[MT_TXQ_PSD], false);
mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false); mt76_queue_tx_cleanup(dev, mdev->q_tx[MT_TXQ_BE], false);
/* /*
* TODO: MT_TX_FREE_LATENCY is msdu time from the TXD is queued into PLE, * TODO: MT_TX_FREE_LATENCY is msdu time from the TXD is queued into PLE,
...@@ -1421,7 +1421,7 @@ mt7915_dma_reset(struct mt7915_dev *dev) ...@@ -1421,7 +1421,7 @@ mt7915_dma_reset(struct mt7915_dev *dev)
usleep_range(1000, 2000); usleep_range(1000, 2000);
for (i = 0; i < __MT_TXQ_MAX; i++) for (i = 0; i < __MT_TXQ_MAX; i++)
mt76_queue_tx_cleanup(dev, i, true); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], true);
mt76_for_each_q_rx(&dev->mt76, i) { mt76_for_each_q_rx(&dev->mt76, i) {
mt76_queue_rx_reset(dev, i); mt76_queue_rx_reset(dev, i);
......
...@@ -2799,7 +2799,7 @@ static int mt7915_load_firmware(struct mt7915_dev *dev) ...@@ -2799,7 +2799,7 @@ static int mt7915_load_firmware(struct mt7915_dev *dev)
return -EIO; return -EIO;
} }
mt76_queue_tx_cleanup(dev, MT_TXQ_FWDL, false); mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_FWDL], false);
dev_dbg(dev->mt76.dev, "Firmware init done\n"); dev_dbg(dev->mt76.dev, "Firmware init done\n");
......
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