Commit e5a32b5b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Paul Burton:
 "Here are the main MIPS changes for 4.19.

  An overview of the general architecture changes:

   - Massive DMA ops refactoring from Christoph Hellwig (huzzah for
     deleting crufty code!).

   - We introduce NT_MIPS_DSP & NT_MIPS_FP_MODE ELF notes &
     corresponding regsets to expose DSP ASE & floating point mode state
     respectively, both for live debugging & core dumps.

   - We better optimize our code by hard-coding cpu_has_* macros at
     compile time where their values are known due to the ISA revision
     that the kernel build is targeting.

   - The EJTAG exception handler now better handles SMP systems, where
     it was previously possible for CPUs to clobber a register value
     saved by another CPU.

   - Our implementation of memset() gained a couple of fixes for MIPSr6
     systems to return correct values in some cases where stores fault.

   - We now implement ioremap_wc() using the uncached-accelerated cache
     coherency attribute where supported, which is detected during boot,
     and fall back to plain uncached access where necessary. The
     MIPS-specific (and unused in tree) ioremap_uncached_accelerated() &
     ioremap_cacheable_cow() are removed.

   - The prctl(PR_SET_FP_MODE, ...) syscall is better supported for SMP
     systems by reworking the way we ensure remote CPUs that may be
     running threads within the affected process switch mode.

   - Systems using the MIPS Coherence Manager will now set the
     MIPS_IC_SNOOPS_REMOTE flag to avoid some unnecessary cache
     maintenance overhead when flushing the icache.

   - A few fixes were made for building with clang/LLVM, which now
     sucessfully builds kernels for many of our platforms.

   - Miscellaneous cleanups all over.

  And some platform-specific changes:

   - ar7 gained stubs for a few clock API functions to fix build
     failures for some drivers.

   - ath79 gained support for a few new SoCs, a few fixes & better
     gpio-keys support.

   - Ci20 now exposes its SPI bus using the spi-gpio driver.

   - The generic platform can now auto-detect a suitable value for
     PHYS_OFFSET based upon the memory map described by the device tree,
     allowing us to avoid wasting memory on page book-keeping for
     systems where RAM starts at a non-zero physical address.

   - Ingenic systems using the jz4740 platform code now link their
     vmlinuz higher to allow for kernels of a realistic size.

   - Loongson32 now builds the kernel targeting MIPSr1 rather than
     MIPSr2 to avoid CPU errata.

   - Loongson64 gains a couple of fixes, a workaround for a write
     buffering issue & support for the Loongson 3A R3.1 CPU.

   - Malta now uses the piix4-poweroff driver to handle powering down.

   - Microsemi Ocelot gained support for its SPI bus & NOR flash, its
     second MDIO bus and can now be supported by a FIT/.itb image.

   - Octeon saw a bunch of header cleanups which remove a lot of
     duplicate or unused code"

* tag 'mips_4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (123 commits)
  MIPS: Remove remnants of UASM_ISA
  MIPS: netlogic: xlr: Remove erroneous check in nlm_fmn_send()
  MIPS: VDSO: Force link endianness
  MIPS: Always specify -EB or -EL when using clang
  MIPS: Use dins to simplify __write_64bit_c0_split()
  MIPS: Use read-write output operand in __write_64bit_c0_split()
  MIPS: Avoid using array as parameter to write_c0_kpgd()
  MIPS: vdso: Allow clang's --target flag in VDSO cflags
  MIPS: genvdso: Remove GOT checks
  MIPS: Remove obsolete MIPS checks for DST node "chosen@0"
  MIPS: generic: Remove input symbols from defconfig
  MIPS: Delete unused code in linux32.c
  MIPS: Remove unused sys_32_mmap2
  MIPS: Remove nabi_no_regargs
  mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123
  mips: dts: mscc: Add spi on Ocelot
  MIPS: Loongson: Merge load addresses
  MIPS: Loongson: Set Loongson32 to MIPS32R1
  MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller
  MIPS: generic: Select MIPS_AUTO_PFN_OFFSET
  ...
parents 2280a536 22f20a11
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
Required properties: Required properties:
- compatible: "qca,ar7100-usb-phy" - compatible: "qca,ar7100-usb-phy"
- #phys-cells: should be 0 - #phys-cells: should be 0
- reset-names: "usb-phy"[, "usb-suspend-override"] - reset-names: "phy"[, "suspend-override"]
- resets: references to the reset controllers - resets: references to the reset controllers
Example: Example:
...@@ -11,7 +11,7 @@ Example: ...@@ -11,7 +11,7 @@ Example:
usb-phy { usb-phy {
compatible = "qca,ar7100-usb-phy"; compatible = "qca,ar7100-usb-phy";
reset-names = "usb-phy", "usb-suspend-override"; reset-names = "phy", "suspend-override";
resets = <&rst 4>, <&rst 3>; resets = <&rst 4>, <&rst 3>;
#phy-cells = <0>; #phy-cells = <0>;
......
...@@ -16,6 +16,7 @@ config MIPS ...@@ -16,6 +16,7 @@ config MIPS
select BUILDTIME_EXTABLE_SORT select BUILDTIME_EXTABLE_SORT
select CLONE_BACKWARDS select CLONE_BACKWARDS
select CPU_PM if CPU_IDLE select CPU_PM if CPU_IDLE
select DMA_DIRECT_OPS
select GENERIC_ATOMIC64 if !64BIT select GENERIC_ATOMIC64 if !64BIT
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select GENERIC_CMOS_UPDATE select GENERIC_CMOS_UPDATE
...@@ -97,6 +98,7 @@ config MIPS_GENERIC ...@@ -97,6 +98,7 @@ config MIPS_GENERIC
select HW_HAS_PCI select HW_HAS_PCI
select IRQ_MIPS_CPU select IRQ_MIPS_CPU
select LIBFDT select LIBFDT
select MIPS_AUTO_PFN_OFFSET
select MIPS_CPU_SCACHE select MIPS_CPU_SCACHE
select MIPS_GIC select MIPS_GIC
select MIPS_L1_CACHE_SHIFT_7 select MIPS_L1_CACHE_SHIFT_7
...@@ -193,6 +195,7 @@ config ATH79 ...@@ -193,6 +195,7 @@ config ATH79
select CSRC_R4K select CSRC_R4K
select DMA_NONCOHERENT select DMA_NONCOHERENT
select GPIOLIB select GPIOLIB
select PINCTRL
select HAVE_CLK select HAVE_CLK
select COMMON_CLK select COMMON_CLK
select CLKDEV_LOOKUP select CLKDEV_LOOKUP
...@@ -211,6 +214,8 @@ config ATH79 ...@@ -211,6 +214,8 @@ config ATH79
config BMIPS_GENERIC config BMIPS_GENERIC
bool "Broadcom Generic BMIPS kernel" bool "Broadcom Generic BMIPS kernel"
select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
select ARCH_HAS_PHYS_TO_DMA
select BOOT_RAW select BOOT_RAW
select NO_EXCEPT_FILL select NO_EXCEPT_FILL
select USE_OF select USE_OF
...@@ -438,7 +443,6 @@ config MACH_LOONGSON32 ...@@ -438,7 +443,6 @@ config MACH_LOONGSON32
config MACH_LOONGSON64 config MACH_LOONGSON64
bool "Loongson-2/3 family of machines" bool "Loongson-2/3 family of machines"
select ARCH_HAS_PHYS_TO_DMA
select SYS_SUPPORTS_ZBOOT select SYS_SUPPORTS_ZBOOT
help help
This enables the support of Loongson-2/3 family of machines. This enables the support of Loongson-2/3 family of machines.
...@@ -662,11 +666,11 @@ config SGI_IP22 ...@@ -662,11 +666,11 @@ config SGI_IP22
config SGI_IP27 config SGI_IP27
bool "SGI IP27 (Origin200/2000)" bool "SGI IP27 (Origin200/2000)"
select ARCH_HAS_PHYS_TO_DMA
select FW_ARC select FW_ARC
select FW_ARC64 select FW_ARC64
select BOOT_ELF64 select BOOT_ELF64
select DEFAULT_SGI_PARTITION select DEFAULT_SGI_PARTITION
select DMA_COHERENT
select SYS_HAS_EARLY_PRINTK select SYS_HAS_EARLY_PRINTK
select HW_HAS_PCI select HW_HAS_PCI
select NR_CPUS_DEFAULT_64 select NR_CPUS_DEFAULT_64
...@@ -721,6 +725,7 @@ config SGI_IP28 ...@@ -721,6 +725,7 @@ config SGI_IP28
config SGI_IP32 config SGI_IP32
bool "SGI IP32 (O2)" bool "SGI IP32 (O2)"
select ARCH_HAS_PHYS_TO_DMA
select FW_ARC select FW_ARC
select FW_ARC32 select FW_ARC32
select BOOT_ELF32 select BOOT_ELF32
...@@ -743,7 +748,6 @@ config SGI_IP32 ...@@ -743,7 +748,6 @@ config SGI_IP32
config SIBYTE_CRHINE config SIBYTE_CRHINE
bool "Sibyte BCM91120C-CRhine" bool "Sibyte BCM91120C-CRhine"
select BOOT_ELF32 select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1120 select SIBYTE_BCM1120
select SWAP_IO_SPACE select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1 select SYS_HAS_CPU_SB1
...@@ -753,7 +757,6 @@ config SIBYTE_CRHINE ...@@ -753,7 +757,6 @@ config SIBYTE_CRHINE
config SIBYTE_CARMEL config SIBYTE_CARMEL
bool "Sibyte BCM91120x-Carmel" bool "Sibyte BCM91120x-Carmel"
select BOOT_ELF32 select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1120 select SIBYTE_BCM1120
select SWAP_IO_SPACE select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1 select SYS_HAS_CPU_SB1
...@@ -763,7 +766,6 @@ config SIBYTE_CARMEL ...@@ -763,7 +766,6 @@ config SIBYTE_CARMEL
config SIBYTE_CRHONE config SIBYTE_CRHONE
bool "Sibyte BCM91125C-CRhone" bool "Sibyte BCM91125C-CRhone"
select BOOT_ELF32 select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1125 select SIBYTE_BCM1125
select SWAP_IO_SPACE select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1 select SYS_HAS_CPU_SB1
...@@ -774,7 +776,6 @@ config SIBYTE_CRHONE ...@@ -774,7 +776,6 @@ config SIBYTE_CRHONE
config SIBYTE_RHONE config SIBYTE_RHONE
bool "Sibyte BCM91125E-Rhone" bool "Sibyte BCM91125E-Rhone"
select BOOT_ELF32 select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1125H select SIBYTE_BCM1125H
select SWAP_IO_SPACE select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1 select SYS_HAS_CPU_SB1
...@@ -784,7 +785,6 @@ config SIBYTE_RHONE ...@@ -784,7 +785,6 @@ config SIBYTE_RHONE
config SIBYTE_SWARM config SIBYTE_SWARM
bool "Sibyte BCM91250A-SWARM" bool "Sibyte BCM91250A-SWARM"
select BOOT_ELF32 select BOOT_ELF32
select DMA_COHERENT
select HAVE_PATA_PLATFORM select HAVE_PATA_PLATFORM
select SIBYTE_SB1250 select SIBYTE_SB1250
select SWAP_IO_SPACE select SWAP_IO_SPACE
...@@ -797,7 +797,6 @@ config SIBYTE_SWARM ...@@ -797,7 +797,6 @@ config SIBYTE_SWARM
config SIBYTE_LITTLESUR config SIBYTE_LITTLESUR
bool "Sibyte BCM91250C2-LittleSur" bool "Sibyte BCM91250C2-LittleSur"
select BOOT_ELF32 select BOOT_ELF32
select DMA_COHERENT
select HAVE_PATA_PLATFORM select HAVE_PATA_PLATFORM
select SIBYTE_SB1250 select SIBYTE_SB1250
select SWAP_IO_SPACE select SWAP_IO_SPACE
...@@ -809,7 +808,6 @@ config SIBYTE_LITTLESUR ...@@ -809,7 +808,6 @@ config SIBYTE_LITTLESUR
config SIBYTE_SENTOSA config SIBYTE_SENTOSA
bool "Sibyte BCM91250E-Sentosa" bool "Sibyte BCM91250E-Sentosa"
select BOOT_ELF32 select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_SB1250 select SIBYTE_SB1250
select SWAP_IO_SPACE select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1 select SYS_HAS_CPU_SB1
...@@ -819,7 +817,6 @@ config SIBYTE_SENTOSA ...@@ -819,7 +817,6 @@ config SIBYTE_SENTOSA
config SIBYTE_BIGSUR config SIBYTE_BIGSUR
bool "Sibyte BCM91480B-BigSur" bool "Sibyte BCM91480B-BigSur"
select BOOT_ELF32 select BOOT_ELF32
select DMA_COHERENT
select NR_CPUS_DEFAULT_4 select NR_CPUS_DEFAULT_4
select SIBYTE_BCM1x80 select SIBYTE_BCM1x80
select SWAP_IO_SPACE select SWAP_IO_SPACE
...@@ -895,8 +892,8 @@ config CAVIUM_OCTEON_SOC ...@@ -895,8 +892,8 @@ config CAVIUM_OCTEON_SOC
bool "Cavium Networks Octeon SoC based boards" bool "Cavium Networks Octeon SoC based boards"
select CEVT_R4K select CEVT_R4K
select ARCH_HAS_PHYS_TO_DMA select ARCH_HAS_PHYS_TO_DMA
select HAS_RAPIDIO
select PHYS_ADDR_T_64BIT select PHYS_ADDR_T_64BIT
select DMA_COHERENT
select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN
select EDAC_SUPPORT select EDAC_SUPPORT
...@@ -945,7 +942,6 @@ config NLM_XLR_BOARD ...@@ -945,7 +942,6 @@ config NLM_XLR_BOARD
select PHYS_ADDR_T_64BIT select PHYS_ADDR_T_64BIT
select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_HIGHMEM
select DMA_COHERENT
select NR_CPUS_DEFAULT_32 select NR_CPUS_DEFAULT_32
select CEVT_R4K select CEVT_R4K
select CSRC_R4K select CSRC_R4K
...@@ -973,7 +969,6 @@ config NLM_XLP_BOARD ...@@ -973,7 +969,6 @@ config NLM_XLP_BOARD
select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_HIGHMEM
select DMA_COHERENT
select NR_CPUS_DEFAULT_32 select NR_CPUS_DEFAULT_32
select CEVT_R4K select CEVT_R4K
select CSRC_R4K select CSRC_R4K
...@@ -992,7 +987,6 @@ config MIPS_PARAVIRT ...@@ -992,7 +987,6 @@ config MIPS_PARAVIRT
bool "Para-Virtualized guest system" bool "Para-Virtualized guest system"
select CEVT_R4K select CEVT_R4K
select CSRC_R4K select CSRC_R4K
select DMA_COHERENT
select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN
...@@ -1118,12 +1112,14 @@ config DMA_PERDEV_COHERENT ...@@ -1118,12 +1112,14 @@ config DMA_PERDEV_COHERENT
bool bool
select DMA_MAYBE_COHERENT select DMA_MAYBE_COHERENT
config DMA_COHERENT
bool
config DMA_NONCOHERENT config DMA_NONCOHERENT
bool bool
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_HAS_SYNC_DMA_FOR_CPU
select NEED_DMA_MAP_STATE select NEED_DMA_MAP_STATE
select DMA_NONCOHERENT_MMAP
select DMA_NONCOHERENT_CACHE_SYNC
select DMA_NONCOHERENT_OPS
config SYS_HAS_EARLY_PRINTK config SYS_HAS_EARLY_PRINTK
bool bool
...@@ -1365,6 +1361,7 @@ choice ...@@ -1365,6 +1361,7 @@ choice
config CPU_LOONGSON3 config CPU_LOONGSON3
bool "Loongson 3 CPU" bool "Loongson 3 CPU"
depends on SYS_HAS_CPU_LOONGSON3 depends on SYS_HAS_CPU_LOONGSON3
select ARCH_HAS_PHYS_TO_DMA
select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES select CPU_SUPPORTS_HUGEPAGES
...@@ -1427,7 +1424,8 @@ config CPU_LOONGSON1B ...@@ -1427,7 +1424,8 @@ config CPU_LOONGSON1B
select LEDS_GPIO_REGISTER select LEDS_GPIO_REGISTER
help help
The Loongson 1B is a 32-bit SoC, which implements the MIPS32 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
release 2 instruction set. Release 1 instruction set and part of the MIPS32 Release 2
instruction set.
config CPU_LOONGSON1C config CPU_LOONGSON1C
bool "Loongson 1C" bool "Loongson 1C"
...@@ -1436,7 +1434,8 @@ config CPU_LOONGSON1C ...@@ -1436,7 +1434,8 @@ config CPU_LOONGSON1C
select LEDS_GPIO_REGISTER select LEDS_GPIO_REGISTER
help help
The Loongson 1C is a 32-bit SoC, which implements the MIPS32 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
release 2 instruction set. Release 1 instruction set and part of the MIPS32 Release 2
instruction set.
config CPU_MIPS32_R1 config CPU_MIPS32_R1
bool "MIPS32 Release 1" bool "MIPS32 Release 1"
...@@ -1831,11 +1830,12 @@ config CPU_LOONGSON2 ...@@ -1831,11 +1830,12 @@ config CPU_LOONGSON2
select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES select CPU_SUPPORTS_HUGEPAGES
select ARCH_HAS_PHYS_TO_DMA
config CPU_LOONGSON1 config CPU_LOONGSON1
bool bool
select CPU_MIPS32 select CPU_MIPS32
select CPU_MIPSR2 select CPU_MIPSR1
select CPU_HAS_PREFETCH select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HIGHMEM
...@@ -1979,12 +1979,6 @@ config SYS_HAS_CPU_XLR ...@@ -1979,12 +1979,6 @@ config SYS_HAS_CPU_XLR
config SYS_HAS_CPU_XLP config SYS_HAS_CPU_XLP
bool bool
config MIPS_MALTA_PM
depends on MIPS_MALTA
depends on PCI
bool
default y
# #
# CPU may reorder R->R, R->W, W->R, W->W # CPU may reorder R->R, R->W, W->R, W->W
# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
...@@ -2994,6 +2988,9 @@ config PGTABLE_LEVELS ...@@ -2994,6 +2988,9 @@ config PGTABLE_LEVELS
default 3 if 64BIT && !PAGE_SIZE_64KB default 3 if 64BIT && !PAGE_SIZE_64KB
default 2 default 2
config MIPS_AUTO_PFN_OFFSET
bool
source "init/Kconfig" source "init/Kconfig"
source "kernel/Kconfig.freezer" source "kernel/Kconfig.freezer"
...@@ -3115,10 +3112,13 @@ config ZONE_DMA32 ...@@ -3115,10 +3112,13 @@ config ZONE_DMA32
source "drivers/pcmcia/Kconfig" source "drivers/pcmcia/Kconfig"
config HAS_RAPIDIO
bool
default n
config RAPIDIO config RAPIDIO
tristate "RapidIO support" tristate "RapidIO support"
depends on PCI depends on HAS_RAPIDIO || PCI
default n
help help
If you say Y here, the kernel will include drivers and If you say Y here, the kernel will include drivers and
infrastructure code to support RapidIO interconnect devices. infrastructure code to support RapidIO interconnect devices.
......
...@@ -122,12 +122,22 @@ cflags-y += -ffreestanding ...@@ -122,12 +122,22 @@ cflags-y += -ffreestanding
# are used, so we kludge that here. A bug has been filed at # are used, so we kludge that here. A bug has been filed at
# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29413. # http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29413.
# #
# clang doesn't suffer from these issues and our checks against -dumpmachine
# don't work so well when cross compiling, since without providing --target
# clang's output will be based upon the build machine. So for clang we simply
# unconditionally specify -EB or -EL as appropriate.
#
ifeq ($(cc-name),clang)
cflags-$(CONFIG_CPU_BIG_ENDIAN) += -EB
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -EL
else
undef-all += -UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ undef-all += -UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__
undef-all += -UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ undef-all += -UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__
predef-be += -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__ predef-be += -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__
predef-le += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__ predef-le += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__
cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be)) cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be))
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le)) cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
endif
cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
-fno-omit-frame-pointer -fno-omit-frame-pointer
...@@ -155,15 +165,11 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap ...@@ -155,15 +165,11 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap
-Wa,-mips32 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
-Wa,-mips32r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \ cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap
-Wa,-mips64 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
-Wa,-mips64r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap
cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap
cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \ cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \
......
...@@ -34,6 +34,7 @@ ...@@ -34,6 +34,7 @@
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/idle.h> #include <asm/idle.h>
#include <asm/reboot.h> #include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h> #include <asm/mach-au1x00/gpio-au1000.h>
#include <prom.h> #include <prom.h>
...@@ -60,7 +61,7 @@ void __init prom_init(void) ...@@ -60,7 +61,7 @@ void __init prom_init(void)
add_memory_region(0, memsize, BOOT_MEM_RAM); add_memory_region(0, memsize, BOOT_MEM_RAM);
} }
void prom_putchar(unsigned char c) void prom_putchar(char c)
{ {
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
} }
......
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#include <mtd/mtd-abi.h> #include <mtd/mtd-abi.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/reboot.h> #include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h> #include <asm/mach-au1x00/gpio-au1000.h>
#include <asm/mach-au1x00/au1xxx_eth.h> #include <asm/mach-au1x00/au1xxx_eth.h>
...@@ -58,7 +59,7 @@ void __init prom_init(void) ...@@ -58,7 +59,7 @@ void __init prom_init(void)
add_memory_region(0, memsize, BOOT_MEM_RAM); add_memory_region(0, memsize, BOOT_MEM_RAM);
} }
void prom_putchar(unsigned char c) void prom_putchar(char c)
{ {
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
} }
......
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#include <linux/pm.h> #include <linux/pm.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/reboot.h> #include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
#include <prom.h> #include <prom.h>
...@@ -55,7 +56,7 @@ void __init prom_init(void) ...@@ -55,7 +56,7 @@ void __init prom_init(void)
add_memory_region(0, memsize, BOOT_MEM_RAM); add_memory_region(0, memsize, BOOT_MEM_RAM);
} }
void prom_putchar(unsigned char c) void prom_putchar(char c)
{ {
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
} }
......
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/idle.h> #include <asm/idle.h>
#include <asm/reboot.h> #include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h> #include <asm/mach-db1x00/bcsr.h>
...@@ -36,7 +37,7 @@ void __init prom_init(void) ...@@ -36,7 +37,7 @@ void __init prom_init(void)
add_memory_region(0, memsize, BOOT_MEM_RAM); add_memory_region(0, memsize, BOOT_MEM_RAM);
} }
void prom_putchar(unsigned char c) void prom_putchar(char c)
{ {
if (alchemy_get_cputype() == ALCHEMY_CPU_AU1300) if (alchemy_get_cputype() == ALCHEMY_CPU_AU1300)
alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
......
...@@ -476,3 +476,32 @@ void __init ar7_init_clocks(void) ...@@ -476,3 +476,32 @@ void __init ar7_init_clocks(void)
/* adjust vbus clock rate */ /* adjust vbus clock rate */
vbus_clk.rate = bus_clk.rate / 2; vbus_clk.rate = bus_clk.rate / 2;
} }
/* dummy functions, should not be called */
long clk_round_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
WARN_ON(clk);
return NULL;
}
EXPORT_SYMBOL(clk_get_parent);
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#include <linux/string.h> #include <linux/string.h>
#include <linux/io.h> #include <linux/io.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/setup.h>
#include <asm/mach-ar7/ar7.h> #include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h> #include <asm/mach-ar7/prom.h>
...@@ -259,10 +260,9 @@ static inline void serial_out(int offset, int value) ...@@ -259,10 +260,9 @@ static inline void serial_out(int offset, int value)
writel(value, (void *)PORT(offset)); writel(value, (void *)PORT(offset));
} }
int prom_putchar(char c) void prom_putchar(char c)
{ {
while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0) while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0)
; ;
serial_out(UART_TX, c); serial_out(UART_TX, c);
return 1;
} }
...@@ -12,6 +12,7 @@ config SOC_AR2315 ...@@ -12,6 +12,7 @@ config SOC_AR2315
config PCI_AR2315 config PCI_AR2315
bool "Atheros AR2315 PCI controller support" bool "Atheros AR2315 PCI controller support"
depends on SOC_AR2315 depends on SOC_AR2315
select ARCH_HAS_PHYS_TO_DMA
select HW_HAS_PCI select HW_HAS_PCI
select PCI select PCI
default y default y
...@@ -146,10 +146,10 @@ int __init ath25_find_config(phys_addr_t base, unsigned long size) ...@@ -146,10 +146,10 @@ int __init ath25_find_config(phys_addr_t base, unsigned long size)
pr_info("Fixing up empty mac addresses\n"); pr_info("Fixing up empty mac addresses\n");
config->reset_config_gpio = 0xffff; config->reset_config_gpio = 0xffff;
config->sys_led_gpio = 0xffff; config->sys_led_gpio = 0xffff;
random_ether_addr(config->wlan0_mac); eth_random_addr(config->wlan0_mac);
config->wlan0_mac[0] &= ~0x06; config->wlan0_mac[0] &= ~0x06;
random_ether_addr(config->enet0_mac); eth_random_addr(config->enet0_mac);
random_ether_addr(config->enet1_mac); eth_random_addr(config->enet1_mac);
} }
} }
......
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/serial_reg.h> #include <linux/serial_reg.h>
#include <asm/setup.h>
#include "devices.h" #include "devices.h"
#include "ar2315_regs.h" #include "ar2315_regs.h"
...@@ -25,7 +26,7 @@ static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) ...@@ -25,7 +26,7 @@ static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg)
return __raw_readl(base + 4 * reg); return __raw_readl(base + 4 * reg);
} }
void prom_putchar(unsigned char ch) void prom_putchar(char ch)
{ {
static void __iomem *base; static void __iomem *base;
...@@ -38,7 +39,7 @@ void prom_putchar(unsigned char ch) ...@@ -38,7 +39,7 @@ void prom_putchar(unsigned char ch)
while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
; ;
prom_uart_wr(base, UART_TX, ch); prom_uart_wr(base, UART_TX, (unsigned char)ch);
while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
; ;
} }
...@@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(void) ...@@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(void)
iounmap(dpll_base); iounmap(dpll_base);
} }
static void __init qca953x_clocks_init(void)
{
unsigned long ref_rate;
unsigned long cpu_rate;
unsigned long ddr_rate;
unsigned long ahb_rate;
u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
u32 cpu_pll, ddr_pll;
u32 bootstrap;
bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
ref_rate = 40 * 1000 * 1000;
else
ref_rate = 25 * 1000 * 1000;
pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
QCA953X_PLL_CPU_CONFIG_NINT_MASK;
frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
cpu_pll = nint * ref_rate / ref_div;
cpu_pll += frac * (ref_rate >> 6) / ref_div;
cpu_pll /= (1 << out_div);
pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
QCA953X_PLL_DDR_CONFIG_NINT_MASK;
frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
ddr_pll = nint * ref_rate / ref_div;
ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
ddr_pll /= (1 << out_div);
clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
cpu_rate = ref_rate;
else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
cpu_rate = cpu_pll / (postdiv + 1);
else
cpu_rate = ddr_pll / (postdiv + 1);
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
ddr_rate = ref_rate;
else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
ddr_rate = ddr_pll / (postdiv + 1);
else
ddr_rate = cpu_pll / (postdiv + 1);
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
ahb_rate = ref_rate;
else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
ahb_rate = ddr_pll / (postdiv + 1);
else
ahb_rate = cpu_pll / (postdiv + 1);
ath79_add_sys_clkdev("ref", ref_rate);
ath79_add_sys_clkdev("cpu", cpu_rate);
ath79_add_sys_clkdev("ddr", ddr_rate);
ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
}
static void __init qca955x_clocks_init(void) static void __init qca955x_clocks_init(void)
{ {
unsigned long ref_rate; unsigned long ref_rate;
...@@ -440,6 +525,110 @@ static void __init qca955x_clocks_init(void) ...@@ -440,6 +525,110 @@ static void __init qca955x_clocks_init(void)
clk_add_alias("uart", NULL, "ref", NULL); clk_add_alias("uart", NULL, "ref", NULL);
} }
static void __init qca956x_clocks_init(void)
{
unsigned long ref_rate;
unsigned long cpu_rate;
unsigned long ddr_rate;
unsigned long ahb_rate;
u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
u32 cpu_pll, ddr_pll;
u32 bootstrap;
/*
* QCA956x timer init workaround has to be applied right before setting
* up the clock. Else, there will be no jiffies
*/
u32 misc;
misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
ref_rate = 40 * 1000 * 1000;
else
ref_rate = 25 * 1000 * 1000;
pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
cpu_pll = nint * ref_rate / ref_div;
cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
cpu_pll /= (1 << out_div);
pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
ddr_pll = nint * ref_rate / ref_div;
ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
ddr_pll /= (1 << out_div);
clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
cpu_rate = ref_rate;
else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
cpu_rate = ddr_pll / (postdiv + 1);
else
cpu_rate = cpu_pll / (postdiv + 1);
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
ddr_rate = ref_rate;
else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
ddr_rate = cpu_pll / (postdiv + 1);
else
ddr_rate = ddr_pll / (postdiv + 1);
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
ahb_rate = ref_rate;
else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
ahb_rate = ddr_pll / (postdiv + 1);
else
ahb_rate = cpu_pll / (postdiv + 1);
ath79_add_sys_clkdev("ref", ref_rate);
ath79_add_sys_clkdev("cpu", cpu_rate);
ath79_add_sys_clkdev("ddr", ddr_rate);
ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
}
void __init ath79_clocks_init(void) void __init ath79_clocks_init(void)
{ {
if (soc_is_ar71xx()) if (soc_is_ar71xx())
...@@ -450,8 +639,12 @@ void __init ath79_clocks_init(void) ...@@ -450,8 +639,12 @@ void __init ath79_clocks_init(void)
ar933x_clocks_init(); ar933x_clocks_init();
else if (soc_is_ar934x()) else if (soc_is_ar934x())
ar934x_clocks_init(); ar934x_clocks_init();
else if (soc_is_qca953x())
qca953x_clocks_init();
else if (soc_is_qca955x()) else if (soc_is_qca955x())
qca955x_clocks_init(); qca955x_clocks_init();
else if (soc_is_qca956x() || soc_is_tp9343())
qca956x_clocks_init();
else else
BUG(); BUG();
} }
......
...@@ -103,8 +103,12 @@ void ath79_device_reset_set(u32 mask) ...@@ -103,8 +103,12 @@ void ath79_device_reset_set(u32 mask)
reg = AR933X_RESET_REG_RESET_MODULE; reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x()) else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE; reg = AR934X_RESET_REG_RESET_MODULE;
else if (soc_is_qca953x())
reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x()) else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE; reg = QCA955X_RESET_REG_RESET_MODULE;
else if (soc_is_qca956x() || soc_is_tp9343())
reg = QCA956X_RESET_REG_RESET_MODULE;
else else
BUG(); BUG();
...@@ -131,8 +135,12 @@ void ath79_device_reset_clear(u32 mask) ...@@ -131,8 +135,12 @@ void ath79_device_reset_clear(u32 mask)
reg = AR933X_RESET_REG_RESET_MODULE; reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x()) else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE; reg = AR934X_RESET_REG_RESET_MODULE;
else if (soc_is_qca953x())
reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x()) else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE; reg = QCA955X_RESET_REG_RESET_MODULE;
else if (soc_is_qca956x() || soc_is_tp9343())
reg = QCA956X_RESET_REG_RESET_MODULE;
else else
BUG(); BUG();
......
...@@ -13,12 +13,13 @@ ...@@ -13,12 +13,13 @@
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/serial_reg.h> #include <linux/serial_reg.h>
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/setup.h>
#include <asm/mach-ath79/ath79.h> #include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h> #include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ar933x_uart.h> #include <asm/mach-ath79/ar933x_uart.h>
static void (*_prom_putchar) (unsigned char); static void (*_prom_putchar)(char);
static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
{ {
...@@ -33,31 +34,72 @@ static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) ...@@ -33,31 +34,72 @@ static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
static void prom_putchar_ar71xx(unsigned char ch) static void prom_putchar_ar71xx(char ch)
{ {
void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY); prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
__raw_writel(ch, base + UART_TX * 4); __raw_writel((unsigned char)ch, base + UART_TX * 4);
prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY); prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
} }
static void prom_putchar_ar933x(unsigned char ch) static void prom_putchar_ar933x(char ch)
{ {
void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE)); void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
AR933X_UART_DATA_TX_CSR); AR933X_UART_DATA_TX_CSR);
__raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG); __raw_writel(AR933X_UART_DATA_TX_CSR | (unsigned char)ch,
base + AR933X_UART_DATA_REG);
prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
AR933X_UART_DATA_TX_CSR); AR933X_UART_DATA_TX_CSR);
} }
static void prom_putchar_dummy(unsigned char ch) static void prom_putchar_dummy(char ch)
{ {
/* nothing to do */ /* nothing to do */
} }
static void prom_enable_uart(u32 id)
{
void __iomem *gpio_base;
u32 uart_en;
u32 t;
switch (id) {
case REV_ID_MAJOR_AR71XX:
uart_en = AR71XX_GPIO_FUNC_UART_EN;
break;
case REV_ID_MAJOR_AR7240:
case REV_ID_MAJOR_AR7241:
case REV_ID_MAJOR_AR7242:
uart_en = AR724X_GPIO_FUNC_UART_EN;
break;
case REV_ID_MAJOR_AR913X:
uart_en = AR913X_GPIO_FUNC_UART_EN;
break;
case REV_ID_MAJOR_AR9330:
case REV_ID_MAJOR_AR9331:
uart_en = AR933X_GPIO_FUNC_UART_EN;
break;
case REV_ID_MAJOR_AR9341:
case REV_ID_MAJOR_AR9342:
case REV_ID_MAJOR_AR9344:
/* TODO */
default:
return;
}
gpio_base = (void __iomem *)KSEG1ADDR(AR71XX_GPIO_BASE);
t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
t |= uart_en;
__raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
}
static void prom_putchar_init(void) static void prom_putchar_init(void)
{ {
void __iomem *base; void __iomem *base;
...@@ -76,8 +118,12 @@ static void prom_putchar_init(void) ...@@ -76,8 +118,12 @@ static void prom_putchar_init(void)
case REV_ID_MAJOR_AR9341: case REV_ID_MAJOR_AR9341:
case REV_ID_MAJOR_AR9342: case REV_ID_MAJOR_AR9342:
case REV_ID_MAJOR_AR9344: case REV_ID_MAJOR_AR9344:
case REV_ID_MAJOR_QCA9533:
case REV_ID_MAJOR_QCA9533_V2:
case REV_ID_MAJOR_QCA9556: case REV_ID_MAJOR_QCA9556:
case REV_ID_MAJOR_QCA9558: case REV_ID_MAJOR_QCA9558:
case REV_ID_MAJOR_TP9343:
case REV_ID_MAJOR_QCA956X:
_prom_putchar = prom_putchar_ar71xx; _prom_putchar = prom_putchar_ar71xx;
break; break;
...@@ -88,11 +134,13 @@ static void prom_putchar_init(void) ...@@ -88,11 +134,13 @@ static void prom_putchar_init(void)
default: default:
_prom_putchar = prom_putchar_dummy; _prom_putchar = prom_putchar_dummy;
break; return;
} }
prom_enable_uart(id);
} }
void prom_putchar(unsigned char ch) void prom_putchar(char ch)
{ {
if (!_prom_putchar) if (!_prom_putchar)
prom_putchar_init(); prom_putchar_init();
......
...@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; ...@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
static void ath79_restart(char *command) static void ath79_restart(char *command)
{ {
local_irq_disable();
ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
for (;;) for (;;)
if (cpu_wait) if (cpu_wait)
...@@ -59,6 +60,7 @@ static void __init ath79_detect_sys_type(void) ...@@ -59,6 +60,7 @@ static void __init ath79_detect_sys_type(void)
u32 major; u32 major;
u32 minor; u32 minor;
u32 rev = 0; u32 rev = 0;
u32 ver = 1;
id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
major = id & REV_ID_MAJOR_MASK; major = id & REV_ID_MAJOR_MASK;
...@@ -151,6 +153,17 @@ static void __init ath79_detect_sys_type(void) ...@@ -151,6 +153,17 @@ static void __init ath79_detect_sys_type(void)
rev = id & AR934X_REV_ID_REVISION_MASK; rev = id & AR934X_REV_ID_REVISION_MASK;
break; break;
case REV_ID_MAJOR_QCA9533_V2:
ver = 2;
ath79_soc_rev = 2;
/* drop through */
case REV_ID_MAJOR_QCA9533:
ath79_soc = ATH79_SOC_QCA9533;
chip = "9533";
rev = id & QCA953X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_QCA9556: case REV_ID_MAJOR_QCA9556:
ath79_soc = ATH79_SOC_QCA9556; ath79_soc = ATH79_SOC_QCA9556;
chip = "9556"; chip = "9556";
...@@ -163,14 +176,30 @@ static void __init ath79_detect_sys_type(void) ...@@ -163,14 +176,30 @@ static void __init ath79_detect_sys_type(void)
rev = id & QCA955X_REV_ID_REVISION_MASK; rev = id & QCA955X_REV_ID_REVISION_MASK;
break; break;
case REV_ID_MAJOR_QCA956X:
ath79_soc = ATH79_SOC_QCA956X;
chip = "956X";
rev = id & QCA956X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_TP9343:
ath79_soc = ATH79_SOC_TP9343;
chip = "9343";
rev = id & QCA956X_REV_ID_REVISION_MASK;
break;
default: default:
panic("ath79: unknown SoC, id:0x%08x", id); panic("ath79: unknown SoC, id:0x%08x", id);
} }
if (ver == 1)
ath79_soc_rev = rev; ath79_soc_rev = rev;
if (soc_is_qca955x()) if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
chip, ver, rev);
else if (soc_is_tp9343())
sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
chip, rev); chip, rev);
else else
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
......
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
#include <bcm63xx_io.h> #include <bcm63xx_io.h>
#include <linux/serial_bcm63xx.h> #include <linux/serial_bcm63xx.h>
#include <asm/setup.h>
static void wait_xfered(void) static void wait_xfered(void)
{ {
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
#include <linux/printk.h> #include <linux/printk.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/types.h> #include <linux/types.h>
#include <dma-coherence.h> #include <asm/bmips.h>
/* /*
* BCM338x has configurable address translation windows which allow the * BCM338x has configurable address translation windows which allow the
...@@ -40,7 +40,7 @@ static struct bmips_dma_range *bmips_dma_ranges; ...@@ -40,7 +40,7 @@ static struct bmips_dma_range *bmips_dma_ranges;
#define FLUSH_RAC 0x100 #define FLUSH_RAC 0x100
static dma_addr_t bmips_phys_to_dma(struct device *dev, phys_addr_t pa) dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t pa)
{ {
struct bmips_dma_range *r; struct bmips_dma_range *r;
...@@ -52,17 +52,7 @@ static dma_addr_t bmips_phys_to_dma(struct device *dev, phys_addr_t pa) ...@@ -52,17 +52,7 @@ static dma_addr_t bmips_phys_to_dma(struct device *dev, phys_addr_t pa)
return pa; return pa;
} }
dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
{
return bmips_phys_to_dma(dev, virt_to_phys(addr));
}
dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
{
return bmips_phys_to_dma(dev, page_to_phys(page));
}
unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
{ {
struct bmips_dma_range *r; struct bmips_dma_range *r;
...@@ -74,6 +64,22 @@ unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) ...@@ -74,6 +64,22 @@ unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
return dma_addr; return dma_addr;
} }
void arch_sync_dma_for_cpu_all(struct device *dev)
{
void __iomem *cbr = BMIPS_GET_CBR();
u32 cfg;
if (boot_cpu_type() != CPU_BMIPS3300 &&
boot_cpu_type() != CPU_BMIPS4350 &&
boot_cpu_type() != CPU_BMIPS4380)
return;
/* Flush stale data out of the readahead cache */
cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
__raw_readl(cbr + BMIPS_RAC_CONFIG);
}
static int __init bmips_init_dma_ranges(void) static int __init bmips_init_dma_ranges(void)
{ {
struct device_node *np = struct device_node *np =
......
...@@ -202,13 +202,6 @@ void __init device_tree_init(void) ...@@ -202,13 +202,6 @@ void __init device_tree_init(void)
of_node_put(np); of_node_put(np);
} }
int __init plat_of_setup(void)
{
return __dt_register_buses("simple-bus", NULL);
}
arch_initcall(plat_of_setup);
static int __init plat_dev_init(void) static int __init plat_dev_init(void)
{ {
of_clk_init(NULL); of_clk_init(NULL);
......
...@@ -105,28 +105,29 @@ $(obj)/uImage: $(obj)/uImage.$(suffix-y) ...@@ -105,28 +105,29 @@ $(obj)/uImage: $(obj)/uImage.$(suffix-y)
# Flattened Image Tree (.itb) images # Flattened Image Tree (.itb) images
# #
targets += vmlinux.itb
targets += vmlinux.gz.itb
targets += vmlinux.bz2.itb
targets += vmlinux.lzma.itb
targets += vmlinux.lzo.itb
ifeq ($(ADDR_BITS),32) ifeq ($(ADDR_BITS),32)
itb_addr_cells = 1 itb_addr_cells = 1
endif endif
ifeq ($(ADDR_BITS),64) ifeq ($(ADDR_BITS),64)
itb_addr_cells = 2 itb_addr_cells = 2
endif endif
targets += vmlinux.its.S
quiet_cmd_its_cat = CAT $@ quiet_cmd_its_cat = CAT $@
cmd_its_cat = cat $^ >$@ cmd_its_cat = cat $(filter-out $(PHONY), $^) >$@
$(obj)/vmlinux.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS)) $(obj)/vmlinux.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS)) FORCE
$(call if_changed,its_cat) $(call if_changed,its_cat)
targets += vmlinux.its
targets += vmlinux.gz.its
targets += vmlinux.bz2.its
targets += vmlinux.lzmo.its
targets += vmlinux.lzo.its
quiet_cmd_cpp_its_S = ITS $@ quiet_cmd_cpp_its_S = ITS $@
cmd_cpp_its_S = $(CPP) $(cpp_flags) -P -C -o $@ $< \ cmd_cpp_its_S = $(CPP) -P -C -o $@ $< \
-D__ASSEMBLY__ \
-DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \ -DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \
-DVMLINUX_BINARY="\"$(3)\"" \ -DVMLINUX_BINARY="\"$(3)\"" \
-DVMLINUX_COMPRESSION="\"$(2)\"" \ -DVMLINUX_COMPRESSION="\"$(2)\"" \
...@@ -136,19 +137,25 @@ quiet_cmd_cpp_its_S = ITS $@ ...@@ -136,19 +137,25 @@ quiet_cmd_cpp_its_S = ITS $@
-DADDR_CELLS=$(itb_addr_cells) -DADDR_CELLS=$(itb_addr_cells)
$(obj)/vmlinux.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE $(obj)/vmlinux.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,none,vmlinux.bin) $(call if_changed,cpp_its_S,none,vmlinux.bin)
$(obj)/vmlinux.gz.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE $(obj)/vmlinux.gz.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,gzip,vmlinux.bin.gz) $(call if_changed,cpp_its_S,gzip,vmlinux.bin.gz)
$(obj)/vmlinux.bz2.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE $(obj)/vmlinux.bz2.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,bzip2,vmlinux.bin.bz2) $(call if_changed,cpp_its_S,bzip2,vmlinux.bin.bz2)
$(obj)/vmlinux.lzma.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE $(obj)/vmlinux.lzma.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,lzma,vmlinux.bin.lzma) $(call if_changed,cpp_its_S,lzma,vmlinux.bin.lzma)
$(obj)/vmlinux.lzo.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE $(obj)/vmlinux.lzo.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,lzo,vmlinux.bin.lzo) $(call if_changed,cpp_its_S,lzo,vmlinux.bin.lzo)
targets += vmlinux.itb
targets += vmlinux.gz.itb
targets += vmlinux.bz2.itb
targets += vmlinux.lzma.itb
targets += vmlinux.lzo.itb
quiet_cmd_itb-image = ITB $@ quiet_cmd_itb-image = ITB $@
cmd_itb-image = \ cmd_itb-image = \
...@@ -162,14 +169,5 @@ quiet_cmd_itb-image = ITB $@ ...@@ -162,14 +169,5 @@ quiet_cmd_itb-image = ITB $@
$(obj)/vmlinux.itb: $(obj)/vmlinux.its $(obj)/vmlinux.bin FORCE $(obj)/vmlinux.itb: $(obj)/vmlinux.its $(obj)/vmlinux.bin FORCE
$(call if_changed,itb-image,$<) $(call if_changed,itb-image,$<)
$(obj)/vmlinux.gz.itb: $(obj)/vmlinux.gz.its $(obj)/vmlinux.bin.gz FORCE $(obj)/vmlinux.%.itb: $(obj)/vmlinux.%.its $(obj)/vmlinux.bin.% FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.bz2.itb: $(obj)/vmlinux.bz2.its $(obj)/vmlinux.bin.bz2 FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.lzma.itb: $(obj)/vmlinux.lzma.its $(obj)/vmlinux.bin.lzma FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.lzo.itb: $(obj)/vmlinux.lzo.its $(obj)/vmlinux.bin.lzo FORCE
$(call if_changed,itb-image,$<) $(call if_changed,itb-image,$<)
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